VLSI Systems Design - vada.skku.ac. MicroLab, VLSI-31 (1/61) JMM v1.0 VLSI Systems Design Connection

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  • MicroLab, VLSI-31 (1/61)

    JMM v1.0

    VLSI Systems Design

    Connection and Communication Models

    Goal: You can make the link between the low level connection architectures and the higher level communication models and master their implementation. You are familiar with the most common buses and networks.

  • MicroLab, VLSI-31 (2/61)

    JMM v1.0

    Interprocess Communication

    multitasking systems need mechanisms for communication between tasksreal-time operating systems (RTOS) provide interprocess communication mechanisms in embedded systemsdefinition of process element (PE):

    a piece of software running on an embedded processora hardware unit executing an algorithm implemented for example as a FSM-D architecture model

    interprocess communication is information exchange between processing elements

  • MicroLab, VLSI-31 (3/61)

    JMM v1.0

    Blocking/Non-Blocking Communication

    We distinguish between blocking and non-blocking communication:blocking communication: the process element initiating the communication goes in a waiting state until communication end.non-blocking communication: the process element initiating the communication can execute other useful tasks during an ongoing communication.both types of communication are useful.

  • MicroLab, VLSI-31 (4/61)

    JMM v1.0

    Shared Memory Communication:test-and-set operation

    two major (logically equivalent) communication styles exist:

    shared memorymessage passing

    shared memory communication between processing elements using bus a structuremessage is stored in communication link

    need of atomic test-and-set operations, else:PE 1 reads flag location and sees not busyPE2 reads flag location and sees no busyPE1 sets flag location to busy writing and writes data to the shared locationPE2 erroneously sets flag busy writing and overwrites the data left by PE1

    PE1 PE2sharedlocation

    Memory

    write read

  • MicroLab, VLSI-31 (5/61)

    JMM v1.0

    Shared Memory Communication:Semaphores

    a semaphore is a language level synchronization elementwith semaphores guarded access to shared memory can be realized:

    wait for semaphore: P();P() uses a test-and-set operation to repeatedly test a location that holds a memory lockrelease semaphore: V();V() resets the memory lock

    ...

    /* non-protected memory access is here */P(); /* wait for semaphore */ /* do protected memory access here */V(); /* release semaphore */

    /* non-protected memory access is here */

    ...

  • MicroLab, VLSI-31 (6/61)

    JMM v1.0

    Message Passing Communication

    each communication entity has its own send/receive unitmessage is stored on endpoints of send/receive unit and not in communication link as at shared memory communicationmessage passing is used at applications where units operate relatively autonomous: ex. car control system

    PE1 PE2

    send/receive send/receivemessage

  • MicroLab, VLSI-31 (7/61)

    JMM v1.0

    Signals

    major interprocess communication mechanisms:shared memorymessage passing

    simple interprocess communication mechanism:signal

    a signal does not pass data beyond its existencea signal is analogous to hardware interrupt, but can entirely be implemented in softwarea signal is generated by a process and transmitted to another process by the operating systemsignal have fairly limited functionality:

    CPU exceptions to operating systemoperating system servicestermination of a process

    PE1 OS/PE2

    send receivesignal

  • MicroLab, VLSI-31 (8/61)

    JMM v1.0

    Data Dependencies

    communication processes that execute data exchange at identical rates:

    relationship shown using data dependenciesdata dependencies define a partial ordering of process executiondirected acyclic graph (DAG): task graph

    communication processes that execute data exchange at different rates:

    no one-to-one relation between source and destination of data

    P1

    P2

    P3 P4

    system

    video

    audio

  • MicroLab, VLSI-31 (9/61)

    JMM v1.0

    Deadlocks

    US Kansas legislature law early last century:When two trains approach each other at a crossing, both shall come to a full stop and neither shall start up again until the other has gone.

    Dealing with deadlock problem:ignoring (very popular)detection and recovering (quite popular)preventingavoiding (not applicable)

    P1 P2

    R1 R3

    R2

    P3

  • MicroLab, VLSI-31 (10/61)

    JMM v1.0

    The Four-Cycle-Handshake

    the four-cycle-handshake ensures a correct communication between two devicespredefined master/slave devices

    device 1 is master and initiates communicationdevice 2 is slavesend or receive is possibledata bus is bidirectional

    device 1(master)

    device 2(slave)

    req

    ack

    data

    rw

  • MicroLab, VLSI-31 (11/61)

    JMM v1.0

    The Four-Cycle-Handshake:predefined master/slave

    four-cycle-handshake for data sending:

    four-cycle-handshake for data receiving:

    rw

    req

    data

    ack

    data data stored

    data valid

    requ

    est

    phas

    e

    stor

    eph

    ase

    ackn

    owle

    dge

    phas

    e

    end

    phas

    e

    device 1

    device 2

    rw

    req

    data

    ack

    data

    data stored

    data valid

    requ

    est

    phas

    e

    achn

    owle

    dge

    phas

    e

    stor

    eph

    ase

    end

    phas

    e

    device 1

    device 2

  • MicroLab, VLSI-31 (12/61)

    JMM v1.0

    Bus Allocation

    complex SoC may have sharable resources:memoriesprocessing elementsI/O devicesbuses

    bus allocation principles:allocation on a fixed time schedulebus allocation on the basis of need

    destructive bus allocation (Ethernet: Carrier Sense Multiple Access with Collision Detection CSMD/CD, ...)non-destructive bus allocation (arbitration)

  • MicroLab, VLSI-31 (13/61)

    JMM v1.0

    Bus Arbitration Algorithms

    arbitration is the method to grant the bus to a requesting masterarbitration schemas:

    fixed priority (or rate-monotonic) algorithmround robin algorithm

    A B C D E F G H

    priorities 8 7 6 5 4 3 2 1

    top priority

    A B C D E F G H

    priorities 8 7 6 5 4 3 21

  • MicroLab, VLSI-31 (14/61)

    JMM v1.0

    Typical Processor Bus

    a bus is a collection of wires as well as a protocolmicroprocessor buses build on handshake protocolbasic bus operations are reading and writingsystem clock helps to increase data transfer speed

    processingelement(CPU)

    device 1

    clockr/waddr enaddrdata rdydata

    device 2

    clock

    r/w

    addr en

    addr

    data rdy

    data valid

    addr valid addr valid

    valid

    waitstate

    read write

  • MicroLab, VLSI-31 (15/61)

    JMM v1.0

    Bus With DMA Controller

    direct memory access (DMA) controllers perform direct data transfers between devices without CPU involvementfour-cycle-handshake with processor to get bus master (interrupt processor when finished)used for high speed requirementsto prevent to block the processor too long, partial block transfer mode possible, 16, 32 or 256 words for example. bus DMA controller is a bus with 2 masters

    processingelement(CPU)

    DMAcontroller

    clockr/waddr enaddrdata rdydata

    device 1

    busrequest

    busgrant

    device 2

  • MicroLab, VLSI-31 (16/61)

    JMM v1.0

    System Bus

    embedded systems-on-chip use bus hierarchies:Avalon from Altera Inc., used for Nios (simple)AMBATM bus from AMD Inc., used for ARMTM

    CoreConnectTM from IBM Inc., used for PowerPCTM

    features:high-speed buses provide wider data connectionshigh-speed buses require more expensive circuitry and connectors. The cost of low-speed devices can be held down by using lower-speed, lower-cost bus.The bridge may allow the buses to operate independently, thereby providing some parallelism in processing an I/O operations.

    bus bridge: slave at fast bus, master at slow bus

    CPU

    memoryhigh-speedprocessing

    element

    brid

    ge

    low-speedI/O device

    low-speedprocessing

    element

    high-speed bus low-speed bus

  • MicroLab, VLSI-31 (17/61)

    JMM v1.0

    The AMBA System Bus

    advanced high-performance bus (AHB)high-performancepipelined operationmultiple bus masterburst transfersplit transactions

    advanced high-performance system bus (ASB)dito, but no split transactions

    advanced peripheral bus (APB)low-powerlatched address and controlsimple interfacesuitable for many peripherals

    CPU

    on-chip RAM(high-

    bandwidth)

    processingelement

    (high-speed)

    brid

    ge

    UART

    AHB or ASB APB

    DMA

    Timer

    PIO Keypadexternalmemoryinterface

    (high-band-width)

  • MicroLab, VLSI-31 (18/61)

    JMM v1.0

    Advanced High-Performance Bus (AHB)

    The AHB bus consists of the following elements:

    AHB master: able to initiate read and write transfersonly one bus master is allowed to control the bus

    AHB slave:responds to read and write operations in a given address spacesignals back to the master: success, failure or waiting of the data transfer

    AHB arbiter:ensures that only one master at a time is allowed to control busany arbitration algorithm can be used, like highest priority, fair access, etc

    AHB decoder:decodes address and generates device select signalssingle centralized decoder is required

  • MicroLab, VLSI-31 (19/61)

    JMM v1.0

    Basic AHB Interconnection Schemaarbiter determi