Organized By:

The course will cover an overview of electronic testing, automated model gen-eration for high level fault modelling (HLFM), system level testing for complex system-on-chips including design-for-testability and core-based test scheduling. The topics of logic built-in self-test (LBIST) will also be covered, with an exam-ple LBIST implementation case study looking at several low power techniques. Participants will get an opportunity to have hands-on experience on high-level automated model generation using software provided from Mentor Graphics.

Facilitators

Dr Fawnizu Azmadi Hussin is an Asso-

ciate Professor at the Universiti

Teknologi PETRONAS (UTP), Malay-

sia. He was the program manager of

Master by coursework program at UTP

(2009-2013) and the Deputy Head of

Electrical & Electronic Engineering

department at UTP since 2013. He ob-

tained the Bachelor of Electrical Engineering (Computer

Design) from the University of Minnesota, Twin Cities,

U.S.A. in 1999 and subsequently his M.Eng.Sc. in Sys-

tems and Control from the University of New South

Wales, Australia in 2001. Dr Fawnizu completed his PhD

in 2008 at the Nara Institute of Science and Technology in

Japan under the scholarship from the Japanese Govern-

ment (Monbukagakusho). His PhD thesis was on core-

based testing of system-on-chips (SOC) and network-on-

chips (NOC), which won an award ASP-DAC 2008 Stu-

dent Forum. Dr Fawnizu’s research interests are in VLSI

design and test especially in core-based testing, SOC and

NOC. Dr Fawnizu currently works on functional debug of

integrated circuits and on test program generation for soft-

ware-based self-test. He is actively involved with the

IEEE Malaysia Section. He is the 2013 Chair of the IEEE

Circuits and Systems Society Malaysia Chapter. Mr. Dileep Kumar (Research Scientist), CISIR, UTP,

Email: dileep.utp@gmail.com Phone: 0195591650

For Any Further Information, Please contact

Targeted Audience: The one-day short course targets to Electronic engineers, Researchers, Postgraduate Students, and Industry Re-searchers

Dr. Likun Xia Received his MSc de-

gree from the University of Newcastle,

UK in September 2001, and PhD in

2009 in VLSI Design and Test Group

at the University of Hull, UK. He is

currently a senior Lecturer/Researcher

at Electrical & Electronic Engineering

Department, Universiti Teknologi PETRONAS (UTP),

Malaysia. He is a member of IEEE CAS and EAGE.

He is interested in mathematical behaviour modeling for

various applications including high level fault modeling

for analogue and mix-signal circuit and system; bio-

marker development inNeuroscience on stress and de-

pression issues; and seismic imaging on fractured reser-

voir.

He has published various publications in top-tier jour-

nals including IEEE TCAD, JETTA, and also attended

international conferences such as ISCAS, EMBC, and

ASP-DAC.

Venue:

1 DAY SHORT COURSE

ON

VLSI SYSTEM MODELLING AND TEST 24 Dec,2013 || Venue: CISIR, Bandar Seri Iskandar, UTP

Centre for Intelligent Signal and Imaging Research (CISIR)

Universiti Teknologi Petronas

Bandar Seri Iskandar, Tronoh

31750, Perak, Malaysia

Fees for Participants from Malaysian Universities

For On-line transaction and cash deposit to ITP account, please use

the account information below

INSTITUTE OF TEKNOLOGI PETRONAS SDN BHD (352875-U):

0809-0004124-054 (CIMB Bank Berhad, Batu Gajah)

Kindly fill the registration form and send a scan copy of filled form

to one of the below e‐mails:

dileep.utp@gmail.com or cisirutp@gmail.com

Note: - Registration should be completed 4 days before course

commencement. First-come, first-served policy is implemented due

to limited seats

Accommodation

Participants are required to make their own arrange-

ments for accommodation near by Venue.

To introduce basic difficulty faced by semiconductor industries and

the concepts of faults in analogues and/or digital circuits and sys-

tems

To explain various types of fault-free and faulty models for ana-

logues and mixed circuits and systems

To compare the benefits of modular testing against conventional

monolithic testing

To apply the concept of modular test methodology for complex

system-on-chip (SOC)

To explore the use of logic BIST for testing of complex SOC.

Programme Schedule

Objectives Registration Form

IEEE Student Member/Full IEEE CAS Member RM 650

Student Non-Member RM 700

Full IEEE Member RM 700

Non-Member. RM 750

The fee is per person and includes lunch, refreshments and short course materials only. A certificate of attendance will be given at the end of the course. Participants are required to bring their own Laptop.

Mr. Dileep Kumar (Research Scientist)

Centre for Intelligent Signal and Imaging (CISIR),

Universiti Teknologi Petronas, Malaysia dileep.utp@gmail.com

or dileep.kumar@petronas.com.my

Phone/Mobile : 0195591650

For Any Further Information, Please contact

Day 1:

08:00 Registration & Opening Remarks

09:00

Review of Automated Model Genera-

tion Approaches for High Level Fault

Modelingin Analogue and Mixed-Signal

Systems

10:30 Tea break

11:00

Practical session: Performing of High

level modelling and high level fault

modelling using Mentor Graphics soft-

ware

12:30 Lunch Break

14:00

Introduction to SOC testing

Challenges in SOC testing

Motivation for modular testing of

SOCs

Test wrapper design and optimization

Test access mechanism design and op-

timization

15:30 Tea break

16:00

Test scheduling

IEEE 1500 core test standard

Built-in Self-test for complex SOC

17:00 Adjourn