Tic Tac ToeVLSI Project Presentation

(Part 2)Aaron Williams and Shayda Shahbazi

December 1, 2014

● vdd/gnd● clk

9 inputs (1 for each block)● 18 outputs (9 for each player)● 9 outputs (3 bits for counting win/loss/draw)● 1 hidden input(1/2/3 for reset)

Layout Aspects

Overall Implementation

● Pitch = 35.4u○ Due to High number of inputs per component

Transistor CountDFF: 6+4+8+8=26 transistorsMemory: 26*18 + 8*18 + 6*9 + 12 = 678Checker: 9*18 + 9*8 = 262Comb: 9*6 = 54Total Win:158*3 + 28 + 64*2 = 630Turn: 164+10+16 = 190Out of AI: 1814Conditions: 6*9 +96+48=198Filter: 10*9 + 18 = 108Extra: 8*6 +4 +4+6+8+10+12+14+16 =122Think: 4*10+4*8+6+18=96Memory: 9*26 + 4 = 238Memroy_Add:3*26 + 12+12+6+14+36=158Win: 6*8 + 16 = 64Counter:4*26 + 12 +14+ 34=164Total AI: 198*2 +108*2+122+96+238+164=12323046 transistors total

Component Conditions

Component Checker

Component Turn

Combination Win

Memory Main

Filter Component

Component Extra

Memory Add

Verilog Test Code-Tests applying a set of inputs to the circuit

Future Tests:-Find a set of conditions that guarantee a Computer victory-Find a set of conditions that guarantee a Human victory-Find a set of conditions that guarantee a draw

Next Steps

● Complete testing● Complete layout

Thank You!