VLSI & E-CAD LAB B.Tech. IV Year I Sem. L T P C Course ... · 5. Design of 4 bit binary to gray code converter 6. Design of 4 bit comparator 7. Design of Full adder using 3 modeling

VLSI & E-CAD LAB

B.Tech. IV Year I Sem. L T P C Course Code: EC703PC 0 0 3 2

List of Experiments: Design and implementation of the following CMOS digital/analog circuits using Cadence /

Mentor Graphics / Synopsys /Equivalent CAD tools. The design shall include Gate-level design, Transistor-level design, Hierarchical design, Verilog HDL/VHDL design, Logic synthesis, Simulation and verification, Scaling of CMOS Inverter for different technologies, study of secondary effects ( temperature, power supply and process corners), Circuit optimization with respect to area, performance and/or power, Layout, Extraction of parasitics and back annotation, modifications in circuit parameters and layout consumption, DC/transient analysis, Verification of layouts (DRC, LVS) E-CAD programs: Programming can be done using any complier. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels) and logic analyzer apart from verification by simulation with any of the front end tools. 1. HDL code to realize all the logic gates 2. Design of 2-to-4 decoder 3. Design of 8-to-3 encoder (without and with priority) 4. Design of 8-to-1 multiplexer and 1-to-8 demultiplexer 5. Design of 4 bit binary to gray code converter 6. Design of 4 bit comparator 7. Design of Full adder using 3 modeling styles 8. Design of flip flops: SR, D, JK, T 9. Design of 4-bit binary, BCD counters (synchronous/ asynchronous reset) or any sequence counter 10. Finite State Machine Design VLSI programs: Introduction to layout design rules. Layout, physical verification, placement & route for

complex design, static timing analysis, IR drop analysis and crosstalk analysis of the following:

1. Basic logic gates 2. CMOS inverter 3. CMOS NOR/ NAND gates 4. CMOS XOR and MUX gates 5. Static / Dynamic logic circuit (register cell) 6. Latch 7. Pass transistor 8. Layout of any combinational circuit (complex CMOS logic gate). 9. Analog Circuit simulation (AC analysis) – CS & CD amplifier.

Note: Any SIX of the above experiments from each part are to be conducted (Total 12)

1 | P a g e potharajuvidyasagar.wordpress.com PREPARED BY VIDYA SAGAR.P

CYCLE-II

1 CMOS INVERTER

2 NAND GATE

3 NOR Gate

4 XOR GATE

5 MUX

6 CMOS 1-Bit Full Adder


Pyxis Schematic: Pyxis Schematic interacts seamlessly with other solutions in

the Pyxis Custom IC Design Platform to create, develop, simulate, verify, optimize

and implement even the most challenging full custom analog and mixed-signal IC

designs quickly and accurately—the first time. As a designer, you enjoy a

consistent look and feel in single environment, whether creating schematics,

block diagrams, symbols, or HDL representations. Additionally, Mentor’s foundry

partners provide certified design kits for use with Pyxis Custom IC Design

Platform solutions.

Pyxis Layout: Pyxis Layout supports an extensive set of editing functions for

efficient, accurate polygon editing. This gives the design engineer full control of

circuit density and performance, while improving productivity by as much as 5X.

Hierarchy and advanced window management allows multiple views of the same

cell and provides the capability to edit both views. Additionally, design engineers

can create matched analog layouts quickly by editing using a half-cell

methodology.

Calibre: Debugging the error results of physical and circuit verification is costly,

both in time and resources. Calibre RVE provides fast, flexible, easy-to-use

graphical debugging capabilities that minimize your turnaround time and get you

to “tapeout-clean” on schedule. Better yet, Calibre RVE easily integrates into all

popular layout environments, so no matter which design environment you use,

Calibre RVE provides the debugging technology you need for fast, accurate error

resolution.


EXP 1: DESIGN AND IMPLEMENTATION OF AN INVERTER

AIM: To design and Implementation of an Inverter

TOOLS:

SOFTWARE & HARDWARE:

Mentor Graphics: Pyxis Schematic, Pyxis Layout, Eldo, Ezwave, Calibre.

THEORY:

The inverter is universally accepted as the most basic logic gate doing a Boolean

operation on a single input variable. Fig.1 depicts the symbol, truth table and a general

structure of a CMOS inverter. As shown, the simple structure consists of a combination

of a pMOS transistor at the top and an nMOS transistor at the bottom.CMOS is also

sometimes referred to as complementary-symmetry metal–oxide–semiconductor. The

words "complementary-symmetry" refer to the fact that the typical digital design style

with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide

semiconductor field effect transistors (MOSFETs) for logic functions. Two important

characteristics of CMOS devices are high noise immunity and low static power

consumption. Significant power is only drawn while the transistors in the CMOS device

are switching between on and off states. Consequently, CMOS devices do not produce

as much waste heat as other forms of logic, for example transistor-transistor logic (TTL)

or NMOS logic, which uses all n-channel devices without p-channel devices.

Schematic

CAPTURE:


PROCEDURE:

1. Connect the Circuit as shown in the circuit diagram using Pyxis Schematic tool

2. Enter into Simulation mode.

3. Setup the Analysis and library.

4. Setup the required analysis.

5. Probe the required Voltages

6. Run the simulation.

7. Observe the waveforms in EZ wave.

8. Draw the layout using Pyxis Layout.

9. Perform Routing using IRoute

10. Perform DRC, LVS, and PEX.

SCHEMATIC SYMBOL:

TESTING THE SCHEMATIC:


SIMULATION OUTPUT:

Input Vs Output

Transient and DC

CHARACTERISTICS:

LAYOUT OF THE INVERTER:


DRC REPORT:

LVS REPORT:

RESULT: Hence developed the INVERTER schematic and layout. Verified the DRC and

LVS report. Is done.


EXP 2: DESIGN AND IMPLEMENTATION OF AN NAND GATE

AIM: To design and Implementation of an NAND GATE

TOOLS:



THEORY:

NAND and NOR gates are known as universal gates as any function can be implemented

with them,NAND functionality can be implemented by parallel combination of PMOS and

series combination of NMOS transistor. When any one of the inputs is zero, then the

output will be one and when both the inputs are one the output will be low.

CAPTURE:


PROCEDURE:











SCHEMATIC SYMBOL:



SIMULATION OUTPUT:

Input Vs Output

Transient and DC

CHARACTERISTICS:


LAYOUT OF THE NAND GATE:

DRC REPORT:

LVS REPORT:

RESULT: Hence developed the NAND schematic and layout. Verified the DRC and LVS

report. Is done.


EXP 3: DESIGN AND IMPLEMENTATION OF AN NOR GATE

AIM: To design and Implementation of an NOR GATE

TOOLS:



THEORY:

NAND and NOR gates are known as universal gates as any function can be implemented

with them, NOR functionality can be implemented by parallel combination of NMOS and

series combination of PMOS transistor. When any one of the inputs is one, then the

output will be one and when both the inputs are zero the output will be low.

CAPTURE:


PROCEDURE:











SCHEMATIC SYMBOL:



SIMULATION OUTPUT:

Input Vs Output

Transient and DC

CHARACTERISTICS:

LAYOUT OF THE NOR GATE:


DRC REPORT:

LVS REPORT:

RESULT: Hence developed the NOR schematic and layout. Verified the DRC and LVS

report. Is done.


EXP 4: DESIGN AND IMPLEMENTATION OF AN XOR GATE

AIM: To design and Implementation of an XOR GATE

TOOLS:



THEORY:

The output of the XOR gate is logic zero only when all the inputs are equal.

CAPTURE:

PROCEDURE:












SCHEMATIC SYMBOL:


SIMULATION OUTPUT:

Input Vs Output

Transient and DC


CHARACTERISTICS:

LAYOUT OF THE XOR GATE:


DRC REPORT:

LVS REPORT:

RESULT: Hence developed the XOR schematic and layout. Verified the DRC and LVS

report. Is done.


EXP 5: DESIGN AND IMPLEMENTATION OF AN MUX

AIM: To design and Implementation of an MUX

TOOLS:



THEORY:

The output of the MUX is one of the inputs selected by selection lines.

CAPTURE:

PROCEDURE:












SCHEMATIC SYMBOL:


SIMULATION OUTPUT:

Input Vs Output

Transient and DC

CHARACTERISTICS:

LAYOUT OF THE MUX:


DRC REPORT:

LVS REPORT:

RESULT: Hence developed the MUX schematic and layout. Verified the DRC and LVS

report. Is done.


EXP 6: DESIGN AND IMPLEMENTATION OF AN FULL ADDER

AIM: To design and Implementation of an FULL ADDER

TOOLS:



THEORY:

The output of the FULL ADDER is sum and carry.

CAPTURE:

PROCEDURE:











SCHEMATIC SYMBOL:



SIMULATION OUTPUT:

Input Vs Output

Transient and DC

LAYOUT OF THE FULL ADDER:


CHARACTERISTICS:

DRC REPORT:

LVS REPORT:

RESULT: Hence developed the FULL ADDER schematic and layout. Verified the DRC

and LVS report. Is done.

Documents

VLSI & E-CAD LAB B.Tech. IV Year I Sem. L T P C Course ... · 5. Design of 4 bit binary to gray code converter 6. Design of 4 bit comparator 7. Design of Full adder using 3 modeling