BER Measurement and Comparator Design

Bit-error Rate Measurement Setup and

Comparator Design

By Amir Agah

Delft University of Technology, June. 2009

Broadcom Corporation, the Netherlands

A thesis submitted to the Electrical Engineering, Mathematics and Computer Science Department of Delft University of Technology in partial fulfillment of the requirements for the degree of Master of Science.

Delft University of Technology, the Netherlands Copyright by Amir Agah, June. 2009

ii

Approval

Name: Amir Agah

Degree: Master of Science

Title of Thesis: Bit-error Rate Measurement Setup

and Comparator Design

Committee in Charge of Approval:

Chair:

_________________________

Professor John R. Long

Department of Electrical Engineering

Committee member:

____________________________

Dr. Klaas Bult

Broadcom Corporation, the Netherlands

____________________________

Professor Edoardo Charbon


____________________________

Professor Wouter A. Serdijn


iii

Abstract Bit-error rate (BER) of comparators is becoming one of the limiting factors in the design

of high speed ADCs. BER measurement setup is introduced and implemented in this

thesis. Using this BER measurement setup gives us the opportunity to compare the BER

of different comparators. It also enables us to study the effect of different parameters

such as bias current, and power supply variations on the BER of these comparators.

Capacitive based comparator is also proposed in this work which is a new topology for

comparators and simulations show that it can perform better than the other conventional

comparators with respect to BER.

The capacitive based comparator and 2 conventional comparators are implemented in the

BER measurement setup so that they can also be compared on silicon.

Acknowledgement

iv

Acknowledgement

Foremost, I would like to express my sincere gratitude to my supervisor Dr. Klaas Bult at

Broadcom Netherlands for the continuous support of my M.Sc. thesis, for his patience,

motivation, enthusiasm, and immense knowledge. His guidance helped me in all the time

of research. I could not have imagined having a better supervisor for my M.Sc. thesis. He

not only gives me technical support himself, but also offers me good opportunities to

discuss with the experienced designers in Broadcom.

I would also like to thank Professor John R. Long. I benefit a lot from the discussions

with him. The design experiences and the research attitude I learn from professor Long

are really precious to my future career. His guidance helped me a lot in all the time of

research and writing of this thesis.

I would like to show my special gratitude to all the colleagues in Broadcom, especially

Jan Mulder, Jan Westra and Frank Van der Goes. I really appreciate their willing and

patience to help me whenever I have problems. Without their help, I can not widen my

knowledge and make progress in my work.

Last, but not the least, I would like to express my gratitude to my family. Even thousands

of kilometers apart, they have been present through every step of my life, providing

support in difficult times. They have been a constant source of inspiration, and this thesis

is dedicated to them.

Table of Contents

v

Table of Contents

Abstract iii

Acknowledgement iv

Table of Contents v

List of Figures viii

List of Tables x

Chapter 1 Introduction 1

1.1 Comparator design 1

1.2 Bit-error rate measurement setup 3

1.3 Programmability 5

1.4 Scope of this report 5

References 6

Chpter 2 Comparator and Metastability 7

2.1 Comparator behavior 7

2.2 Performance parameters of the Comparator 9

2.2.1 Metastability and bit error rate 9

2.2.2 Power consumption 12

2.2.3 Hysteresis and kick-back 12

2.2.4 Noise 13

2.2.5 Offset 13

2.3 Literature review 14

2.3.1 How to solve metasatability problem? 14

2.3.2 Effect of power supply on metastability 17

2.3.3 Effect of temperature on metastability 18

2.3.4 Effect of technology scaling (channel length reduction) 19

on metastability

2.3.5 Effect of noise on metastability 20

2.3.6 Popular comparators 21

Table of Contents

vi

Summary 22

References 22

Chapter 3 Comparator Design 24 3.1 Comparator with vertical latch 24

3.2 Capacitive based comparator 27

3.3 Variable capacitor 31

3.4 Comparison of the comparators 32

Summary 35

References 35

Chapter 4 BER measurement system 36

4.1 How to detect a BER? 36

4.2 Noise effect 39

4.3 BER measurement setup 44

4.4 Clock generator 48

4.5 Divider 50

4.6 Counter 51

Summary 52

References 52

Chapter 5 Physical layout and testing 53

5.1 Layout strategy 53

5.2 Layout of different blocks 54

5.3 Preamp 57

5.4 Post layout simulation 58

5.5 Test plan, Test board and pad-ring design 60

5.6 Programmability 65

Summary 66

References 67

Table of Contents

vii

Chapter 6 Conclusions and Future Work 68

6.1 Work summary and conclusions 68

6.2 Future work 69

List of Figures

viii

List of Figures

Fig. 1-1. (a) Conventional comparator (b) Rest-time and Evaluation-time 2

in a clk cycle 2

Fig. 2-1. Simple comparator 8

Fig.2-2. Waveforms for the two outputs of the comparator for different

input signal amplitudes 10

Fig. 2-3. Theoretical error rates for two- and three-latch designs [1] 15

Fig.2-4. D latch structure 16

Fig.2-5. Measurement data of MTBF of CMOS latch/flip-flop with 18

chip temperature variation [4]

Fig.2-6. Conventional comparator 21

Fig. 3-1. Vertical latch 24

Fig. 3-2. Simplified comparator structure 25

Fig. 3-3. Vertical latch comparator schematic 26

Fig. 3-4. Vertical latch in metastable region 27

Fig. 3-5. Capacitive based comparator 29

Fig. 3-6. Output voltages of the capacitive based comparator 31

Fig. 3-7. NMOS capacitor 31

Fig.3-8. Total gate capacitance versus Vgs 32

Fig. 3-9. Conventional comparator 33

Fig.4-1. Detecting BE 36

Fig.4-2. Two outputs of the comparator and clock of the latch 37

Fig.4-3 Comparator with RC feedback 38

Fig.4-4 Digital latch 39

Fig.4-5 PDF of the pure sine wave 40

Fig. 4-6 Sine wave plus noise with sigma which is 3 times smaller

than the amplitude of the sine wave (a) and its PDF (b) 40

Fig. 4-7: Sine wave plus noise with sigma which is 3 times smaller

than the amplitude of the sine wave (a) and its PDF (b) 41

List of Figures

ix

Fig.4-8 Output of the RC feedback and input sine-wave with no noise 41

Fig.4-9 Output of the RC feedback and small input sine-wave

with transient noise 42

Fig. 4-10 Output of the RC feedback and big input sine-wave with

transient noise 43

Fig. 4-11 Programmable preamp 44

Fig. 4-12 BER measurement setup 45

Fig. 4-13. XOR and divider output 46

Fig. 4-14 placing three comparators in one setup using multiplexers 48

Fig. 4-15 Differential to CMOS amplifier 49

Fig. 4-16 Gain bode diagram of the amplifier 49

Fig. 4-17 Divider block diagram 50

Fig. 4-18 Counter block diagram 51

Fig. 5-1 Layout of 2 MOS transistors with 10 fingers 53

Fig. 5-2 Layout of capacitive based comparator 54

Fig. 5-3 Layout of conventional comparator 55

Fig. 5-4 Layout of vertical latch comparator 56

Fig. 5-5 layout of the preamp 58

Fig. 5-6 Capacitive based comparator (a) two input nodes of the

comparators (b) output of the digital latch 59

Fig. 5-7 Vertical latch comparator (a) two input nodes of the comparators

(b) output of the digital latch 59

Fig.5-8 Conventional comparator (a) two input nodes of the comparators

(b) output of the digital latch 60

Fig. 5-9. Board schematic 61

Fig. 5-10 circuit for applying the input signal to chip 62

Fig.5-11 Resistive division circuit and layout 63

Fig .5-12 Chip layout 4mm by 4mm 64

Fig. 5-13 serial input schematic 66

List of Tables

x

List of Tables

Table 2-1: Slopes of data in Fig. 2-5 [4] 18

Table 3-1. W/L and number of fingers of each transistor in the comparators 34

Table 3-2. Comparison of different comparators 34

Chapter 1 Introduction

- 1 -


In today's world, where demand for portable high-speed battery operated devices is

increasing, there is a major thrust towards low power design methodologies for high

resolution and high speed applications. It is well known that moving toward smaller

feature size CMOS technologies can reduce power consumption, however, process

variations and other non-idealities will greatly affect the overall performance of the

devices.

One such application where low power, high resolution and high speed are required is

analog-to-digital converters (ADCs). There are several portable devices which are

making use of these ADCs. For instance, these days, all the laptops and cell phones are

equipped with Wi-Fi and this is where a low power, high speed and high resolution ADC

is highly required. With the high growth in internet usage and demand for the higher

speed, there is also growing need for faster ADCs which are also low power. Advancing

from 2G mobile networks into 3G and 4G is also another indication of the growing

demand of high speed and low power ADCs.

The performance limiting blocks in such ADCs are typically inter-stage gain amplifiers

and comparators. According to the architecture of the ADC chosen, one or several

comparators might be used in a single ADC. Therefore, the comparator structure can

have an important influence on the total power consumption and other specifications of

the ADC, such as bit-error rate (BER), which will be discussed in details in this work.

1.1. Comparator design The comparator is one of the few circuits which is fully mixed signal. Its input is fully

analog and its output is digital. Therefore, design of a comparator is a critical job and

several measures should be taken into account carefully at all levels of the design,

starting from the choice of comparator appropriate to the application, to its physical

layout. It is also important to note that the overall performance of the ADC is dependent

upon the performance of the comparators which are used in it.


- 2 -

In the literature one will find that a major emphasis has been made in regard to different

parts of ADCs such as inter-stage gain amplifiers but very little effort has been made

towards the design of comparators [1] [2] [3]. In most publications, a standard

comparator (Fig.1-1a) is used without considering the advantages or disadvantages of this

structure. In this work, it is shown that the conventional comparator is not always the best

choice with respect to power consumption and BER.

All of the comparators discussed in this work are clocked comparators. Considering the

behavior of the comparator, the clock period is divided into two parts, reset-time and

evaluation-time (Fig.1-1 b). During the reset-time the previous decision is removed and

comparator becomes ready for making a new decision. Evaluation time is the time in

which a comparator reacts to the input signal and makes decision. As the clock frequency

increases, the evaluation-time and also the reset-time of the comparator are reduced,

respectively, which shows the growing need for higher-speed comparators.

Fig. 1-1. (a) Conventional comparator (b) Rest-time and Evaluation-time in a clk cycle

M1

Clk

M2

M4

M7

M6 M5

M3

M8

Clk

In+ In-

Out+ Out-

Evaluation-time

Reset-timeclk

(b)

(a)


- 3 -

Insufficient evaluation time results in the bit errors (which will be discussed in details

later) and insufficient reset-time results in hysterisis.

In this work, a new comparator structure is proposed. Looking at the literature, it can be

recognized that all comparators have a transconductance stage at their input which

converts a differential input voltage difference into a differential current. This current

difference is then applied to a latch, however, the main disadvantage of this method is

high power consumption, since the input stage also consumes power in the reset mode.

The proposed structure converts the voltage difference into a capacitor difference which

unbalances the latch. This unbalanced capacitive load helps the latch make the correct

decision. Simulation results show that this comparator has low power consumption and

with same power consumption it has lower BER when compared with other comparators.

This circuit will be discussed in details in chapter 3.

1.2. Bit-error rate measurement setup

The errors caused by metastable behavior are particularly difficult to trace, due to their

random and intermittent nature. Metastable behavior in comparators is unavoidable and

produces a dramatic range of failure [4] [5]. They may be the cause of unexplained

computer crashes and other mysterious digital system malfunctions.

Designers should give special attention to it, particularly if they are attempting to build

highly reliable systems. They should also develop techniques for accurately predicting

system reliability and should exploit techniques for reducing the probability of

synchronization failure due to metastable behavior.

One of the major problems for studying the BER and the effect of different parameter on

BER is the time required for measuring the bit-error rate of a system. Accurate BER

measurement can take days to perform, which makes it impractical. For instance,

measuring the BER of a system which is running at 1GHz and at a BER of 1e-15 (i.e.,

close to the BER required for 10GBASE Ethernet) is

Required time = 1015*10-9=106 [s] Eq. (1.1)


- 4 -

or approximately 12 days. If we want to examine the effect of one bias current on the

BER of an ADC, then we should change this current and run the system for several days

to see the effect of this change, which is really impractical. Thats why there are not

many publications in which BER of the design is reported, although it is becoming a

critical specification.

It is also seen that there are several publications proposing some new ideas for making

low-power ADCs but a lot of them are using some methods which are obviously

degrading the BER of the ADC but this is not shown in the measurements since no BER

measurement is done [6].

In this work, we propose a system which can measure the BER of different comparators

in less than a minute. For reducing the measurement time, several methods are used.

Increasing the clock frequency and keeping the comparator near its trigger point by

canceling offset and reducing signal variations at the input of the comparator are done in

order to increase the probability of the bit errors.

Being able to measure the BER of a comparator in a short time enables us to study the

effect of various parameters on the metastability of a comparator and it is also possible to

compare different comparators with respect to their BER.

Since the comparator can cause metastability in the system, it is critical to know the BER

of different comparators. Knowing the BER of different comparators, we can make use of

proper comparators in proper places and avoid poor BER or over designing by burning

too much current or wasting too much area.

One might say that it is a good idea to measure the BER of a comparator using the

available simulators, however, simulating metastability of a comparator is not straight

forward. For measuring the BER of a comparator at a certain clock frequency, first we

need to know the distribution of the signal at the input of the comparator and second we

need to find the smallest input voltage which can be detected by that comparator. This is

not easily done, since the accuracy of the simulator is limited (e.g., it is not possible to

apply 1fV input to the comparator). We can measure the time-constant of the comparator

and then calculate the BER by assuming that this time constant is not a function of input

voltage. This can be done by applying different voltages (relatively small but in the


- 5 -

region where the simulator is still accurate enough) and observing the behavior of the

output voltage of the comparator to each of these input voltages. Making use of this time

constant, we can extrapolate the BER of the comparator considering the frequency at

which comparator is supposed to operate. This is the main method used to design a

comparator with a proper BER, however, this method is based on the assumption that the

time constant of the comparator is not a function of the input voltage. This is not

necessarily correct, since a comparator is a nonlinear device and the time constant of the

circuit is not necessarily constant for different input voltages. Measurement of BER will

be discussed in Chapter 3.

1.3. Programmability

Since we are going to study the effect of different parameters on the BER of comparators,

being able to change these parameters manually is a key point. We decided to make all of

these parameters programmable so that we can change and study their effect

independently. All of the bias currents, gains of the preamps and parameters in the digital

parts are made fully programmable. These parameters are controlled through a serial

computer interface and can be programmed via MATLAB. This way of testing also

enables us to automate many different tests to save time when testing the circuit. More

details about the testing of the circuit are discussed in Chapter 5.

1.4. Scope of this report

Chapter 2 is dedicated to a literature review on comparator design and metastability.

Basic specifications of comparators are also discussed.

In Chapter 3, existing comparator structures are described and a new high-speed, low-

power comparator is proposed. The new structure will be compared in simulation with

other existing structures with respect to speed, power consumption, noise and offset.

The advantages and disadvantages of each of them will be shown in detail.

In Chapter 4, a comparator BER measurement system is developed. Making use of this

system we can measure the BER of different comparators in a reasonable amount of time


- 6 -

and we can study the effect of different parameters on their BER. This system will

enables us to compare different comparators with respect to their BER on silicon, which

have never been done before.

In Chapter 5, the layout details and testing of the BER measurement setup are described.

It will be shown that comparators are sensitive to their physical layout and special

measures should be taken into account in order to make the layout completely

symmetrical, otherwise the comparator will show a considerable amount of offset. Well

also discuss the programmability of the setup, which eases the testing procedure of the

system.

Chapter 6 is dedicated to the conclusion and summery of what have been done in this

work.

Reference [1] J. H. Hohl, W. R. Larsen, and L. C. Schooley, Prediction of error probabilities for

integrated digital synchronizers, IEEE J. Solid-State Circuits, vol. SC-19, pp. 236244,

Apr. 1984.

[2] C.W. Mangelzdorf, A 400-MHz Input Flash Converter with Error Correction, IEEE

J. Solid-State Circuits ,vol. 25, no. 1, pp. 184-191, Feb. 1990.

[3] Le-sup Kim and Robert W. Dutton, Metastability of CMOS Latch/Flip-Flop, IEEE

J. of Solid-State Circuits, VOL. 25, No.4, August 1990.

[4] L. Kleeman, A. Cantoni, Metastable behavior in digital systems, IEEE design & test

of computers, pp. 4-19, Dec. 1987.

[5] G.R. Couranz and D.F. Wann, "Theoretical and Experimental Behavior of

Synchronizers Operating in the Metastable Region," IEEE Trans. Computers, pp. 604-

616, June 1975.

[6] B. Verburggen, J. Craninckx, M. Kuijk, P. Wambacq, G. Van Der Plas, A 2.2mW

5b 1.75GS/s folding flash ADC in 90nm digital CMOS, ISSCC digest of Technical

papers, pp. 252-253, Feb. 2008.

Chapter 2 Comparators and Metastability

- 7 -

Chapter 2 Comparator and Metastability

In this chapter, general behavior of comparators will be discussed and important

performance parameters will be introduced. Bit error rate (BER) will be defined and

literature review is also done to determine the parameters which can affect the BER of a

comparator. Some previous works for improving the BER will also be introduced.

2.1. Comparator behavior Comparators in general are made of an input stage which is usually a differential pair

loaded by a negative resistance realized using positive feedback. The gain is made

sufficiently high to causes regenerative action yielding a logic one on one side and zero

on the other side. A switch is also required between the two output nodes of the

comparator for resetting purpose. When the switch is closed, comparator is in the reset

mode. During the reset-time the previous decision is removed and comparator becomes

ready for making a new decision. As soon as the switch is opened, the regenerative action

causes a logical one or zero to appear at the output, depending on the input signal. This is

referred to as evaluation mode.

For better understanding of the behavior of the comparator lets consider a simple

comparator which is made of an input differential pair, a current mirror and two cross-

coupled NMOS transistors (see Fig.2-1).


- 8 -

Fig.2-1. Simple comparator When the comparator is switched from reset mode to evaluation mode, the transient

appearing at the outputs can be approximated by [1]:

Vo = A Vi exp ( t/ ) Eq. (2-1)

where Vo is the output of the comparator, A is the gain in evaluation mode, Vi, is the

input voltage, t is the time since the onset of positive feedback, and is the time constant

of the latch in positive feedback. This time constant is defined by equation (2-2).

= Cout / gmeff Eq. (2-2)

where Cout is the total capacitance at the output node and gmeff is the effective

transconductance of the NMOS latch which is:

gmeff = gm-or1 Eq. (2-3)

Effect of ro on BER will be discussed in more details in section 2.3.4.

M9

M8 M7

Clk

In+ In-

Out+ Out-

M10 Bias

M1 M2

M3 M4 M5 M6


- 9 -

2.2 Performance parameters of the Comparator

The performance parameters related to the design of comparators are: power

consumption, BER, noise, chip area which is occupied by the comparator, offset,

hysteresis and kick-back. Each of these factors have different priorities with respect to the

application in which comparator is used, therefore, a comparator should be always chosen

with respect to the application. Knowing the performance advantages and disadvantages

of different comparator circuits helps the designer optimize a mixed-signal design.

2.2.1 Metastability and bit error rate

The error mechanism of concern is the occasional inability of a comparator to resolve a

small differential input into a valid logic level within a given time interval, a

phenomenon known as metastability. Metastability refers to the operating point of a

comparator, when it is balanced right at its threshold so that both outputs are equal and

neither logical one or zero, which is only possible for a short period of time (i.e., this is

not a stable long-term operating point) This mechanism has long been understood as a

limitation in the design of high-speed flash converters [2].

For clarification consider Fig.2-2,


- 10 -

Fig.2-2. Waveforms for the two outputs of the comparator for different input signal

amplitudes

When the clock signal is high, the comparator is in the reset mode and differential output

voltage is equal to zero since the switch between the output nodes is closed. When clock

signal becomes zero this switch opens and comparator enters the evaluation mode. The

output voltage grows roughly exponentially until it reaches a valid logic level.

As can be seen in Fig. 2, the comparator needs more time to reach a valid logic level as

the input voltage amplitude decreases. However, for a fixed evaluation time, there is a

minimum input voltage which can be detected by the comparator. During this period we

can consider the regenerative circuit to have an effective gain which is a function of time:


- 11 -

Aeff=Vo/Vi=Aexp(t/ ) Eq. (2-4)

As the clock rate of the ADC is increased, the amount of time the latch stage of the

comparator spends in evaluation mode (where there is positive feedback) is reduced and

the effective gain of the latch reached at the end of half a clock cycle is lower. Lower

effective gain makes it more likely that relatively small input voltages will not be

amplified to a full logic level, and thus increases the chances for an error.

Reduction in can lower the error rate of the comparator. This can be done by increasing

the gain-bandwidth product of the latch since is inversely proportional to the gain-

bandwidth product of the latch.

Assuming a uniform distribution for the signal present at the input of the comparator,

BER can be defined by the minimum signal which can be detected by the comparator

divided by the maximum input voltage at the input of the comparator. However this is not

a practical definition, since the accuracy of the simulator is limited. Therefore for

measuring the BER of a comparator by a simulator, input voltages with amplitudes of

10mV, 1mV, 100uV, 10uV, 1uV (which are still in the range which can be accurately

simulated) are applied to the comparator, and all the output voltages are plotted on a same

graph, as shown in Fig. 2-2. Since these inputs differ by a factor of ten from each other,

all the output voltages should be equally distanced from each other in time considering

the exponential behavior of the comparator. It can be shown that this distance is equal to:

t = ln(10) * Eq. (2-5)

Therefore, by measuring t on the plot one can calculate the time constant of the

comparator. Knowing this time constant and the clock frequency of the comparator, one

can calculate the minimum input voltage which can be detected by the comparator. Using

this minimum value and the distribution of the input signal of the comparator, the BER of

the comparator may be calculated. However, this method is based on this assumption that

the time constant of the comparator is not a function of the input signal, which is not

necessarily true for all comparator structures (this will be discussed in Chapter 3).


- 12 -

2.2.2 Power consumption

Power consumption is one the main performance parameters of comparators.

A portion of the total power consumption is due to constant currents such as the bias

current of the input pair. This part of the power consumption is always present, even

when comparator is in the reset mode. Therefore, in the design we always try to minimize

this part.

A second part of the power consumption is due to the current consumed when the

comparator enters the evaluation mode. Depending on the topology of the latch which is

used, current is pumped into the latch in order to increase the effective gm in the

evaluation mode, thereby reducing the time constant which results in a higher effective

gain and a faster decision. In a CMOS latch, this current flow stops when a logical one or

zero state is reached. This part of the power consumption is highly dependent on the

clock frequency.

Considering this description, it can be understood that staying in metastable region

increases the power consumption dramatically, since most of the current flowing through

the latch is burned while comparator is in this region.

2.2.3 Hysteresis and kick-back

Considering the limited reset time and the fact that the switches which are used for

resetting the comparator are not ideal each decision might affect the next decision. This

phenomenon is referred to as hysteresis.

The other mechanism which can results in hysteresis is called kick-back. It is clear that in

each clock cycle output nodes of the comparator are changing from a common-mode

voltage into valid logical one and zero (i.e. one node to logical one and the other one to

logical zero). These voltage variations can feedthrough the input transistors and into the

input nodes. If the time-constant of the input node is low enough so that these voltage

variations are canceled before the next evaluation time no problem occurs, however if

this time constant is not small enough next decision is affected by the current decision

which is the definition of the hysteresis.


- 13 -

2.2.4 Noise Input referred noise is an important parameter which is used to characterize the

performance of the comparator. PDF of this noise is considered to be Gaussian with zero

mean. Standard deviation (sigma) of this curve is the parameter which should determined

for characterizing this noise.

In most of the applications in which a comparator is used, 2 or 3 additional preamplifiers

are placed before the comparator. Using these preamps has several advantages, such as

reduction of the noise and offset. It can also suppress the effect of the kick-backs of the

comparator. However it increases the power consumption and the physical area of the

circuit.

Since a comparator is a nonlinear circuit, calculating the input referred noise of it is not a

straight-forward task. There are several simulation methods for measuring the noise of

linear and partially linear circuits, but there these are not applicable for the comparator.

Therefore, in this work we used large-signal (i.e., transient) noise simulation in order to

measure the standard deviation (sigma) of the input referred noise of the comparator.

2.2.5 Offset In an ideal op amp or comparator, if the input signal is zero, the output will also be zero.

In actual circuits, imperfections in the circuit components and mismatch cause a DC

voltage to exist at the output, even when the input voltage is zero. This DC voltage is

referred to as DC offset.

A comparator is a sensitive structure to asymmetry and special attention should be made

in order to design it completely symmetrical. Any mismatch or any non-idealities in the

layout of the comparator will result in significant DC offset therefore layout of the

comparator is really important and critical. Although offset can be reduced significantly

by making use of preamps, it is still one of the major performance parameters of the

comparator.

It is shown that the common-mode voltage jump of the comparator output nodes at the

onset of the evaluation mode has a significant effect on the DC offset which is generated

by mismatch. It is shown that minimizing the common-mode voltage change at the start


- 14 -

of the evaluation mode can minimize the effect of mismatch on the offset. We will use

this fact for designing a new comparator in Chapter 3. The other mechanism which can

result in offset is the imbalanced cross-talk from the clock.

2.3 Literature review

Looking to the literature, it is clear that there are few papers about the metastability of the

comparators. However, there are some papers about the metastability of digital latches

and flip-flops which operate using the same principle. Here we are looking at what has

been discussed in these papers about the metastability.

2.3.1 How to solve metasatability problem?

One of the solutions which have been proposed [3] is the use of two cascaded comparator

stages strobed on opposite phases of the clock, making the total evaluation time one

whole clock cycle. This improves the effective gain approximately by a factor exp(t/)

which reduces the probability of bit errors by several orders of magnitude. Some articles

[1] also believe that cascading three latches was more effective than a two latch design

for the same total power consumption. Projected error rates for the two designs with two

and three cascaded comparators are shown in Fig.2-3. It can be seen that using three

cascaded stages can reduces the BER considerably. The only drawbacks of the third latch

are another stage of pipeline delay and the increase in die area.


- 15 -

Fig. 2-3. Theoretical error rates for two- and three-latch designs [1]

Reduction in is also one of the things which can improve the error rate of the

comparator and it can be done by increasing the gain bandwidth of the latch.

Considering that the process sequence and device parameters are not routinely adjusted to

improve robustness against metastability, choosing the optimal device size, aspect ratio,

and circuit configuration seems the most viable approach to attack this problem

effectively at the circuit design stage.

Consider the structure of the normal D latch in CMOS shown below in Fig. 2-4.


- 16 -

In the metastable region, voltage at the output and the input of the inverters (I2 & I3) are

equal and thus all of the transistors are working in the saturation region. Considering this

fact, some papers [4] suggest using small-signal analysis for optimizing the device sizes.

In these articles, frequency-domain analysis is shown to be as effective in design as large-

signal analysis. It is also verified by comparing results with those investigated

analytically and by large-signal (i.e., time-domain or transient) simulation [5], [6].

It is shown that using this kind of analysis it is possible to present further considerations

for optimal design of the CMOS latch/flip-flop against the metastable state. For instance,

in the frequency domain the Miller effect plays an important role in limiting the gain-

bandwidth product, which is a measure of how quickly the regenerative configurations

(which latches and flip-flops belong to), recover from the metastable state.

It is well known that the CMOS inverter has a high small-signal (i.e., ac) gain at the

metastable voltage. This ac gain determines the resolving capability (ability of going out

of metastable region) of CMOS inverters of the latch/flip-flop. It can be shown that total

small-signal Gm of two back-to-back inverters is equal to:

Fig.2-4. D latch structure

I1 I2

I3

CLK

CLKB

CLK CLKB

D Q


- 17 -

Gm= ( )VtnVtpVdda

aL

WppCoxaL

WnnCox

+++ .111 Eq. (2-6)

Where a is defined as:

p

n

p

n

WWa

= Eq. (2-7) Studying the effect of different parameters such as aspect ratio of NMOS and PMOS

transistors and power supply on gain-bandwidth product, can also verify their effect on

metastability and enables us to optimize the design for lower BER.

2.3.2 Effect of power supply on metastability

Power supply degradation is one of the parameters which can affect the probability of

going into the metastable region. The power supply degradation in VLSI circuits

becomes a more serious problem with larger chip size due to IR drop over power and

ground rails which are also longer now and hence is a major cause of metastability [4].

The effect of power supply degradation on the ac gain of the inverters is clearly shown in

equation (2-6). As one can see, decreasing the Vdd supply directly decreases the ac gain

of the inverter (by decreasing Gm) which results in the increase in the probability of the

metastability. We can also look at this problem from a different point of view. It is well

known that power supply disturbances can cause serious disruption to the operation of

digital systems. Among the possible problems, degraded propagation delay time due to

reduced power supply voltage is the most serious one on the performance of circuits, and

has been studied extensively [7], [8]. In addition, the reduced power supply voltage due

to voltage drops caused by long power and ground rails can cause the metastability of the

latch/flip-flop.

Mean time between failure MTFB is the average time between the failures of a system

and it is a measure of the BER of a system.


- 18 -

After doing the measurement on CMOS latch/flip-flop with different power supplies,

about three orders of magnitude of mean time between failure MTBF change is reported

as Vdd varies from Vdd = 5 V to Vdd = 4.5 V [4].

2.3.3 Effect of temperature on metastability

In addition to supply voltage variations, operating temperature is one of the most severe

operating constraints of digital systems. The temperature at which most VLSI circuits are

operated is elevated owing to the heat generated by circuits on the same chip. An

unexpected hazardous situation occurs when VLSI circuits are exposed to a high

temperature environment. Therefore, it is necessary to investigate the temperature effects

on metastability. In these studies, the temperature of the chip is raised. The measurement

results on CMOS latch/flip-flop corresponding to T = 50, 75, 100, and 125C are

available and shown in Fig. 2-5.

Fig.2-5. Measurement data of MTBF of CMOS latch/flip-flop with chip temperature variation [4]

Table 2-1: Slopes of data in Fig. 2-5 [4]


- 19 -

As expected, the higher chip temperature gives rise to higher failure rates. About 75C of temperature difference causes four orders of magnitude degradation in MTBF. It also

can be noticed that higher chip temperatures result in a lower slope of the measurement

data as listed in Table 2-1. In other words, the metastable state resolving ability of a

latch/flip-flop is severely hampered by increased chip temperature. This can be explained

by considering the fact that mobility of the transistor is reduced by increasing the

temperature since:

23

0300

=

T Eq. (2-8)

Where 0= (T=300 K).

2.3.4 Effect of technology scaling (channel length reduction) on

metastability

There are several different theories about the effect of technology scaling on

metastability. This is because technology scaling can affect metastability in different

ways.

Since time constant of the latch () is essentially Cout/gm where Cout is the total

capacitance at the output node and gm is the transconductance of the transistors at that

node, Cout is decreasing when we are going into sub-micron technologies, however, gm is

increasing in these technologies which result in smaller .

Using the first order equations for the variations in it can be shown that [9]:

ppnnth WWVVdd

WpWnKL )2(

)(2

+= Eq. (2-9)

As you can see, scaling reduces the numerator of equation (2-9) more than the

denominator, which results in a smaller time constant. So it seems that scaling can reduce

the metastability problem. However, it can be seen from equation (2-9) that decreasing

the power supply will degrade , and as Vdd approaches 2Vth, will increase markedly.

But it is also possible to look at this problem from a different point of view. As discussed

earlier, the ac gain is the critical parameter for the metastable condition when the input


- 20 -

and the output are at the same voltage. The slope in the dc voltage transfer characteristic

curve of the CMOS inverter represents the maximum ac gain. The output resistance of

the load (i.e., the PMOS device and NMOS device) determines that slope. For the scaled

devices, the channel-length modulation effect becomes more transparent, and as a result,

the output resistance is reduced, which results in a lower slope at V, which means a lower

ac gain. It can also be explained by mentioning that gmro decreases as we go into smaller

technologies. Since ro decreases dramatically as gate length is scaled down, this reduction

is not compensated by the increase in gm, so gmro is decreasing with technology scaling.

This negative effect can also be explained by equation 2-3, reduction of ro reduces gmeff

and this degradation of gmeff increases the time constant of the comparator. Therefore, the

metastable state problem becomes more serious in VLSI circuits using scaled devices due

to the degraded characteristics of the load.

2.3.5 Effect of noise on metastability When a circuit is in the metastable region, there are several forces that tend to destroy the

equilibrium rather than restore it. However, it has been shown that noise has a negligible

statistical effect on the time duration in the metastable state for a flip-flop [10]. Some

might think that noise can help our circuit to go out of metastable region, but thats not

the case. The number of states forced out of metastable region because of noise will be

replaced by an equal number forced in from the other region. This qualitative argument

has been verified also experimentally by Couranz [10]. In his paper it is shown that the

probability of the output voltage being found outside the metastable region (PE(t)) is

given by:

PE(t) = 1 - exp (-t/RC) Eq. (2-10)

where R and C stand for total impedance and total capacitance at the output node of the

latch. It is also shown that this probability is exactly the same for the time when circuit is

noise free.


- 21 -

2.3.6 Popular comparators Consider the comparator which is shown in Figure 2-1. This comparator has two major

disadvantages. First, lets consider the output node of the comparator, one node voltage

which is supposed to become zero is pulled down exponentially by the NMOS transistor ,

however the only mechanism which can pull up the other node is the bias current which

comes from the PMOS current mirror. This mechanism is much slower than the pull

down since it is approximately linear with time (when the FET is in saturation).

The other disadvantage of this structure is that it continually burns current, even during

the reset time, which results in the high power consumption. One of the most popular

comparators which is used extensively has solved these two problems. This comparator is

shown in Figure 2-6.

Fig.2-6. Conventional comparator

M1

Clk

M2

M4

M7

M6 M5

M3

M8

Clk

In+ In-

Out+ Out-


- 22 -

A second switch (M8) is placed on top of the input pair which is open during the reset so

no current is burned during the reset time. Two PMOS transistors (M3 and M4) are added

which are responsible for pulling up the output node. These transistors reduce the pull-up

time of the comparator considerably.

This topology also has some problems, since M8 is open in the reset mode. Then all of

the transistors are biased off, and when comparators enter the evaluation mode it take a

while for this transistors to turn on and this delay can slow the comparator. The other

disadvantage is caused by adding PMOS transistors. These transistors increase the total

capacitance at the output approximately by a factor of two, however, they cant double

the effective gm of the comparator due to smaller of the PMOS transistors and also

smaller voltage headroom which is left for them. This results in a bigger time constant

and therefore slower comparator. This solution also increases the offset of the

comparator.

Summary

In this chapter, general behavior of the comparator is discussed and the performance

parameters of the comparators are introduced. A literature review is also done on what

have been done previously on the metastability problem of the latches and some solutions

are provided from the previous works.

References [1] C.W. Mangelsdorf, A 400-MHz Input Flash Converter with Error Correction, IEEE

J. Solid-State Circuits ,vol. 25, no. 1, pp. 184-191, Feb. 1990.

[2] B.Zojer, R. Petschacher, and W. Luschnig, A 6-bit/200-MHz full Nyquist A/D

converter, IEEE J. Solid-State Circuits, vol. SC-20, no, 3, pp. 780-786, June 1985.

[3] J. H. Hohl, W. R. Larsen, and L. C. Schooley, Prediction of error probabilities for

integrated digital synchronizers, IEEE J. Solid-State Circuits, vol. SC-19, pp. 236244,

Apr. 1984.

[4] Le-sup Kim and Robert W. Dutton, Metastability of CMOS Latch/Flip-Flop, IEEE

J. of solid-state circuits, VOL. 25, No.4, Aug. 1990.


- 23 -

[5] S. T. Flanagan, Synchronization reliability in CMOS technology, IEEE J. Solid-

state Circuits, vol. SC-20, no. 4, pp. 880-882, Aug. 1985.

[6] T. Sakurai, Optimization of CMOS arbiter and synchronizer circuits with

submicrometer MOSFETs, IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 901-906,

Aug. 1988.

[7] M. L. Cortes, E. J. McCluskey, K. D. Wagner, and D. J. Lu, Modeling power-supply

disturbances in digital circuit, ISSCC Dig. Tech. Papers, pp. 164-165, Feb. 1986.

[8] K. D. Wagner and E. J. McCluskey, Effect of study voltage on circuit propagation

delay and test applications, IEEE IC-CAD Conf. Proc., pp. 42-44, Nov. 1985.

[9] Clemenz L. Portmann and Teresa H. Y. Meng, Metastability in CMOS Library

Elements in Reduced Supply and Technology Scaled Applications, IEEE J. of solid-

state circuits, VOL. 30, No.14, Jan. 1995.

[10] G.R.Couranz and D.F. Wann, "Theoretical and Experimental Behavior of

Synchronizers Operating in the Metastable Region," IEEE Trans. Computers, pp. 604-

616, June 1975.

Chapter 3 Comparator Design

- 24 -

Chapter 3. Comparator Design In this chapter we will discuss different architectures of the comparator and a new

topology is proposed. This new architecture is designed for low power and low BER

applications. In the final part of the chapter, we will compare different comparators with

respect to their power consumption, offset and time constant, which is an indication of

the BER of the comparators.

3.1 Comparator with vertical latch As described previously in section 2.3.6 of this thesis, the bias current coming from the

current mirror is the only pull-up mechanism of the comparator shown in Fig. 2-1. This

bias current is limited due to the limitations on the power consumption therefore pull-up

speed of this comparator is also limited. For solving this problem some designers

suggested the idea of using vertical latch. For better understanding lets first consider Fig.

3-1.

Fig. 3-1. Vertical latch This structure is known as vertical latch. Consider the initial condition in which A+ is

grounded and B- is connected to VDD, in this condition system is stable and no drain

current flows since Vgs of both transistors is zero. The other case in which this latch is

M2

M6

A+ B-

VDD


- 25 -

stable is the case when A+ is VDD and B- is grounded. In this case also no current is

flowing since Vds of all transistors are zero. However in any other condition which is

between these two stable conditions, the latch is unstable and it wants to reach the stable

condition in which A+ is VDD and B- is grounded. It is also good to mention that this

latch is capable of fast switching since Vgs of each transistor can reach VDD.

Now consider the comparator which is shown in Fig. 3-2. Some transistors such as reset

transistors are not shown for simplicity.

Fig. 3-2. Simplified comparator structure [1] In the reset mode nodes B+ and B- are connected to VDD, therefore PMOS transistors

(M1, M2) are off and the only current which flows through the M7 and M8 is the current

which comes from the current mirror (M11 and M12). M5 and M6 are also turned off by

means of 2 switches which are placed on their drain (not shown in Fig. 3-2).

As soon as the reset switches are opened, the comparator enters the evaluation mode. If

the input voltage is big enough (i.e. bigger than 1mV), A- or A+ is pulled down by M7

and M8. Lets assume that In+ is considerably bigger than In- and therefore A+ is pulled

down. In this case since B- is VDD, the vertical latch of M2 and M6 is in stable region and

no current flows through these transistors. However since A- is not grounded, the other

vertical latch (M5 and M1) is in the unstable region described previously, and A- is

pulled up by M1 and B+ is pulled down by M5. The comparator is now in the stable

region and the decision is made.

M8 M7

B+

M1 M2

M6

A+ A-

M5

B-

In+In-

Bias

A-A+

M3 M4

M9 M10 M12

M13

M11


- 26 -

Now lets assume that input voltage is not big enough (i.e. smaller than 1V) and

therefore M7 and M8 can not make a decision instantaneously. In this case, both of

vertical latches are in the unstable region and therefore both M5 and M6 are on. Nodes

B+ and B- are pulled down simultaneously, and therefore both M1 and M2 start to pump

more current into M7 and M8. This current increases the gm of these transistors which

therefore increases the effective gain of the latch and can effectively increase the speed of

the comparator. Making use of this structure, small input signals are amplified by a

higher gain and big inputs are amplified by lower gain. This results in the less total power

consumption, since extra current is only used if the input is considerably small (i.e.,

smaller than 1V) which is not the case usually.

Considering the fact that when one of M1 or M2 is turned on the other one should be

turned off by means of pulling up its gate to VDD, a pull-up network is required for B- and

B+. M3 and M4 are added for this purpose to the structure. The complete structure is

shown in Fig. 3-3.

Fig. 3-3. Vertical latch comparator schematic [1]

M11 and M12 are added in order to prevent any current flowing to M5 and M6 during the

reset mode. M9 is used as a reset switch which short-circuits A+ and A- in the reset

mode. M13 and M14 are also reset switches which are used for resetting out- and out+

nodes into VDD in the reset mode.

M9

M8 M7

Clk

In+ In-

Out+Out-

Bias

M1 M2

M6

A- A+ A- A+

ClkBClkB

ClkB ClkB

M5

M3 M4

M11 M12

M13 M14

M16

M17

M18 M19 M20

M15

M21


- 27 -

Now that the whole structure is complete, it is good to make a final remark about this

circuit. When the comparator is in the metastable region, the structure of the vertical latch

from the common mode point of view is shown in Fig.3-4.

Fig. 3-4. Vertical latch in metastable region Sizing of the transistor in this structure is critical. This loop is made of two current

mirrors with gain of m and n. Current gain of the loop is the product of m and n. Since we

want this structure to latch just at the beginning of the evaluation mode, the current gain

of this loop should be more than one, otherwise the vertical latch is not latching.

Simulations show that a current gain of 3 or 4 achieves the lowest BER. A loop with

smaller gain is slow and therefore it reduces the effectiveness of the loop. Increasing the

current loop gain further is also not effective since it also increases the parasitic

capacitance of the output node which increases the time constant and it also increases the

power consumption dramatically. From now on, this comparator is referred to as vertical

latch comparator.

3.2 Capacitive based comparator

All of the comparators which have been discussed until now consist of a

transconductance input stage. This input stage converts the input voltage into current and

M2

M6

A+ B-

M8

M4

m : 1

1 : n


- 28 -

this current is applied to the latch. The latch is making its decision by considering this

current difference.

Using the input transconductance stage increases the power consumption of the

comparator since it is burning the bias current for the entire clock cycle (i.e., even during

the reset mode). If we use a switch to turn this stage off during the reset mode, it slows

the comparator since transistors need time for being turned on completely.

Considering the regenerative structure of the latches, it is clear that these structures are

extremely sensitive to mismatch and any unbalanced loading. Special measures should be

taken into account in order to keep the latch completely balanced. One of these measurers

is minimizing the common-mode (CM) jump which occurs at the beginning of the

evaluation mode. Reducing this CM jump can effectively reduce the sensitivity to

unbalanced loading [1].

Considering the fact that comparators are extremely sensitive to unbalanced loading, we

realized that it is possible to apply the input voltage into the comparator by converting

this voltage difference into a capacitor difference. By loading the latch with two

capacitors which are not equal due to applied input voltage, the comparator can then

make a decision.

One might think that adding the variable capacitors might slow down the latch however

thats not the case. It should be mentioned that no current mirror is connected to the latch

in this topology and this reduces the total excess capacitance at these nodes with respect

to the vertical latch comparator. The main advantage of this approach is the fact that this

comparator burns no current during the reset mode and this current can be used to

increase the gm and therefore reducing the time constant of the latch although the total

capacitance is increased. The other mechanism which reduces the effect of this additional

capacitance is the CM jump at the onset of the evaluation mode which can be translated

to an additional gain which increases the effective gain of this comparator.

Several measures have been taken into account in order to increase the sensitivity of the

comparator to the unbalanced load since we can increase the effective gain of the

comparator by this means. All the methods which one had to follow in order to reduce

this sensitivity should now be reversed [2] [3]. For instance maximizing the common-


- 29 -

mode jump at the beginning of the evaluation mode is an effective way of increasing the

effective gain of this comparator.

Structure of the capacitor based comparator is shown in Fig. 3-5.

Fig. 3-5. Capacitive based comparator In the reset mode, all the nodes of the comparator are connected to Vdd by M11, M12,

M13 and M14. Power consumption is zero during the reset mode since no current flows

through the circuit. M10 is also open during the reset and therefore no current flows

through the comparator in this mode. At the beginning of the evaluation mode, nodes A-

and A+ are pulled down (common mode jump), however, the time constant of these two

nodes is different since the variable capacitors (M15 and M16) at these nodes have

different values. Therefore the node which has the bigger time constant is pulled down

slower than the one which has a smaller time constant. The voltage difference between

the two nodes of the vertical latch results in the decision.

Choosing good sizing of the transistors for the capacitor based comparator is really

critical and it should be designed carefully. Designers should try to use transistors with

minimum length in order to minimize the parasitic caps at all the nodes. Current gain of

the vertical latch should be more than one, but going to gains of more than 4 is not

Clk

M9

M8M7

Clk

Out+ Out-

M1 M2

M6

A- A+

Clk Clk

M5

M3 M4Clk

In+ In-

Clk M10

M11 M12 M13 M14

M15 M16


- 30 -

effective and it just increases the time constant which is not favorable. Sizes of the

switches should also be chosen carefully. Two measures should be taken into account for

choosing the best switch sizes, the ability of the switches to reset the comparator during

the reset time and also preventing the comparator from latching in the reset mode. So as

one can see, switch sizes are dependent on the clock frequency of the circuit.

One of the main things which should to be taken into account in the design of this

comparator is the value of this variable capacitor. Increasing the value of this capacitor is

not beneficial since it increases the loading of the comparator which increases the time

constant and slows the comparator. However, offset prevents us from decreasing this

value into really small values.

Due to processing variation, all the transistors which are used in the comparator are not

perfectly matched. This mismatch, which is mainly due to gm mismatch between

transistors, generates offset. If the variable capacitor is chosen to be rather small, even

with the highest input voltage it will not be able to compensate for the offset and it looks

like that the comparator has infinite offset. Therefore, offset should be checked carefully

when choosing these variable capacitors.

Input referred noise of this comparator is also highly dependent on the value of these

variable capacitors. Increasing these capacitors decreases the input referred noise.

The main disadvantage of this structure is hysteresis since this structure kicks back the

previous stage. The output of the comparator is separated from the input by just a

capacitor, and therefore the input node can sense the voltage fluctuations on the output.

This results in hysteresis. The amount of hysteresis which is tolerable highly depends on

the application. However, since the offset of these comparators is much larger than their

hysteresis, this effect is not usually limiting the performance. When necessary, measures

such as using a preamp and reducing the time constant of the input node can decrease this

hysterisis further.

Output voltages of the comparator are shown in Fig. 3-6. As one can see, two outputs of

the comparator are equal to Vdd in the reset mode. The comparator then enters the

evaluation mode and two output nodes are pulled down, but with different slopes. This

results in a voltage difference which helps the latch to make the decision.


- 31 -

Fig. 3-6. Output voltages of the capacitive based comparator

3.3 Variable capacitor An NMOS transistor is used as the variable capacitor in the capacitive based comparator.

The Capacitance versus voltage characteristic for this NMOS transistor is shown in Fig.8.

For driving this graph drain and source of an NMOS transistor is connected to each other

and gate is connected to VDD (Fig. 3-7) because in the reset mode this node is also

connected to VDD. Fig. 3-7 shows how a capacitor varies while changing the voltage

across it.

Fig. 3-7. NMOS capacitor

Vin

VDD

Out+ Out-

Voltage [V]


- 32 -

Variable capacitor

0

5

10

15

20

25

30

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Vgs [V]

Tota

l gat

e ca

paci

tanc

e [fF

]

Fig.3-8. Total gate capacitance versus Vgs This curve is consistent with the curve shown in [4]. Considering the fact that the gate of

these NMOS capacitor is connected to VDD during the reset mode, the common mode

voltage for the output of the preamp that maximizes the capacitive difference between the

two input nodes is around 0.8V, which is about one threshold voltage below the VDD. At

this voltage, slope of the curve is maximum which maximizes the sensitivity of the

capacitor to voltage changes.

In this work, the output common mode voltage of the preamp is designed to be

programmable so that it is possible to trim the common mode voltage in order to

maximize the latch sensitivity.

Simulations show that using the NMOS transistor as the input variable capacitor

minimizes the BER and using PMOS transistor slows the comparator although it might

have noise advantages.

3.4 Comparison of the comparators In this chapter we are going to compare the 3 comparators. These comparators are shown

in Fig 3-9, Fig. 3-3 and Fig. 3-5.


- 33 -

Fig. 3-9. Conventional comparator These comparators are designed in TSMC 65nm technology. W/L and number of fingers

of each transistor in the comparators are shown in table 1. It is also good to mention that

the bias current of the differential pair in the vertical latch comparator is 20uA. As will be discussed in Chapter 4, comparators will be compared for the same input

referred noise level. Table 2 shows the power consumption (average power consumption

is measured at 500MHz), layout area, offset, time constant and BER at 2GHz of these

comparators

M1

Clk

M2

M4

M9

M6 M5

M3

M10

Clk

In+ In-

Out+ Out-


- 34 -

Table 3-1. W/L and number of fingers of each transistor in the comparators

Conventional comparator

Vertical latch comparator

Capacitive based comparator

W/L- number of fingers W/L- number of fingers W/L- number of fingers M1-M2 2um/0.06um-8 0.6um/0.06um-6 0.8um/0.06um - 4 M3-M4 1um/0.06um-2 0.6um/0.06um-2 0.8um/0.06um - 2 M5-M6 1um/0.06um-2 1um/0.06um-2 1.2um/0.06um -2 M7-M8 1um/0.06um-2 1.2um/0.06um -2 M9 0.4muu/0.06um-2 1.4um/0.06um-2 0.21um/0.06um - 1 M10 2um/0.06um-10 1.2um/0.06um -16 M11-M12 0.7/0.06-1 0.5um/0.06um-2 M13-M14 0.21um/0.06um-1 0.21um/0.06um-1 M15-M16 1um/0.06um-2 1um/1um - 2 M17 1um/0.16um-2 M18-M19 1um/0.06um-2 M20-M21 1um/0.06um-2

Table 3-2. Comparison of different comparators

Conventional comparator

Vertical latch comparator

Capacitive based comparator

Average power [W] 102 128 114

Offset[mV] 11 12.5 13.2 tau[ps] 21 18 17

Layout area [m2] 85 190 85.5 BER (2GHz) 7.00E-10 5.00E-11 1.60E-11

By means of this table, one can choose the comparator which matches the best to its

application and as it was discussed previously, this can effectively improve the

performance of the total circuit.

Considering this table, it can be seen that time constant of both the vertical latch

comparator and the capacitive based comparator are almost the same, but the total power

which is burned for the comparator with the vertical latch is approximately 10% higher. It

can be seen that conventional comparator has a bigger time constant than the other two,

which indicates that this comparator it slower than the other ones. It is also good to

mention that the time constant of the comparator in Fig (3-6) varies a lot in different

process corners, therefore a lot of current needs to be burned in order to achieve small

time constant in all process corners.


- 35 -

It is also important to mention that this vertical latch comparator needs two clock signals

which increase the total power consumption of the clock generator. It also increases the

complexity of the layout. The area of this comparator is also bigger than the area

occupied by the capacitive comparator, however, the comparator of Fig. 3-6 is the best

choice when area is important. Layout of the comparators will be discussed in detail in

Chapter 5.

Offset of all these comparators are also in the same range and no circuit has any

advantage over the other one.

BER of the comparators is also calculated using the approximation which was explained

in Chapter 2. As one can see, BER of the capacitive based comparator is lower than the

other ones which make this comparator the best choice for high speed applications.

As it was mentioned previously, kick-backs of the capacitive based comparator is bigger

than the other two. The offset of these comparators are around 13mV. However, since the

kick backs are around one hundred microvolt in amplitude, it is not of a big concern.

Summary In this chapter, the vertical latch is introduced for solving the pull-up problem of the

conventional comparator. The Idea of using a variable capacitor as the input of the latch

instead of the input current is discussed, and a capacitive based comparator is designed

using this idea. In the final part of this chapter, a conventional comparator, vertical latch

comparator and capacitive based comparator are compared with respect to their BER,

power consumption, layout area and offset.

References [1] US Patent 6639430, Bult, et al. October 28,2003.

[2] A. Nikoozadeh, B. Murmann, An analysis of latch comparator offset due to load

capacitor mismatch, IEEE Transaction on circuits and systems-II, VOL. 53, NO. 12, pp.

1398-1402, December 2006.

[3] L. Samid, P. Volz, Y. Manoli, A dynamic analysis of a latched CMOS comparator,

in Proc. IEEE ISCAS., pp. 181184, May 2004.

[4] B. Razavi, Design of analog CMOS integrated circuits, New York: McGraw-Hill, pp.

39, 2003.

Chapter 4 BER Measurement Setup

- 36 -

4. BER measurement system Considering the importance of the bit-error rate (BER) of the comparators in the high

speed ADCs and the long time which is required for this measurement, we will propose a

system which can measure the BER of comparators within few seconds. This setup will

enable us to compare the BER of different comparators and study the effect of different

parameters such as bias currents, power supply, input common mode voltage and other

parameters on their BERs. It is also good to mention that there are just a few publications

on BER measurement which make this topic more interesting [1] [2] [3]. 4.1 How to detect a BER? For measuring the BER of a comparator, first we need to detect the occurrence of a bit

error. For detecting the bit-error (BE), the circuit in Fig.4-1 is proposed.

Fig.4-1. Detecting BE

The two outputs of the comparators are buffered and applied to two D flip-flops. At the

end of the evaluation time, these outputs are latched into these flip-flops. Different flip-

flop outputs indicate that no bit error happened, since the comparator has made a

decision. If these outputs are equal, it means that comparator hasnt been able to make a

decision and a bit error has occurred. This can easily be detected by making use of an

XNOR.

Latch

Latch

clk reset

reset

clk with phase shift

In+

In- Xout


- 37 -

For reducing the measurement time several measures have been taken into account. One

of the ways for increasing the number of bit errors is to increase the clock frequency.

This reduces the evaluation time and therefore the effective gain is reduced exponentially

(see Eq. 2-4) which increases the probability of the BE.

However, increasing the clock frequency also reduces the reset time, which is not really

favorable, and at certain point it might result in hysteresis. In order to prevent this

problem, it is possible to use wider reset switches, however this increases the BER since

it increases parasitic capacitance and the time constant of the output node.

The other way of reducing this effect is changing the duty cycle of the clock. By this

means, we can change the evaluation time without changing the reset time.

The other solution is to use different clocks for the comparator and the flip-flops. By

changing the phase of the clock which goes into the flip-flops, it is possible to change the

evaluation time without reducing the reset time. For a better understanding, look at Fig.4-

2.

Fig.4-2. Two outputs of the comparator and clock of the latch

A

B

Time [ns]

Out- Out+ Clock

Voltage [V]


- 38 -

If the flip-flops are latched at moment A, no bit error is made since the outputs of the

comparator are different and the comparator has made its decision. But if the latches are

clocked at moment B, this situation is considered as a bit error because both of output

signals of the comparator have the same value which means that the comparator has not

been able to decide which input has a higher voltage. This has exactly the same effect as

changing the duty cycle of the clock.

The other effective way of increasing the BER of a comparator is to reduce the amplitude

of the signal at the input of the comparator. For this reason we should make sure that

comparator is always near its switching voltage. For this purpose, the circuit of Fig.4-3 is

proposed.

Fig.4-3 Comparator with RC feedback

This RC feedback works as an averaging circuit and it always keeps the comparator near

its switching point. This also automatically cancels the offset of the comparator. Now if

we apply a sine wave to the other input of the comparator, its negative input will follow

this sine wave. Reducing the amplitude of the sine wave increases the probability of the

bit error.

Since the comparator outputs are equal in the reset mode, the output of the RC network is

not following the input sine wave for the entire duration of the clock cycle. For

Latch

Latch reset

reset

Digital Latch

In-

In+

Out+

Out-

clk

Pre amp

500uV


- 39 -

preventing this effect, a digital latch is placed at the output of the comparator (see Fig.4-

3). This digital latch holds the output of the comparator for the entire clock cycle and the

RC output follows the sine wave perfectly. The structure of this latch is shown in Fig. 4-4

Fig.4-4 Digital latch

4.2 Noise effect Bit-error rate is a stochastic process and the probability density function (PDF) of the

input signal is related to the BER. We want to compare the BER of different comparators

and for this reason we need to exactly know the PDF of the signal at the input of these

comparators. It is also known that comparators are noisy circuits and they have

considerable input referred noise. If we apply a sine wave with an amplitude which is not

at least 2 times bigger than the standard deviation of the input referred noise, the PDF of

the signal at the input is determined by the noise (which is not exactly known) and

therefore we will not be able to compare different comparators. However we dont want

to increase this amplitude because it reduces the probability of a bit error happening.

Therefore, there is an optimum value for this amplitude which we tried to find by using

different simulations.

The PDF of a pure sine wave is shown in Fig.4-5.

In+In-


- 40 -

Fig.4-5 PDF of the pure sine wave

If noise is added to the input sine wave with sigma standard deviation which is one-third

the amplitude of the sine wave, the signal of Fig. 6-a is produced which has a PDF which

is shown in Fig 4-6b.

Fig. 4-6 Sine wave plus noise with sigma which is 3 times smaller than the amplitude

of the sine wave (a) and its PDF (b)

As you can see, we can reasonably approximate this curve with a pure sine wave.

However if the noise amplitude is not small with respect to sine wave, the PDF of the

resulting waveform can not be approximated by a pure sine wave (see Fig.4-7).

(a) (b)


- 41 -

Fig. 4-7: Sine wave plus noise with sigma which is 3 times smaller than the

amplitude of the sine wave (a) and its PDF (b)

As you can see we are not able to approximate this wave with a pure sine wave anymore.

For a better understanding of how this can affect the behavior of the circuit, lets consider

Fig.4-8, which shows the waveforms at the input of the comparator when all the devices

are noise free.

Fig.4-8 Output of the RC feedback and input sine-wave with no noise

As one can see, the negative input of the comparator (i.e., coming from the RC network)

is following the sine wave. Now, lets activate the transient noise of the devices

(amplitude of the input sine wave is small and comparable to the standard of the input

(a) (b)


- 42 -

referred noise). Transient noise simulation is a transient simulation in Cadence which

models all the noise sources of the devices with transient sources and includes them in

the simulation. This kind of simulation is really effective for simulating the noise of non-

linear circuits such as comparators. Waveforms are shown in Fig.4-9.

Fig.4-9 Output of the RC feedback and small input sine-wave with transient noise

As one can see, negative input of the comparator is not following the sine wave, which is

an indication that the sine wave has a small amplitude compared to the input referred

noise. By increasing the amplitude of the sine wave, this problem is solved (see Fig. 4-

10).


- 43 -

Fig. 4-10 Output of the RC feedback and big input sine-wave with transient noise

By increasing the amplitude of the input sine wave, the output of the RC network is again

following the sine wave although the transient noise is applied. These waveforms

illustrate the importance of choosing a reasonable amplitude for the input sine wave.

Considering the fact that the standard deviation of the input referred noise of all the

comparators are designed to be 150V, amplitude of the sine wave is chosen to be 500

V.

In order to reduce the input referred noise and offset of the comparator, we added a

preamp to the comparator. This preamp has a programmable bias current (600A-800A-

1mA-1.2mA) and programmable resistive load (440-660-990). This

programmability not only enables us to achieve a gain of 3 to 5 but also lets change the

output common mode voltage of the preamp. We dont want to increase the gain of the

preamp more than this because in this way we are increasing the amplitude of the signal

at the input of the comparator, and we want to keep this signal as small as possible.

Unity-gain-bandwidth of the preamp also alternates between 1GHz and 2GHz by

choosing different bias currents and resistive loads. Putting the preamp at the input of the

comparator also helps to reduce the effect of comparator kickbacks.

A schematic of the preamp is shown in Fig.4-11.


- 44 -

Fig. 4-11 Programmable preamp

4.3 BER measurement setup

As we described previously, we are able to detect the BER. Now we need to find the

relationship between the number of bit errors and the number of clock cycles in which

these errors happened. For this purpose, well pass the clock signal through a divider and

compare this signal with the output of the XOR, which is an indication of a bit error. If a

proper division factor is chosen, the number of bit error signals and the output of the

divider would be approximately the same if they are counted in a reasonable amount of

time. This will be discussed in more detail later in this chapter.

For better understanding of the setup see Fig.4-12.

In+In-

Bias

C2 C1 C1C2

W=3 m L=0.2 m m=140

W=3 m L=0.2 m m=140 W=2 m

L=0.12 m m=120

M1 M2

M3

M4 M5 M6 M7

W=5 m L=0.06 m m=30

W=5 m L=0.06 m m=30

440 440

220 220

330 330

W=5 m L=0.06 m m=30

W=5 m L=0.06 m m=30


- 45 -

Fig.4-12 BER measurement setup

A detected bit error (which is the output of the XOR) and the output of the clock divider

are applied to counter1 in Fig. 4-12. Counter1 consists of two smaller counters which can

separately count the number of pulses at their input. So one of these counters is counting

the number of bit errors and the other is counting transitions in the divided clock signal.

When any of these counters reaches its maximum scale, a logic circuit compares it with

the value of the other counter. If the difference between the outputs of these two counters

is smaller than 33 percent, no change is necessary and the division factor is correct

because changing the division factor can only change the output of the divider by a factor

of 2 and if the difference is smaller than 33% changing the division factor just increases

this difference. However if this difference is bigger than 33%, the division factor needs to

be corrected.

Correction of the division factor is done by counter2. This counter can count up and

down, and the outputs of counter1 are the inputs to this counter.

Consider the case in which the number of bit errors is smaller than the number of divided

clock pulses. In this case, counter1 applies a pulse to the Up input of counter2. This pulse

increases the output of counter2, whic

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BER Measurement and Comparator Design