VLSI Design Lab1 by Parag

8/12/2019 VLSI Design Lab1 by Parag

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VLSI Design Lab

Presented By:

Parag Parandkar

Associate Professor, ECE Department,

Oriental University, Indore


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Types of IC Designs

IC Designs can be Analogor Digital

Digital designs can be one of three groups

Full Custom Every transistor designed and laid out by hand

ASIC (Application-Specific Integrated Circuits) Designs synthesized automatically from a high-level

language description

Semi-Custom Mixture of custom and synthesized modules


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Need for transistors

Cannot make logic gates with voltage/currentsource, RLC components Consider steady state behavior of L and C

Need a switch: something where a (small)

signal can control the flow of another signal


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6/87

Introduction to

CMOS VLSIDesign

CMOS Transistor Theory


7/87

Introduction So far, we have treated transistors as ideal switches

An ON transistor passes a finite amount of current Depends on terminal voltages

Derive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitance I = C (dV/dt) -> dt = (C/I) dV

Capacitance and current determine speed

Also explore what a degraded level really means


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9/87

MOS Capacitor

Gate and body form MOS capacitor

Operating modes Accumulation

Depletion

Inversion

polysilicon gate

(a)

silicon dioxide insulator

p-type body+-

Vg< 0

(b)

+-

0 < Vg< V

t

depletion region

(c)

+-

Vg> V

t

depletion region

inversion region


10/87

Terminal Voltages Mode of operation depends on Vg, Vd, Vs

Vgs= VgVs Vgd= VgVd Vds= VdVs= Vgs- Vgd

Source and drain are symmetric diffusion terminals

By convention, source is terminal at lower voltage

Hence Vds0

nMOS body is grounded. First assume source is 0 too.

Three regions of operation

Cutoff

Linear

Saturation

Vg

Vs

Vd

Vgd

Vgs

Vds

+-

+

-

+

-


11/87

nMOS Cutoff

No channel

Ids= 0

+-

Vgs

= 0

n+ n+

+-

Vgd

p-type body

b

g

s d


12/87

nMOS Linear Channel forms

Current flows from d to s e-from s to d

Idsincreases with Vds Similar to linear resistor

+-

Vgs

> Vt

n+ n+

+-

Vgd

= Vgs

+

-

Vgs

> Vt

n+ n+

+

-

Vgs

> Vgd

> Vt

Vds= 0

0 < Vds

< Vgs

-Vt

p-type body

p-type body

b

g

s d

b

g

s dIds


13/87

nMOS Saturation

Channel pinches off Idsindependent of Vds We say current saturates

Similar to current source

+-

Vgs

> Vt

n+ n+

+-

Vgd

< Vt

Vds> Vgs-Vt

p-type body

b

g

s d Ids


14/87

I-V Characteristics

In Linear region, Idsdepends on How much charge is in the channel?

How fast is the charge moving?


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Channel Charge

MOS structure looks like parallel platecapacitor while operating in inversion Gateoxidechannel

Qchannel=

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs-

drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate


16/87


17/87

Channel Charge

MOS structure looks like parallel platecapacitor while operating in inversion Gateoxidechannel

Qchannel

= CV

C = Cg= eoxWL/tox= CoxWL

V = VgcVt= (VgsVds/2)Vt

n+ n+

p-type body

+

Vgd

gate

+ +source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

Cox= eox/ tox


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Channel Charge MOS structure looks like parallel plate

capacitor while operating in inversion Gateoxidechannel

Qchannel= CV


V =

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs-

drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

Cox= eox/ tox


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Channel Charge MOS structure looks like parallel plate

capacitor while operating in inversion Gateoxidechannel

Qchannel= CV


V = VgcVt= (VgsVds/2)Vt

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox

= 3.9)

polysilicon

gate

Cox= eox/ tox


20/87

Carrier velocity

Charge is carried by e-

Carrier velocity vproportional to lateral E-field between source and drain

v== mE m called mobility

E = Vds/L

Time for carrier to cross channel: t= L / v


21/87

nMOS Linear I-V

Now we know How much charge Qchannelis in the channel

How much time teach carrier takes to cross

dsI


22/87

nMOS Linear I-V


How much time teach carrier takes to crosschannel

dsQI

t


23/87

nMOS Linear I-V


How much time teach carrier takes to cross

channel

ox 2

2

ds

dsgs t ds

dsgs t ds

QIt

W VC V V V

L

VV V V

ox=

WC

L


24/87

nMOS Saturation I-V

If Vgd< Vt, channel pinches off near drain When Vds> Vdsat= VgsVt

Now drain voltage no longer increases current

dsI


25/87

nMOS Saturation I-V



2dsat

ds gs t dsat

VI V V V


26/87

nMOS Saturation I-V



2

2

2

dsatds gs t dsat

gs t

VI V V V

V V


27/87

nMOS I-V Summary

2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

Shockley1storder transistor models


28/87

Example Example: a 0.6 mm process from AMI

semiconductor tox= 100

m = 350 cm2/V*s

Vt= 0.7 V Plot Idsvs. Vds

Vgs= 0, 1, 2, 3, 4, 5

Use W/L = 4/2 l

14

2

8

3.9 8.85 10350 120 /

100 10ox

W W WC A V

L L L

0 1 2 3 4 50

0.5

1

1.5

2

2.5

Vds

Ids

(mA)

Vgs

= 5

Vgs

= 4

Vgs

= 3

Vgs

= 2

Vgs= 1


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30/87

pMOS I-V

All dopings and voltages are inverted forpMOS

Mobility mp

is determined by holes Typically 2-3x lower than that of electrons mn 120 cm2/V*s in AMI 0.6 mm process

Thus pMOS must be wider to provide samecurrent In this class, assume mn/ mp= 2


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32/87

Capacitance

Any two conductors separated by an insulatorhave capacitance

Gate to channel capacitor is very important Creates channel charge necessary for operation

Source and drain have capacitance to body Across reverse-biased diodes

Called diffusion capacitance because it isassociated with source/drain diffusion


33/87


34/87

Gate Capacitance Approximate channel as connected to source

Cgs= eoxWL/tox= CoxWL = CpermicronW

Cpermicronis typically about 2 fF/mm

n+ n+

p-type body

W

Ltox

SiO2gate oxide

(good insulator, ox

= 3.90)

polysilicon

gate


35/87

Diffusion Capacitance

Csb, Cdb Undesirable, calledparasiticcapacitance

Capacitance depends on area and perimeter Use small diffusion nodes

Comparable to Cg

for contacted diff

Cgfor uncontacted

Varies with process


36/87

Pass Transistors

We have assumed source is grounded

What if source > 0? e.g. pass transistor passing V

DD

VDD

VDD


37/87

Pass Transistors

We have assumed source is grounded What if source > 0?

e.g. pass transistor passing VDD

Vg= VDD If Vs> VDD-Vt, Vgs< Vt Hence transistor would turn itself off

nMOS pass transistors pull no higher than VDD-Vtn

Called a degraded 1 Approach degraded value slowly (low Ids)

pMOS pass transistors pull no lower than Vtp

VDD

VDD


38/87

Pass Transistor Ckts

VDD

VDD

VSS

VDD

VDD

VDD

VDD

VDD

VDD


39/87

Pass Transistor Ckts

VDD

VDD V

s

= VDD

-Vtn

VSS

Vs= |V

tp|

VDD

VDD-Vtn VDD-VtnV

DD-V

tn

VDD

VDD

VDD

VDD

VDD

VDD

-Vtn

VDD-2Vtn


40/87

Back to Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration(VLSI): very many Complementary Metal Oxide Semiconductor

Fast, cheap, low power transistors

Today: How to build your own simple CMOSchip CMOS transistors Building logic gates from transistors Transistor layout and fabrication

Rest of the course: How to build a good CMOSchip

nMOS Transistor


41/87

nMOS Transistor Four terminals: gate, source, drain, body

Gateoxidebody stack looks like a capacitor Gate and body are conductors

SiO2(oxide) is a very good insulator

Called metaloxidesemiconductor (MOS)capacitor

Even though gate is

no longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+


42/87

nMOS Operation

Body is commonly tied to ground (0 V) When the gate is at a low voltage:

P-type body is at low voltage

Source-body and drain-body diodes are OFFNo current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S


43/87

nMOS Operation Cont.

When the gate is at a high voltage: Positive charge on gate of MOS capacitor

Negative charge attracted to body

Inverts a channel under gate to n-type

Now current can flow through n-type silicon fromsource through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

D

1

S


44/87

pMOS Transistor

Similar, but doping and voltages reversed Body tied to high voltage (VDD)

Gate low: transistor ON

Gate high: transistor OFF

Bubble indicates inverted behavior

SiO

2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+


45/87

Power Supply Voltage

GND = 0 V

In 1980s, VDD= 5V

VDDhas decreased in modern processes High VDDwould damage modern tiny transistors

Lower VDDsaves power

VDD= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,


46/87

Transistors as Switches We can view MOS transistors as electrically

controlled switches

Voltage at gate controls path from source todrain

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFFON

ONOFF


47/87

CMOS Inverter

A Y

0

1

VDD

A Y

GNDA Y


48/87

CMOS Inverter

A Y

0

1 0

VDD

A=1 Y=0

GND

ON

OFF

A Y


49/87

CMOS Inverter

A Y

0 1

1 0

VDD

A=0 Y=1

GND

OFF

ON

A Y


50/87

CMOS NAND Gate

A B Y

0 0

0 1

1 0

1 1

A

B

Y


51/87

CMOS NAND Gate

A B Y

0 0 1

0 1

1 0

1 1

A=0

B=0

Y=1

OFF

ON ON

OFF


52/87

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0

1 1

A=0

B=1

Y=1

OFF

OFF ON

ON


53/87

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1

A=1

B=0

Y=1

ON

ON OFF

OFF


54/87

CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

A=1

B=1

Y=0

ON

OFF OFF

ON


55/87

CMOS NOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

BY


56/87

3-input NAND Gate

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0


57/87

3-input NAND Gate

Y pulls low if ALL inputs are 1

Y pulls high if ANY input is 0

A

B

Y

C


58/87

CMOS Fabrication

CMOS transistors are fabricated on siliconwafer

Lithography process similar to printing press

On each step, different materials are depositedor etched

Easiest to understand by viewing both top andcross-section of wafer in a simplifiedmanufacturing process


59/87

Inverter Cross-section Typically use p-type substrate for nMOS

transistors

Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND V

DD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

Well and Substrate Taps


60/87

Well and Substrate Taps Substrate must be tied to GND and n-well to

VDD Metal to lightly-doped semiconductor forms

poor connection called Shottky Diode

Use heavily doped well and substrate contacts/ taps

n+

p substrate

p+

n well

A

YGND V

DD

n+p+

substrate tap well tap

n+ p+

I M k S


61/87

Inverter Mask Set

Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor


62/87

Detailed Mask Views

Six masks n-well

Polysilicon

n+ diffusion

p+ diffusion

Contact

MetalMetal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well


63/87

Fabrication Steps

Start with blank wafer

Build inverter from the bottom up

First step will be to form the n-well Cover wafer with protective layer of SiO2(oxide)

Remove layer where n-well should be built

Implant or diffuse n dopants into exposed wafer

Strip off SiO2

p substrate


64/87

Oxidation

Grow SiO2on top of Si wafer 9001200 C with H2O or O2in oxidation furnace

p substrate

SiO2


65/87

Photoresist

Spin on photoresist Photoresist is a light-sensitive organic polymer

Softens where exposed to light

p substrate

SiO2

Photoresist


66/87

Lithography

Expose photoresist through n-well mask

Strip off exposed photoresist

p substrate

SiO2

Photoresist


67/87

Etch

Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been

exposed

p substrate

SiO2

Photoresist


68/87

Strip Photoresist

Strip off remaining photoresist Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

p substrate

SiO2

n-well


69/87

n-well is formed with diffusion or ionimplantation

Diffusion Place wafer in furnace with arsenic gas

Heat until As atoms diffuse into exposed Si

Ion Implanatation Blast wafer with beam of As ions

Ions blocked by SiO2, only enter exposed Si

n well

SiO2


70/87

Strip Oxide

Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent steps involve similar series ofsteps

p substrate

n well

Pol silicon


71/87

Polysilicon Deposit very thin layer of gate oxide

< 20 (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon

layer

Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon

Heavily doped to be good conductor

Thin gate oxide

Polysilicon

p substraten well


72/87

Polysilicon Patterning

Use same lithography process to patternpolysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well


73/87

Self-Aligned Process

Use oxide and masking to expose where n+dopants should be diffused or implanted

N-diffusion forms nMOS source, drain, and n-

well contact

p substraten well

N diff sion


74/87

N-diffusion Pattern oxide and form n+ regions

Self-aligned processwhere gate blocksdiffusion

Polysilicon is better than metal for self-alignedgates because it doesnt melt during later

processing

p substraten well

n+ Diffusion


75/87

N-diffusion cont.

Historically dopants were diffused

Usually ion implantation today

But regions are still called diffusion

n wellp substrate

n+n+ n+


76/87

N-diffusion cont.

Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+


77/87

P-Diffusion

Similar set of steps form p+ diffusion regionsfor pMOS source and drain and substratecontact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+


78/87

Contacts

Now we need to wire together the devices Cover chip with thick field oxide

Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

Metalization


79/87

Metalization Sputter on aluminum over whole wafer

Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal

Layout


80/87

Layout Chips are specified with set of masks

Minimum dimensions of masks determinetransistor size (and hence speed, cost, and power)

Feature sizef= distance between source and drain Set by minimum width of polysilicon

Feature size improves 30% every 3 years or so

Normalize for feature size when describing design

rules Express rules in terms of l =f/2

E.g. l = 0.3 mm in 0.6 mm process

Simplified Design Rules


81/87

Simplified Design Rules

Conservative rules to get you started

Inverter Layout


82/87

y Transistor dimensions specified as Width /

Length Minimum size is 4l / 2l, sometimes called 1 unit

Inf= 0.6 mm process, this is 1.2 mm wide, 0.6 mmlong

S


83/87

Summary

MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches

Build logic gates out of switches

Draw masks to specify layout of transistors

Now you know everything necessary to start

designing schematics and layout for a simplechip!

SYSTEMFPGA Cell Based


84/87

MODULE

LOGIC GATE

CIRCUIT

D Q

CMOS Inverter

ASIC

Full-Custom

FPGA

PLD

Cell-Based

Gate

Arrays

X

Combinational SequentialR

E

G

DECODER

M

U

X

Simple

Basic

Complex

StaticDynamic

Parallel

Connection

Series

Connection

pn n+ +

MOSFETBipolar Diode

n pn+ n+p

DEVICE

Copy Right

August 2002

Maitham Shams

The MOSFET


85/87

Maitham Shams2002

n+ n+

Gate OxideSource Drain

Body

p-substrate

Gate

2Thin Oxide (SiO2))Polycrystalline Silicon

or Polysilicon (conductor)

Lightly doped

Bulk Contact

FieldOxide

p+ p+

Channel stop implantor field implant

2Thick Oxide (SiO2)

Heavily doped byimplantation or diffusion

For insulatingdevices from

each other

Metal-Oxide-Semiconductor Field-Effect Transistor

Unipolar and symmetric device with four terminals of Gate, Source, Drain, and Body

NMOS: n-type Source and Drain, p-type Body connected to ground (GND)

PMOS: p-type Source and Drain, n-type Body connected to power supply (VDD)

CMOS Technology


86/87

Maitham Shams2002

PMOS NMOS

p+ n+ n+

p-substrate

p+

contact cut

Polysilicon

n-well

MetalGate oxide

Complementary Metal Oxide Silicon Technology combines NMOS and PMOS

Mainstream IC Technology

in

Foreseeable Future

High Integration

Density

Simple Processing

Steps

Low PowerConsumption

Adequate SpeedHigh Reliability

MOSFET Types and Symbols


87/87

D

G

S

D

G

S

D

G

S

D

G

S

B

Analog Digital With non standardsubstrate connection

Enhancement PMOS Depletion PMOS

IDS

VGS +VTp

0

IDS

VGS

-VTp0

D

G

S

D

G

S

D

G

S

B

D

G

S

Analog Digital With non standardsubstrate connection

Enhancement NMOS Depletion NMOS

IDS

VGS+VTn0

0

IDS

VGS-VTn

Enhancement mode transistors are normally OFF (non-conducting with zero bias)

Depletion mode transistors are normally ON (conduct with zero bias)

Most CMOS ICs use Enhancement type MOS

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VLSI Design Lab1 by Parag