VLSI-Cadence

7/27/2019 VLSI-Cadence

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Name: Kirti Susan Varghese; ID. No.

Name: Manasa S Upadhyaya; ID No.

Task 1:

Design Specifications:

• A CMOS Inverter with equal

• Cload = 2p F.

Solution:

The approximate rise time and fall ti

tr = (4*Cload) / (kp* VDD)

tf = (4*Cload) / (kn* VDD)

Inverter Schematic:

SI Design Lab2 Assignment.

: 2013H123032G; 600nm technology.

:2013H123036G; 45nm technology.

rise and fall times.

e are given by



Device sizing details:

The length L has been taken as the fe

The widths of the devices are as follo

Feature size NMOS

600nm 1.5µm

45nm 120nm

Task 1.a: Power Calculation:

For Static power calculation, the DC

• With input voltage is equal to

ature size.

ws:

PMOS Model use

2.55µm nMOS4v,

175nm nMOS1v,

node voltages and DC operating points are as f

VSS (0V):

d

pMOS4v

pMOS1v

llows:



• When input voltage is equal t

The Power Dissipation values

Parameters

Input pulse frequency (MHz)

Rise time, Fall time (nsec)

Static Power Dissipation (W)

Dynamic Power Dissipation (Prac

Dynamic Power Dissipation (The

Total Power Dissipation (W)

VDD [3.3V(600nm) or 1.1V(45nm)]:

are as follows:

600nm 4

0.5 5

100 2

-21.92E-12 -2

tical) (W) -10.119E-6 -6

retical) (W) -10.89E-6 -6

-10.12E-6 -6

nm

0.12E-12

.05E-6

.06E-6

.06E-6



Task 1.b:

For Inverter driving identical inverter load, following are the delays obtained:

Task 1.c: For inverter driving 4 identical inverters as load, the delays obtained are as follows:

Parameters 600nm 45nm

TpHL (sec) 1.380E-9 0.042E-9

TpLH (sec) 0.644E-9 0.277E-9

Average delay (sec) 1.012E-9 0.160E-9



Task 2:

Design Specification:

• A CMOS inverter with its switching potential, VM equal to 25% of VDD.

Solution:

• For 600nm technology,

VM of a long channel MOSFET is given by the equation,

VM = (VDD – Vtp + Vtn*(kn/kp)^0.5) / (1+(kn/kp)^0.5)

On solving the above equation for the required specification, we get the ratio Wn/Wp

as 78:1.

As the simulation was unsuccessful with this sizing, an arbitrary sizing of 48 and 10

was carried out. The figure for sizing corresponding to 48 is attached

• For 45nm technology,Since the above equation doesn’t hold good for this technology as it is a short channel

device, sizing has been done by parametric analysis. In this analysis, the width of the

NMOS has been varied till the maximum width possible. But the desired VM could not be

achieved. The minimum possible VM achieved is 0.414mV, as shown in the figure below:

Parameters 600nm 45nm

TpHL (sec) 2.320E-9 0.464E-9

TpLH (sec) 1.583E-9 0.235E-9

Average delay (sec) 1.951E-9 0.350E-9



Task 3:

Design Specification:

• CMOS inverter with mini

Solution:

The results obtained are as fol

Parameters VDD

(V)

Sizing ratio

600nm 3.3 9.8

45nm 1.1 10

um average delay (Td).

lows:

Wp /Wn Min. TpLH

(sec)

Min. TpHL

(sec)

Mi

0.385E-9 39.86E-9 19.

8.091E-9 24.20E-9 16.

. delay (sec)

7E-9

18E-9



At a lowered power supply value, the results are:

Parameters VDD (V) Sizing ratio Wp /Wn Min. TpLH (sec) Min. TpHL (sec) Min. delay (sec)

600nm 3.26 10.78 0.498E-9 38.78E-9 18.81E-9

45nm 1.06 10 8.913E-9 22.97E-9 16.00E-9



For 45nm technology, the delays always reduce with increase in sizing ratio as shown in the

figure. But the reduction in delays is not very significant once the sizing ratio becomes greater

than 10. Hence an optimum ratio of 10 has been assumed to evaluate minimum delays in both

the cases.

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