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CSE 141 - Carro
Virtual Memory
CSE 141 - Carro
The problem:
Our computer has 32Kbyes of main memory. How can we:
a)run programs that use more than 32Kbytes?
Divide the program into chunks that fit;
Let the user worry about how to bring each chunk fromdisk to memory at the right time.
b)allow multiple users to use our computer?
Pay someone to look at each program and do the abovetasks, just thinking the multiple users programs are like ahuge single program (this is true!).
CSE 141 - Carro
Virtual Memory
Virtual memory is the name of the technique that allows usto view main memory as a cache of a larger memory space(on disk). cpu
$
memory
disk
cache
cacheing
virtual memory
CSE 141 - Carro
Virtual Memory
is just cacheing, but uses different terminologycache VM
block page
cache miss page fault
address virtual address
index physical address (sort of)
CSE 141 - Carro
Virtual Memory
What happens if another program in the processor uses the sameaddresses that yours does?
So, virtual memory provides
CSE 141 - Carro
Virtual Memory
is just a mapping function from virtual memory addressesto physical memory locations, which allows cacheing ofvirtual pages in physical memory.
CSE 141 - Carro
What makes VM different than memorycaches
MUCH higher miss penalty (millions of cycles)! If it is notin memory, it is in the disk!
Therefore:
write-through
substitution policy: LRU
CSE 141 - Carro
Mapping virtual to physical address
Page size =212=4KB
Physical pages < 4* Virtual pages!
3 2 1 011 10 9 815 14 13 1231 30 29 28 27
Page offsetVirtual page number
Virtual address
3 2 1 011 10 9 815 14 13 1229 28 27
Page offsetPhysical page number
Physical address
Translation
CSE 141 - Carro
Virtual Memory mapping
physical addresses
virtual addresses
virtual addresses
disk
We can share code or data!
Where have you seen this?
Address translation via the page tablevirtual page number page offset
valid physical page numberpage table reg
physical page number page offset
virtual address
physical address
pagetable
all page mappings are in the page table, so hit/miss is determinedsolely by the valid bit (i.e., no tag)
if we do it in software, where do we store the address translation table?
CSE 141 - Carro
Actual (somewhat) hardware
Page offsetVirtual page number
Virtual address
Page offsetPhysical page number
Physical address
Physical page numberValid
If 0 then page is not
20
Notice: what do wehave to do to save the context?
CSE 141 - Carro
Making Address Translation Fast
A cache for address translations: translation-lookasidebuffer (TLB)
CSE 141 - Carro
TLBs and caches
CSE 141 - Carro
Memory system Decstation 3100
Yes
Deliver data
CSE 141 - Carro
Modern systems: nightmare!Characteristic Intel Pentium Pro PowerPC 604
Virtual address 32 bits 52 bitsPhysical address 32 bits 32 bitsPage size 4 KB, 4 MB 4 KB, selectable, and 256 MBTLB organization A TLB for instructions and a TLB for data A TLB for instructions and a TLB for data
Both four-way set associative Both two-way set associativePseudo-LRU replacement LRU replacementInstruction TLB: 32 entries Instruction TLB: 128 entriesData TLB: 64 entries Data TLB: 128 entriesTLB misses handled in hardware TLB misses handled in hardware
Characteristic Intel Pentium Pro PowerPC 604Cache organization Split instruction and data caches Split intruction and data cachesCache size 8 KB each for instructions/data 16 KB each for instructions/dataCache associativity Four-way set associative Four-way set associativeReplacement Approximated LRU replacement LRU replacementBlock size 32 bytes 32 bytesWrite policy Write-back Write-back or write-through
CSE 141 - Carro
Virtual Memory Key Points - I
How does virtual memory provide:
Virtual Memory requires twice as many memory accesses,so we cache page table entries in the TLB.
Three things can go wrong on a memory access: cachemiss, TLB miss, page fault.
CSE 141 - Carro
Virtual Memory Key Points - II
Processor speeds continue to increase very fast
Design challenge: dealing with this growing disparity
Trends:
