PROGRAM

(i) HALF ADDER

module ha(a,b,s,c);input a,b;output s,c;

xor g1(s,a,b);and g2 (c,a,b);

endmodule

// test benchmodule ha_tb();reg a,b;wire s, c;

ha dut (a,b,s,c);

initialbegin a=1’b0;b=1’b=0;#5 a=1’b0;b=1’b=0;#5 a=1’b0;b=1’b=0;# 5 a=1’b0;b=1’b=0end

endmodule

HALF ADDER OUTPUT:

(ii) ONE BIT FULL ADDDER

module fa(a,b,cin,s,co);input a,b,cin;output s,co;wire w1,w2,w3;

xor g1(s,a,b,cin);and g2(w1,a,b);and g3(w2,b,cin);and g4(w3,cin,b);or g5(co,w1,w2,w3);

endmodule

// test bench

module fa_tb();reg a,b,ci;wire s,co;

fa dut (a,b,cin,s,co);

initialbegin a=1’b0;b=1’b=0;cin =1’b0;#5 a=1’b0;b=1’b=0;cin=1’b1;#5 a=1’b0;b=1’b=1;cin=1’b0;# 5 a=1’b0;b=1’b=1;cin=1’b1;# 5 a=1’b1;b=1’b=0;cin=1’b0;# 5 a=1’b1;b=1’b=0;cin=1’b1;# 5 a=1’b1;b=1’b=1;cin=1’b0;# 5 a=1’b1;b=1’b=1;cin=1’b1;end

endmodule

FULL ADDER OUTPUT:

(iii) FOUR BIT FULL ADDER

module fa_4(a,b,cin,s,co);input [3:0] a,b;input cin;output [3:0]s;output co;wire c1,c2,c3;

fa d1(a[0],b[0],cin,s[0],c1);fa d2(a[1],b[1],c1,s[1],c2);fa d3(a[2],b[2],c2, s[2]c3);fa d4(a[3],b[3],c3,s[3],co);

endmodule

// sub module( one bit full adder)

module fa(a,b,cin,s,co);input a,b,cin;output s,co;wire w1,w2,w3;

xor g1(s,a,b,cin);and g2(w1,a,b);and g3(w2,b,cin);and g4(w3,cin,b);or g5(co,w1,w2,w3);

endmodule

// test bench

module fa_4_tb();reg [3:0] a,b;reg cin;reg [3:0]s;reg co;

fa_4 dut (a,b,cin,s,co);

initialbegin a=4’b1000; b=4’b0110;cin=1’b0;#20 a=4’b1010;b=4’b1101;cin=1’b1;#20 a=4’b1011;b=4’b0110;cin=1’b0;#20 a=4’b1110;b=4’b0111;cin=1’b0;#20 $stop;end

endmodule

4 BIT FULL ADDER OUTPUT:

(iv) HALF SUBTRACTOR

module hs(a,b,d,bo);input a,b;output d,bo;wire abar;

xor g1(d,a,b);not g2(abar,a);and g3(bo,abar,b);

endmodule

// testbenchmodule hs_tb();reg a,b;wire d, bo;hs dut (a,b,d,bo);initialbegin a=1’b0;b=1’b=0;#5 a=1’b0;b=1’b0;#5 a=1’b0;b=1’b0;# 5 a=1’b0;b=1’b0;endendmodule

HALF SUBTRACTOR OUTPUT:

(v) FULL SUBTRACTOR

module fs(a,b,bin,d,bo);input a,b,bin;output d,bo;wire abar,w1,w2,w3;xor g1(d,a,b,bin);not g2(abar,a);and g3(w1,abar,b);and g4(w2,abar,bin);and g5(w3,bin,b);or g6(bo,w1,w2,w3);endmodule

// test bench

module fs_tb();reg a,b,bin;wire d,bo;fs dut (a,b,,bin,d,bo);initialbegin a=1’b0;b=1’b=0;bin =1’b0;#5 a=1’b0;b=1’b=0;bin=1’b1;#5 a=1’b0;b=1’b=1;bin=1’b0;# 5 a=1’b0;b=1’b=1;bin=1’b1;# 5 a=1’b1;b=1’b=0;bin=1’b0;# 5 a=1’b1;b=1’b=0;bin=1’b1;# 5 a=1’b1;b=1’b=1;bin=1’b0;# 5 a=1’b1;b=1’b=1;bin=1’b1;endendmodule

FULL SUBTRACTOR OUTPUT:

(vi) FOUR BIT FULL SUBTRACTOR

module fs_4(a,b,bin,d,bo);input [3:0] a,b;input bin;output [3:0]d;output bo;wire b1,b2,b3;fs d1(a[0],b[0],bin,b1);fs d2(a[1],b[1],b1,b2);fs d3(a[2],b[2],b2,b3);fs d4(a[3],b[3],b3,bo);endmodule

// sub module( one bit full sub)

module fs(a,b,bin,d,bo);input a,b,bin;output d,bo;wire abar,w1,w2,w3;xor g1(d,a,b,bin);not g2(abar,a);and g3(w1,abar,b);and g4(w2,abar,bin);and g5(w3,bin,b);or g6(bo,w1,w2,w3);endmodule

//testbench

module fs_4(a,b,d,bo);reg [3:0] a,b;reg bin;reg [3:0]d;reg bo;fs_4 dut (a,b,bin,d,bo);initial

begin a=4’b1000; b=4’b0110; bi=1’b0;#20 a=4’b1010;b=4’b1101;bi=1’b1;#20 a=4’b1011;b=4’b0110;bi=1’b0;#20 a=4’b1110;b=4’b0111;bi=1’b0;#20 $stop;endendmodule

4 BIT FULL SUBTRACTOR OUTPUT