Vhdl Synthesis

A VHDL SynthesisTutorial

First Edition

Valentina SalapuraMichael Gschwind

Technische Universitt WienVienna, AUSTRIA

Copyright 1997 by V. Salapura and M. Gschwind

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1. VHDL Primer2. VHDL Simulation3. Exercise 1: Simulation of an ALU4. VHDL Synthesis Primer5. Synthesis and Gate Level Simulation with

Synopsys6. Exercise 2: Synthesis of an ALU7. Modeling Sequential Logic and Finite State

Machines8. Resource Sharing9. Exercise 3: Design of a Digital Thermometer

For bug reports, please contact YDOHQWLQD#YOVLYLHWXZLHQDFDW

Disclaimer: the authors make no warranty of anykind with regard to this material, including, but notlimited to, the implied warranties or merchantabilityand fitness for a particular purpose.

Copyright 1997 by V. Salapura and M. GschwindAll rights reserved. This book may be copied for non-commercial purposes. The material from this bookletmay not be excerpted or stored in any other medium.

1 Copyright 1997 by V. Salapura & M. Gschwind

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VHDL Primer


Copyright 1997 by V. Salapura & M. Gschwind

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About this VHDL primer

u this is not a complete description of VHDLu concepts have been simplifiedu only issues and constructs related to synthesis are

explained in this overviewu refer to a VHDL textbook for a full and exact

description of the language


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VHDLu VHSIC (Very High Speed Integrated Circuit)

Hardware Description Languageu developed by DARPA Very High Speed IC Initiative

sponsored by US Department of Defenceu IEEE standard hardware description language

IEEE Std. No. 1076 since 1988u developed for design specification and validationu required for government defence projects by DoDu similar to ADA programming language

also developed by DoD


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VHDL references

u The VHDL Cookbook, by Peter J. Aschenden available via FTP

ftp://ftp.vlsivie.tuwien.ac.at/pub/hdl/ VHDL-Cookbook.tar.Z

u Peter J. AshendenThe Designers Guide to VHDLMorgan Kaufmann Publishers, Inc.

u IEEE Standard 1076-1987IEEE Standard VHDL Language ReferenceManual


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VHDL descriptions

u a design can be described in VHDL at differentabstraction levels: for the description at thebehavioral level, register-transfer level and at thegate level

u appropriate for describing both hardwarestructure and behavior

structure

A

B

Y

behavior

Y = AB + AB


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VHDL as a programming language ...u several constructs in VHDL like in programming languages

(not hardware specific)u comments : two hypens --u identifiers : letter {[underline] letter number}

7KLV1DPH WKLVQDPH 7KLVB1DPH 7KLV1DPHu numbers : integer and real, in bases 2 - 16

((DEF

u character constants : using single-quote marks =

u string constants : using double-quote marks u bit strings: B2, O 8, X 16 %;$


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Data types

u data type has to be declared - VHDL stronglytyped language

u data type specified using type definitionW\SHidentifierLVtype_definition

u basic data types scalar

integer types floating point types physical types enumeration types

composite arrays records


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Scalar data typesu integer: integer values within a specified range

W\SHsmallLVUDQJH0WR100;W\SHbit_indexLVUDQJH31GRZQWR0;

u floating point: real values within a specified rangeW\SHprobabilityLVUDQJH0.0WR1.0;

u physical: for physical quantities (mass, voltage, time...)QVPP

u enumeration: possible values are listedW\SHbooleanLVtruefalseW\SHweekendLVsaso


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Composite data types - arrays

u array: indexed set of elements of the same type one-dimensional and multidimensional constrained and unconstrained example: one-dimensional, constrainedW\SHwordLVDUUD\31GRZQWR0RIbit

example: multidimensional, constrainedW\SHregister_bankLVDUUD\0 WR31RIword

example: one-dimensional, unconstrainedW\SHwordLVDUUD\positiveUDQJH!RIbit


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Composite data types - records

u record: set of elements of different typesW\SHinstructionLVUHFRUGop_codeprocessor_opoperand1: LQWHJHUUDQJH0WR15operand2LQWHJHUUDQJH0WR15HQGUHFRUG


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Subtypes

u constrained subset of some data typeu subtypes of scalar types and arraysu examples:

W\SHdaysLVmotuwethfrsaVR

VXEW\SHweekend LVdays UDQJHsa WRso

W\SHbin_vectorLVDUUD\LQWHJHUUDQJH!RIbit

VXEW\SHwordLVbin_vector31GRZQWR0


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Objectsu object: named item having value of a specified typeu three classes of objects

constants variables signalsFRQVWDQWcrc_polbit_vector7GRZQWR0 00110011

YDULDEOHcrc_accbit_vector7GRZQWR 11000011

VLJQDOcrc_regbit_vector7GRZQWR0


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Operators

u logic operatorsDQGQDQGRUQRU[RUQRW

u arithmetic operators

DEVPRG

u relational operators !!

u concatenation operator


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Execution in VHDL

u statements in VHDL can be executed sequentially andconcurrently

u sequential statements only contained in processes detailed explanation later, see PROCESS statement

u several statements can be executed both sequentiallyand concurrently

u statements which can be executed both sequentiallyand concurrently

signal assignment procedure call statement


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Sequential and concurrent execution

u statements executed sequentially: variable assignment IF statement CASE statement LOOP statement NULL statement

u statements executed concurrently: PROCESS statement conditional signal assignment selected signal assignment component instantiation statement


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Assignments and NULL statement

u variable assignment sequential statementa new_value-- a is variable

u signal assignment can be executed both sequentially and

concurrentlyb new_value-- b is signal

u NULL statementQXOO


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IF statement

u IF statementLIcondition_1WKHQsequence_of_statements

HOVLIcondition_2WKHQsequence_of_statementsHOVHsequence_of_statementsHQGLI


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CASE statement

u CASE statementFDVHexpressionLVZKHQchoice_1 !sequence_of_statementsZKHQchoice_2 !sequence_of_statementsZKHQRWKHUV !sequence_of_statementsHQGFDVH

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LOOP statementu infinite loop

label: ORRSsequence_of_statementsHQGORRS

u basic loop statement can be extended to while or for looplabel:ZKLOHcondition_IRUparameterORRS

sequence_of_statementsHQGORRS

u NEXT and EXIT expressions optional NEXT: starts the next loop iteration EXIT: exits the loop


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Examples of LOOP statement

u while loopLoop_1ZKLOHindxmaxORRSindx indx1HQGORRS

u for loopLoop_2IRUindxLQ1WR maxORRSvector_aindx 0HQGORRS

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Subprograms

u two forms procedures functions

u defined in two parts declaration

interface

body implementation

u statements in a subprogram are executedsequentially


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Subprogram declaration

u declaration syntax procedureSURFHGXUHname formal_parameter_list;@

functionIXQFWLRQname>formal_parameter_list@UHWXUQtype_result

u declaration example procedureSURFHGXUHreadLLQRXWlinevalueRXWstd_logic

functionIXQFWLRQshlargsignedcountunsignedUHWXUQsigned

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Subprogram body

u syntaxsubprogram_specificationLVsubprogram_declarative_part

EHJLQsubprogram_statements_part

HQGname


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Example: function body

IXQFWLRQmaxLRintegerUHWXUQintegerLV

EHJLQLIL!RWKHQUHWXUQLHOVHUHWXUQRHQGLIHQGmax

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Calling of subprograms

u if calling subprograms, parameters may be passedthrough

parameter positionUHDGact_linenew_value

parameter nameUHDGvalue !new_valueL !act_line

u overloading - several subprograms with the samename

subprogram is selected using the number andtype of parameters


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Packageu encapsulated modules for structured programmingu collection of data types, constants, and

subprogramsu defined in two parts

package declaration interface description

package body implementation

u package usageXVHpackage_nameDOOXVHstd_logic_1164DOO

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Package declarationu syntax

SDFNDJHidentifierLVpackage_declarative_part

HQGidentifieru example

SDFNDJHstd_logic_1164LVW\SHstd_logicLVUX01ZWLH-

W\SHstd_logic_vectorLVDUUD\naturalUDQJH!RIstd_logic

IXQFWLRQand LRstd_logic_vectorUHWXUQstd_logic_vector

HQGstd_logic_1164


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Package body

u contains subprograms implementationsu syntax

SDFNDJHERG\nameLVpackage_body_declaration_partHQGname

u exampleSDFNDJHERG\std_logic_1164LVIXQFWLRQand LRstd_logic_vectorUHWXUQstd_logic_vectorLV

EHJLQHQGandHQGstd_logic_1164

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VHDL description of a function block

u consists of entity

description of the function block interface contains generics and ports

architecture body implementation of the block functionality multiple architecture bodies for same interface can be

definedu different performanceu different sizeu different abstraction levelsu different detailu for simulation or for synthesis


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Entity declarationu ports

input, output, inoutu generics

parameterize function blocks select templates parameters

delay (gates, ) bit width (RAM, ALU, adder, ) implementation (multiplier, divider, )

u syntaxHQWLW\identifierLVJHQHULFgenerics_constants_listSRUWport_listHQGidentifier

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Example: entity declaration

HQWLW\processor LV

JHQHULFwidthintegerSRUWclockLQstd_logicaddressLQstd_logic_vector31GRZQWR0dataLQRXWstd_logic_vector31GRZQWR0controlLQstd_logic_vector5GRZQWR0readyRXWstd_logicHQGprocessor


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Architecture body

u contains the implementation of the block functionalityu several architecture bodies may be specified for each

entity different implementations

u architecture bodies implemented at differentabstraction levels

structural block diagrams, net lists

RTL operation description using formulas

behavioral procedural description

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Architecture body syntax

u syntaxDUFKLWHFWXUHidentifierRIentity_nameLV

architecture_declarative_partEHJLQarchitecture_statements_partHQGidentifier


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Structural descriptionu block functionality described as interconnection of

smaller and simpler components net list, schematic

u hierarchical block structureu contains

components function blocks, usage of existing design entities

signals for interconnection of components

u advantage: easily mapped on hardwareu disadvantage: bad readability and overview

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Componentsu for structural descriptions, interconnected with signalsu existing entities used as componentsu component described at different abstraction levels

different levels of detailu component used in a structural description has to be

declared in the architecture body declaration part

instantiated in the architecture body statements part


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Component declarationu in architecture body declaration partu syntax

FRPSRQHQWidentifierLVJHQHULFgeneric_constants_listSRUWport_listHQGFRPSRQHQW

u exampleFRPSRQHQWcounter JHQHULFN: integerSRUWclock resetLQstd_logic

yRXWstd_logic_vector0 WR N-1HQGFRPSRQHQW

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Component instantiation

u in architecture body statements partu specify connections and parameters for generic

parameterizable modulesu syntax

labelnameJHQHULFPDSgeneric_listSRUWPDSport_list

u exampleu3counterJHQHULFPDS4SRUWPDSclk, n245, n254

parameter for parameterizable blocks

connections


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Structural description - example

u multiply-and-accumulate function blocku block diagram

ACC

FORFN LQ LQ

UHVXOW

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MACC Entity

HQWLW\ maccLVSRUWin1LQstd_logic_vector7GRZQWR0in2LQstd_logic_vector7GRZQWR0clockLQstd_logicresultRXWstd_logic_vector15GRZQWR0HQGmacc


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Architecture body - structural descriptionDUFKLWHFWXUHstructure RImaccLVVLJQDOmul_resstd_logic_vector15GRZQWR0FRPSRQHQWmultSRUWabLQstd_logic_vector7GRZQWR0yRXWstd_logic_vector15GRZQWR0HQGFRPSRQHQWFRPSRQHQWaccSRUWaLQstd_logic_vector15GRZQWR0clkLQstd_logicyRXWstd_logic_vector15 GRZQWR0HQGFRPSRQHQWEHJLQmultiplymultSRUWPDSin1in2mul_resaccumaccSRUWPDSmul_resclockresultHQGstructure

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RTL description

u register transfer levelu description at higher abstraction levelu operations described with formulaeu usage of signals

for value exchange between formulaeu functionality described as calculation of new signal

value from other signals\Q I\N\O

u advantage: good readabilityu disadvantage: complicated mapping on hardware


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Simplified VHDL simulation model

u execution of a VHDL description statements in an endless loop all statements executed repeatedly signal change visible only in the next simulation

loop iteration signals introduce one unit delay abstract model of hardware delay

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Consequences of signal delay

u in architecture body all statements executedconcurrently

corresponds to hardware where all componentsand wires concurrently active

u order of concurrent statements not importantu exact delay of signals possible using after clause


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Execution of concurrent statements

u exercise: write an RTL description for the following

block diagrama b

y1

y2

y3

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SolutionHQWLW\simpleLVSRUWabLQstd_logicy1y2y3RXWstd_logicHQGsimple

DUFKLWHFWXUHarchRIsimpleLVEHJLQy2 aDQGQRWby1 QRWaDQGby3 aRUQRWaDQGbHQGarch


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AFTER clause

u defines exact delayu syntax

target value_expressionDIWHUtime_expression

u exampleout2 QRWin2DIWHU5 nsin2 out1DIWHU1 ns

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Concurrent statements

u signal assignmentu conditional signal assignment

corresponds to sequential IFu selected signal assignment

corresponds to sequential CASE


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Conditional signal assignments

u concurrent IFu syntax

target ^waveformZKHQconditionHOVHwaveform

u examplereset 01DIWHU10 nsZKHQshort 1HOVH01DIWHU25 ns

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Selected signal assignment

u concurrent CASEu syntax

ZLWKexpression VHOHFWtarget ^waveformZKHQchoicewaveformZKHQchoice

u exampleZLWKcodeVHOHFWresult a b ZKHQadditionabZKHQsubtract


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MACC - RTL DescriptionDUFKLWHFWXUHrtlRImacc LVVLJQDOmul_resregstd_logic_vector15GRZQWR0

EHJLQreg regin1 in2 ZKHQclock DQGclockHYHQWUHVXOW regHQGrtl

u VHDL defines attributes for various object types for signals: HYHQW - signal value has changed

rising clock edge

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Behavioral description

u descriptions at high abstraction levelu behavioral VHDL similar to normal

programming languagesu encapsulated in VHDL processesu advantages

simple and quick description high simulation speed

u disadvantages complicated mapping on hardware less detailed description


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Process statement

u concurrent statement in architecture body executed concurrently with other statements

u contains sequential statements encapsulated statements executed sequentially

u variables used in a process variables change value immediately, like in

normal programming languagesu signals can still be used

semantics differ from variable changes onlyvisible in next iteration of process

useful for communication with other concurrentelements in architecture body

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Process statement: syntax

SURFHVV>sensitivity_list@

process_declarative_part

EHJLQ

process_statements_part

HQGSURFHVV


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Process statement: example

P22SURFHVVclockresetEHJLQLIreset 1WKHQ reg 0000HOVLIclock 1DQGclockHYHQWWKHQreg 1100HQGLIHQGSURFHVV

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Building a VHDL description

u in a single VHDL design used many differentpackages, architecture bodies and entities

u active components (architecture bodies, packages)for a particular design selected using

libraries configurations


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Library

u encapsulates various related componentsu identified with a logic nameu design descriptions compiled in libraries for

simulation and synthesisu order of compilation important

primary library units have to be compiled first package declarations, entities, configuration declaration

secondary library units package bodies, architecture bodies

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Using libraries

u referenced with use clauseu example

OLEUDU\IEEEXVHIEEEstd_logic_1164DOOXVHIEEEstd_logic_arithDOO

u library work always selected working library need not to be referenced


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Configuration

u configuration selects architecture body for entities entities for components generics for components

u selects architecture body for each instance, e.g. architecture body with optimized timing for

timing critical parts architecture body with minimal area for area

critical parts behavioral description for fast simulation

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Configuration syntax

FRQILJXUDWLRQidentifierRIentity_nameLV

use_clauseIRUarchitecture_name use_clauseIRUblock_nameHQGIRUHQGIRUHQGidentifier;

u first hierarchical for clause specifies architecturebody


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Configuration: exampleDUFKLWHFWXUHsimulateRIadder LVFRPSRQHQWhaddSRUWHQGFRPSRQHQW

EHJLQ%haddSRUWPDS%haddSRUWPDS

HQGsimulateFRQILJXUDWLRQmixedRIadder LVIRUsimulateIRUB1haddXVHHQWLW\workhaddrtlHQGIRUIRUB2haddXVHHQWLW\workhaddsynthHQGIRUHQGIRUHQGmixed

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Standard logic

u standardized data types for portably describingsignal values in VHDL

u IEEE standard multivalue logic system for VHDLmodel interoperability (Std_logic_1164)

IEEE Std. No. 1164-1993 defined in ,(((VWGBORJLFB package

u should be supported by all simulators andsynthesis tools

u simple mapping on hardwareu arithmetic operations on VWGBORJLF standardized

in IEEE 1076.3 synthesis package Numeric_Std


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Standard logic data types

u data type VWGBORJLF:8 - not initialized; - unknown, strong - 0, strong - 1, strong= - high impedance (tri-state): - unknown, weak/ - 0, weak+ - 1, weak - dont care

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Other standard data types

u VWGBORJLFBYHFWRUu VWGBXORJLF, VWGBXORJLFBYHFWRU

unresolved VWGBORJLF several drivers drive single bus / wire

u VLJQHG, XQVLJQHG defined in IEEE 1076.3 Numeric_Std array of VWGBORJLF with integer semantics


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Data type conversion functions

u VHDL strongly typed - but not hardware synthesis tools have to provide trivial mapping

of functionsu in synthesis package ,(((VWGBORJLFBDULWKu most important conversion functions

FRQYBLQWHJHUFRQYBXQVLJQHGFRQYBVLJQHGFRQYBVWGBORJLFBYHFWRU

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VHDL Simulation


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Introductory note

u this collection only gives short overview ofsimulation

u concepts have been simplifiedu intended to give basic understanding of VHDL

simulationu for full information on VHDL simulation check

VHDL simulation text book

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Simulation

u for validating VHDL Modelsu simulation shows

whether errors are found for given test vectors not that the design is correct

u quality of test vectors is critical for quality ofsimulation

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Simulation development

u 1980 - CAE simulation at the gate level

long simulation time

u 1990 - High level approach simulation at behavioral and RTL levels

usage of test benches procedural description of test vectors simple and quick design at higher abstraction level faster simulation because less detail required

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Usage of simulation

u VHDL system simulation behavioral and RTL description

u post-synthesis simulation and timing analysis at the gate level

u sign-off simulation after layout and routing

exact timing analysis

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Simulation model

u discrete event simulationu simulation controlled by events event driven

simulation event the value of a signal had changed change of a signal is not immediately executed assignment of new signal values scheduled along

a time axis

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Simulation algorithm

u defined by IEEE VHDL standard 1076u simulation starts with the initialization phase

simulation time = 0 all objects initialized

u iterate 2 stage simulation cycle propagation

all transactions (signal changes) scheduled for thissimulation time executed

evaluation execute all VHDL modules which react to events occurring

in the first stage schedule new signal changes

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Delta method

u two dimensional time

u guarantees compatibility between different simulators determinism

0t0

t0 + 1 ns

time0

1 2delta

1 2

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Signal assignmentu without after clauseu input a is 0 at t0

DUFKLWHFWXUHsimpleRIdemoLVEHJLQb ac QRWb

HQGsimple

0 1 2

D E F 8

D E F 8

t0

t1

D E F

time

delta

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Signal assignment (2)u with after clauseu input a is 0 at t0

DUFKLWHFWXUHsimpleRIdemoLVEHJLQb aDIWHU 5 nsc QRWbDIWHU1 nsHQGsimple

0D

E F 8

D E F 8

t0

t0 + 5 ns

D E F

time

delta

t0 + 6 ns

0

0

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Controlling simulation

u evaluate only the modules affected by changed signals

activation list for concurrent statements sensitivity list for processes

u propagate only the signals whose value should change

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VHDL for simulation

u statements for describing time flow in thesimulation

after for time flow of signal assignmentsa 11110000DIWHU100 ns

wait to start and stop a processZDLWIRU10 nsZDLWXQWLOreset 1;ZDLWRQclockHYHQW

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Test benchu defines the stimuli of a designu consists of two components

UUT (unit under test) tested design

TG (test generator) generates stimulus for the design collects the designs response, compares with reference values

TG UUT

TEST BENCH

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Types of test benchu system test bench

describes the design environment designer know how

u comparison test bench compares the implementation with a reference

model reference model = expected simulation results at higher

abstraction levels or golden device difficulties with timing differences between the

implementation and the reference model

UUT GD

TG =?

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Building a test benchHQWLW\TBLVHQGTB

DUFKLWHFWXUHTBARITBLV

declarative_part_signals_componentsEHJLQinstantiate_UUT_and_other_componentsand_optionalbehavioral_description_of_TG

HQGTBA

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Putting together a simulation model

u arranging a configuration connecting objects

component entity entity architecture generics

u exampleFRQILJXUDWLRQcfg_tbRITB LVIRUTBAIRUuutu_entityXVHHQWLW\worku_entityu_archHQGIRUHQGIRUHQGcfg_tb

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Simulation of VHDL modelsu VHDL model has to be

compiled (analyzed) simulated

u simulation using Synopsys interpreted

intermediate format (byte code) similar to VHDL source code easy debugging slow simulation

compiled translated to machine code fast simulation

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Working environment for Synopsys

u setup file in the working directory.V\QRSV\VBYVVVHWXS

contains data path for system librariesu library ZRUN

contains analyzed elementsu typical working directory - listing

OVV\QRSV\VBYVVVHWXS6\QRSV\VFRQILJXUDWLRQYKGOBILOHYKG9+/VRXUFHILOHZRUNFRQWDLQVDQDO\]HGVRXUFH

u Synopsys online documentationLYLHZ

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Compilation with Synopsys

u compilation command (for library work)YKGODQYKGOBILOHYKG

u compilation to other librariesYKGODQYKGOBILOHYKGZOLEUDU\BQDPH library name has to be specified in.V\QRSV\VBYVVVHWXS

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Simulation with Synopsysu Synopsys VHDL debugger - YKGOGE[u select design

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Useful commands

u WUDFH signal selection for waveforms

u FG moving through the program hierarchy

u VWHSQH[W execute simulation in steps

u UXQWLPHBH[SUHVVLRQ simulation start

u LQFOXGH usage of scripts

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Vhdldbx - working window

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Vhdldbx - waveforms

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Simulation example:MACC entity

XVHworkDOO(17,7

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Simulation example:MACC architecture

$5&+,7(&785(macc_arch2)macc,66,*1$/new_valregLQWHJHUUDQJH0WR65535%(*,1Regist352&(66clockreset%(*,1,)reset 7+(1reg (/6,)clock(9(17DQGclock 7+(1reg new_val(1,)(1352&(66new_val reg input1input2DIWHU15 nsout_reg reg(1macc_arch

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Simulation example:Oscillator for clock signal

(17,7

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Simulation example:MACC test bench

HQWLW\TBLVHQGTB

$UFKLWHFWXUHArch RITBLV6,*1$/in1in2LQWHJHUUDQJH0WR2556,*1$/resclockLQWHJHUUDQJH0WR16,*1$/resultLQWHJHUUDQJH0WR65535

&20321(17macc3257input1input2,1LQWHJHUUDQJH0WR255

resetclock,1LQWHJHUUDQJH0WR1 out_reg287LQWHJHUUDQJH0WR65535(1&20321(17

&20321(17oscil3RUWtxc287LQWHJHUUDQJH0WR1(1&20321(17

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Simulation example:MACC test bench contd

%(*,1

UUTmacc32570$3in1in2resclockresultclk oscil32570$3clock

TBP 352&(66%(*,1in1 0in2 0res 1ZDLWIRU70 nsreset cycleres 0ZDLWIRU80 nsin1 115in2 78input dataZDLWIRU100 nsin1 20 new input dataZDLWIRU10 nsin2 50

ZDLWIRU100 ns(1352&(66HQGArch

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Simulation example:MACC configuration

FRQILJXUDWLRQcfg_tb_maccRITB LV

IRUArch

IRUuutmacc

XVHHQWLW\workmaccmacc_arch

HQGIRU

HQGIRU

HQGcfg_tb_macc

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Simulation example:Tracing MACC operation using waveforms

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(

Exercise 1VHDL design and simulation


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(

ALU design and simulation

u describe an ALU with following properties in VHDL 2 data inputs, 1 output

data type integer range 0 to 256

control input for operation selection choose appropriate encoding for function selection: enumeration

data type, integer, bitstring

ALU operations delay SDVV$SDVV%QV QRW$$DQG%$RU%$[RU%QV $%$%QV $%QV

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(

Complete the following tasks

u describe the ALU in VHDLu develop a test bench for simulationu verify ALU functionality using functional

simulationu explain your design decisions and their impact

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VHDL Synthesis Primer


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Synthesis

u automatic translation from one abstraction level toa lower abstraction level

generates more detailed descriptionsu hardware structure directly inferred from an HDL

description hardware not specified explicitly coding style important for efficiency

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Gajskis Y-Diagram

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Design steps in Y-Diagram

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Synthesis at different abstraction levels

u system level synthesisu high-level synthesisu RTL synthesisu logic-level synthesisu technology mapping

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Theory synthesis at high abstraction levels

u system level synthesis partitioning of a system into subsystems and

definition of its algorithmsu behavioral synthesis (high-level synthesis)

translation from a behavioral into an RTLdescription

explore different architectures design divided in data and control path

(resource allocation, scheduling, resourceassignment)

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Theory RTL and logic synthesis

u RTL synthesis performs control and data path synthesis resource allocation and sharing

maps RTL description to Boolean functions

u logic-level synthesis design described with combinational logic

(Boolean functions) and sequential elements description mapped to the gate level and

optimized

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Theory Technology mapping

u technology mapping abstract gates mapped to technology elements function blocks sometimes mapped to macros

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and reality

u system synthesis does not existu behavioral synthesis - first tools available

for example, Behavioral Compiler fromSynopsys

u RTL + logic synthesis available today in good tools no difference between these steps for example, Design Compiler from Synopsys

u pure logic synthesis available for a long time, e.g. Espresso optimization of Boolean equations

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Advantages of synthesis

u shorter design timeu simplifies modularity and simple integration of

designu management of design complexity

10M transistor designs already exist, andgrowing!

u facilitates optimization of the whole design removal of redundant functions

u enables simple porting of design to othertechnologies by re-synthesizing it

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Intellectual property (IP) theoryu how to make 100 Mgate designs

buy already existing design blocks from IPvendors

x86 VHDL model chip set model SCSI controller model Ethernet controller modelequals PC on a chip

synthesize all blocks in a single chipu todays integration of components on printed

circuits board tomorrows integration ofhardware descriptions on a chip

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Disadvantages of synthesis

u synthesized hardware depends on coding styleu synthesis efficiency depends on

synthesis tools used target technology less portable than ideally possible

u less control over the resulting hardwareu hand design of particular blocks may be better than

the synthesis result but hand design probably depends on technology

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HDL - hardware description languages

u synthesis based on HDLu most common HDLs: VHDL and Verilogu developed for simulation, not for synthesis

synthesis semantics sometimes different fromsimulation semantics

what you synthesize is not always what yousimulate

u synthesis basics similar for all HDLs

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Verilog

u mostly used in the USu developed by Gateway Design Automation

software company 1983u similar to C programming languageu data types defined by language, not by user

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VHDL

u mostly used in Europeu developed by DoD required for defense contractsu strong typing systemu similar to ADA by design

also developed by DoD usage of data types and libraries similar syntax

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Design flowRTL VHDL

RTL Simulation

Gate-Level Simulation

Sign-Off Simulation

Translationto Gates

Gate-LevelOptimizationS

ynth

esis

FunctionOK?

Function& Speed

OK?

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Synthesis tools

u RTL and logic synthesis widely used forapproximately 5 years

u up to date hardware design methodu synthesis tools well developed, but quality of

synthesis results varies Synopsys, Compass, Powerview, Cadence, ...

u some synthesis tools ignore configurationspecification and/or user-defined libraries

u some synthesis tools do not support resource-sharing

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Mapping HDL to hardware

u in an HDL description, hardware is not explicitlydefined

u structure of hardware inferred from the structureof a HDL description

the quality of synthesized hardware dependson coding style of an HDL description

possibly also depends on synthesis tools andtarget technology

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HDL translation for synthesis

u translation in two steps (as performed by SynopsysDesign Compiler)

module generator - modules inferred from anHDL description

modules for simple operations technology independent

module mapping to gates technology specific makes gate-level design optimization possible

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Synthesis environment

u VHDL based synthesisu synthesis tools GHVLJQBDQDO\]HU from Synopsys

probably the best synthesis tool currentlyavailable

u target technology (for our experiments) is theASIC technology LSI 10K

available in the Synopsys standard distribution 1.5, double metal, single poly

approximately 10 years old

technology library specified in file V\QRSV\VBGFVHWXS

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Synthesis using Synopsysu invoke GHVLJQBDQDO\]HUu VHWXS GHIDXOWV selected technology libraries

FRPPDQGZLQGRZ command line input

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Synthesis using Synopsys

u synthesis executed in two steps1. step: ILOH UHDG read in VHDL files

macro for commands DQDO\]H and HODERUDWH

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Mapping VHDL constructs

u synthesis tools map VHDL constructs to three hardwareelements

combinational logic multiplexors memory elements

u what hardware is generated from arithmetic, logic and comparison operators IF and CASE statements indexes and arrays process statement

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Arithmetic and logic operationsu arithmetic and logic operation are mapped to

combinational logic/,%5$5

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Result of synthesis

u step 1: modules for simple operatorsu step 2: WRROV GHVLJQRSWLPL]DWLRQ

modules mapped to gate level and optimized

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Comparison operators

u comparison operators are mapped tocombinational logic

(17,7

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Array indexesu from a variable index - multiplexor

u from a constant index - wireY A3

(17,7

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IF statement for memory elementsu if not all states of an IF statement are defined, a

memory element is inserted

(17,7

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Flip-flopu controlled with clock edge

(17,7

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CASE statement and dont careu CASE statements are mapped to multiplexorsu dont care for better optimization

";" in VWGBORJLF for synthesis$5&+,7(&785(arch2)casing,6%(*,1352&(66A BCDSel%(*,1&$6(6HO,6:+(10 !Y A:+(11 !Y B:+(12 !Y C:+(13 !Y D:+(1Others !

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Example design - MACC

u read the VHDL descriptionILOH UHDG PDFFYKG 2.

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Example design - MACCu design optimization

WRROV GHVLJQRSWLPL]DWLRQ 2.ILOH VDYHDV %9+/6;1)

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Synthesis and Gate LevelSimulation with Synopsys


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Synopsys design compiler

u dominant synthesis tool set in the marketu probably the best synthesis tool available todayu synthesis executed in two steps

module generator VHDL description mapped to modules modules for operators technology independent

technology mapping modules mapped to gates technology specific starting point for the optimization at the gate level

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Two synthesis steps

u step 1: simple operators mapped to modulesu step 2: operators mapped to gates and optimization

at the gate level

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What Synopsys offers

u various options for exact specification of technology and working environment

target technology definition max fan-out, max transition, max capacitance

design optimization area and timing optimization clock specification various optimization efforts various optimization methods available (boundary

optimization, flatten, Boolean)

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What can Synopsys do

read in and use user-defined libraries, packages,etc.

generate design reports design complexity (number of gates/technology elements) design speed used resources (also as macros from libraries)

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Starting design compiler

u with GHVLJQBDQDO\]HU for graphical front-end

u with GFBVKHOO for command line orientedinterface

graphical front-end translates pull-down menuselections to script commands

can be seen in command window

not all commands can be selected using thegraphical interface

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Selecting commandsu selecting choices in pull-down menusu writing commands in command window

open with VHWXS FRPPDQGZLQGRZu directly in GFBVKHOO

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Working in batch modeu using scriptsu scripts for synthesis control

advantageous for complex designs synthesis and optimization executed unattended over night

or longer time also useful for less complex designs

u each menu selection can be substituted with ascript command

u for advanced usage wider command selection reproducible script documents selected

synthesis and optimization reduced setup work for repeated synthesis

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Script language

u design compiler controlled using script languageu various command classes for

script control reading and saving designs target technology definition translation of VHDL programs definition of module interfaces optimization control report generation

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Script control

u menu selectionVHWXS H[HFXWHVFULSW

u include scripts in command window and in scriptfilesLQFOXGHVFULSWBILOHBQDPH

u in program GFBVKHOOGFBVKHOOIVFULSWBILOHBQDPH

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Reading and saving designs

u support for various design formats VHDL, Verilog, DB, XNF, EDIF, PLA ...

u reading designs with UHDG example: UHDGI[QIPDFF[QI

u saving designs with ZULWH option -KLHUDUFK\saves all submodules example:ZULWHIGEKLHUDUFK\RXWSXWPDFFGE

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Technology definition

u specified in file V\QRSV\VBGFVHWXSu menu selection VHWXS GHIDXOWV

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DesignWare library

u module generatoru contains different library elements

implementation of operators +, - *, / different modules like RAMs, shift registers, etc.

u various implementations for same functionality different trade-offs, area or speed optimized

u appropriate implementation selected automaticallyin Synopsys as a result of specified designconstraints

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File .V\QRSV\VBGFVHWXS

u an example of file .V\QRSV\VBGFVHWXSVHDUFKBSDWK ^XVUWRROVV\QRSV\VOLEUDULHVV\Q

WDUJHWBOLEUDU\ OVLBNGE

OLQNBOLEUDU\ OVLBNGEV\PEROBOLEUDU\ OVLBNVGE

GHVLJQZDUH

V\QWKHWLFBOLEUDU\ V\QWKHWLFBOLEUDU\^GZVOGEGZVOGEGZVOGEGZVOGEGZVOGE

OLQNBOLEUDU\ OLQNBOLEUDU\^GZVOGEGZVOGEGZVOGEGZVOGEGZVOGE

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Translation of VHDL programs

u in two steps analyze

translates the design into the working library

elaborate generates design structure from description in the working

library

u menu selectionsILOH DQDO\]HILOH HODERUDWH

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Translation of VHDL programs

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Different design viewsu design represented at different hierarchical levels

module (all modules read) entity (interface) architecture (implementation)

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Definition of module interfaces

u ICs require special drivers for external signals pads

u definition of external ports withVHWBSRUWBLVBSDG

typical examples VHWBSRUWBLVBSDGDOOBLQSXWV VHWBSRUWBLVBSDG

u insertion of pads withLQVHUWBSDGV

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Commands for optimization control

u design optimization area minimization timing constraints

u controlling of different optimization methods VHWBERXQGDU\BRSWLPL]DWLRQFXUUHQWBGHVLJQ

constants on ports propagated to submodules

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Area optimizationu menu selection DWWULEXWHV RSWLPL]DWLRQFRQVWUDLQWVGHVLJQFRQVWUDLQWV

u command VHWBPD[BDUHD

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Signal run time optimization

u menu selectionDWWULEXWHV RSWLPL]DWLRQFRQVWUDLQWV WLPLQJFRQVWUDLQWV

u command VHWBPD[BGHOD\ various options (rise, fall) path specification with start and/or end pointVHWBPD[BGHOD\IURPSRUWWRSRUW

u exampleVHWBPD[BGHOD\WRRXWBSRUW

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Synthesis start

u optimization constraints have to be set beforestarting synthesis

u synthesis started withFRPSLOH

example: FRPSLOHPDSBHIIRUWKLJK additional synthesis control options available

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Starting synthesis

u starting withWRROV GHVLJQRSWLPL]DWLRQ

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Generating design reports

u menu selectionDQDO\]H UHSRUW

u report on resources usedUHSRUWBDUHD

u signal delay time reportUHSRUWBWLPLQJ

u report on FPGA resourcesUHSRUWBISJD

u etc. etc.

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Area reportu example: area consumption of design MACC

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Timing report

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Selecting current design

u all commands executed only on current designu current design selection

in GHVLJQBDQDO\]HUclicking on the module

in GFBVKHOOFXUUHQWBGHVLJQPRGXOHBQDPH

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Other useful commandsu XQJURXS and JURXS

for creating and removing hierarchical levels e.g., to enable optimization over various subdesigns

exampleXQJURXSDOO

u GRQWBWRXFK selected module is not further optimized

u FKDUDFWHUL]H transfers design constraints from higher

hierarchical level to submodules

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Example of script fileUHDGIYKGOtest_add.vhdFXUUHQWBGHVLJQadd8_impl1LQFOXGHhandle_design_scriptUHSRUWBDUHD!add8_area.outUHSRUWBWLPLQJSDWKfullGHOD\maxPD[BSDWKV1QZRUVW1!add8_time.out

ZULWHIGEKLHUDUFK\Radd4_impl1.db

u file handle_design_scriptVHWBSRUWBLVBSDGXQJURXSFXUUHQWBGHVLJQVHWBERXQGDU\BRSWLPL]DWLRQFXUUHQWBGHVLJQFRPSLOHXQJURXSBDOOPDSBHIIRUWPHGLXP

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Gate level simulation

u to simulate at the gate level generate a simulation library from the synthesis

library analyze the simulation library reference the simulation library in gate-level

description generate an SDF file from a design start the simulation using the SDF file

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Standard delay format (SDF)u SDF is a standard delay format

portable description of design delays supported by many EDA tools

u contains timing information of a synthesized designu for back-annotating design timing with gate-level

simulation

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Generating simulation library

u simulation library is generated from the synthesislibrary file OLEBQDPHGEOLEDQDUFKPRGHOOLEBQDPHGE option -arch specifys one of five timing models

IWEP accurate timing model, slowest simulation XGVP all cells with 1ns delay, fastest simulation IWVP each cell with accurate timing, less accurate than

IWEP, slower simulation than XGVP IWJV as accurate as IWEP, fast simulation (optimized

for Synopsys) YLWDO vital model

u results of compilation are filesOLEBQDPHBFRPSRQHQWVYKGandOLEBQDPHB)760YKG(

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Analyzing simulation library

u simulation library has to be analyzedYKGODQZOLEBQDPHOLEBQDPHB)760YKG(OLEBQDPHBFRPSRQHQWVYKG

u timing model library files are compiled and storedin the simulation library OLEBQDPH

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Using the simulation library

u simulation libraries are similar to other librariesu simulation library has to be

specified in the setup file referenced in the VHDL description

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Specifying simulation library

u simulation library has to be specified in the setupfile V\QRSV\VBYVVVHWXS

u for simulation library generated from LSI 10ksynthesis library example

insert in the file V\QRSV\VBYVVVHWXS/6,B.6

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Generating an SDF file from a design

u SDF file contains timing information of asynthesized design

required for gate level simulationu generation in command window

select file format for VHDL simulationFKDQJHBQDPHVUXOHVYKGOKLHUDUFK\ generate SDF fileZULWHBWLPLQJIRUPDWVGIRXWSXWVGIBILOHBQDPH

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Starting the gate level simulation

u gate level simulation uses the timing information froman SDF file

u gate level simulation has to be started in commandmodeYKGOVLPVGIBWRSWEXXWVGIVGIBILOHBQDPHFIJBWEBQDPH

option VGIBWRS specifies the design described bySDF file is (UUT in the above example)

the last argument (FIJBWEBQDPH) specifies the testbench configuration

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Simulation in command mode

u command mode simulator YKGOVLP uses the samecommands as the window mode YKGOGE[WUDFH

signal selection for waveforms

FG moving through the program hierarchy

VWHSQH[W execute simulation in steps

UXQWLPHBH[SUHVVLRQ simulation start

LQFOXGH usage of scripts

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Simulation example:MACC gate-level descriptionOLEUDU\,(((OLEUDU\/6,B.XVH,(((VWGBORJLFBDOOXVH/6,B.&20321(176DOOHQWLW\PDFFLVSRUWLQSXWLQSXWLQVWGBORJLFBYHFWRUGRZQWRUHVHWFORFNLQVWGBORJLFRXWBUHJRXWVWGBORJLFBYHFWRUGRZQWRHQGPDFFDUFKLWHFWXUH6

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Simulation example:MACC SDF file(/$

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Simulation example:waveforms

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(

Exercise 2 Synthesis and gate level

simulation


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(

Synthesis and gate level simulation

u use ALU description from exercise 1 as a startingpoint

u modify ALU to use VWGBORJLFBYHFWRU forinputs and output

u synthesize the ALU for an ASIC target technology e.g., LSI 10k included in Synopsys standard

distribution

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u synthesize and optimize the ALU optimized for area optimized for timing

u compare results generated by area and timingoptimization

u explain why DIWHU clause is ignoredu simulate the synthesis results using test bench from

exercise 1u explain why only a subset of VHDL can be

synthesized

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Modeling Sequential Logicand Finite State Machines


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Building complex VHDL models

u VHDL supports modeling at different abstractionlevels

language constructs for each abstraction level behavioral level

functions, procedure calls, processes

register transfer level (RTL) concurrent statements and formulae

structural level (VHDL netlist) components, component instantiation, component

interconnections

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Hybrid descriptions

u language constructs for different abstraction levelscan be mixed in a single description

using constructs of all abstraction levels in singlearchitecture

process for algorithm description RTL formulae component instantiation

useful for simulation and synthesis re-use of existing modules in description of new modules

through component instantiation mixing of descriptions with different amount of detail

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Component declaration and instantiationu component declared in the declaration part of an

architecture bodyu syntax

FRPSRQHQWidentifierLVJHQHULFgeneric_constants_listSRUWport_listHQGFRPSRQHQW

u component instantiated in the statements part of anarchitecture body

u syntaxlabelnameJHQHULFPDSgeneric_listSRUWPDSport_list

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Hybrid design example: MACC$5&+,7(&785(demo_arch2)macc,6&20321(17multy3257in1in2,1std_logic_vector3GRZQWR0res287std_logic_vector3GRZQWR06,*1$/new_valregresstd_logic_vector3 GRZQWR0%(*,1 Reg:352&(66clockreset%(*,1,)reset 17+(1reg 0000(/6,)clock(9(17$1clock 17+(1reg new_val(1,)(1352&(66 MultiplymultySRUWPDSinput1input2resnew_val regresout_reg reg(1demo_arch

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Hybrid design example: MACC schematic

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Synthesis of sequential logic

u to synthesize sequential logic need to define clock(s) requires special treatment

stronger drivers uniform distribution

memory element type selection of flip flops and latch types to be generated by

logic synthesis type of memory element (whether flip flops or latches are

used) depends on VHDL description style

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Setting the clocku menu selection DWWULEXWHV FORFNVVSHFLI\

for selected port of a module set clock period and edges

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Clock specification

u in dc_shell and in command windowFUHDWHBFORFNQDPHclockSHULRG20ZDYHIRUP^010ILQGSRUWclock

u explanationQDPHclock

specify clock nameSHULRG20

period of the clockZDYHIRUP^010

rise and fall times for one periodILQGSRUWclock

clock is specified for this port

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Selection of memory elements type

u selection of particular flip flops or latches styles optional

u for exact specification of memory elementsVHWBUHJLVWHUBW\SHIOLSBIORSFD1S

simple edge-triggered D flip flop

VHWBUHJLVWHUBW\SHODWFKH[DFWLD1P positive edge active D latch

u menu selectionDWWULEXWHV RSWLPL]DWLRQGLUHFWLYHV GHVLJQDWWULEXWHV

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Description of memory elements

u memory elements generated for signals which arenot defined for all possible conditions in conditionalassignments

u the type of memory element generated inferredimplicitly from the VHDL description

flip-flop edge-triggered

latch level sensitive

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Flip-flop register(17,7

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Latch register(17,7< latch_bank,63257A,1std_logic_vector3GRZQWR0

write,1std_logicY287std_logic_vector 3GRZQWR0

(1latch_bank

$5&+,7(&785(arch2)latch_bank,6%(*,1352&(66Awrite%(*,1,)write 17+(1 Y A(1,)(1352&(66(1arch

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Combinational and sequential logicu most designs contain both combinational and

sequential logic

/,%5$5

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Synthesized design

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Design initialization

u all registers in a design are set to an initial valueu registers can be initialized using

synchronous reset executed on the next clock edge activated by positive or negative clock edge

asynchronous reset executed independently on the clock

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Synchronous reset

352&(66clockresetA%(*,1

,)clock(9(17$1clock 17+(1,)reset 17+(1Q 0

(/6(Q A

(1,)(1,)(1352&(66

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Asynchronous reset

352&(66clockresetA%(*,1,)reset 17+(1 Q 0(/6,)clock(9(17$1clock 17+(1 Q A(1,)

(1352&(66

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Example sequential logic: counter

u synchronous 8-bit counteru asynchronous resetu selection between counting up and down

selected with signal GLU increments if GLU 1

decrements if GLU 0

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VHDL implementation of the counter(17,7

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Elaboration generatesstructural representation

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Optimized synthesis result

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Example sequential logic:serial-to-parallel converter

u serial-to-parallel converteru synchronous 8 bit conversionu asynchronous resetu accepts serial data streamu packs 8 bits in a byteu outputs byte

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Serial/parallel sourceShift352&(66clockreset%(*,1,)reset 1 7+(1reg "00000000"(/6,)clock(9(17$1clock 1 7+(1reg data_iregdownto(1,)352&(66

Counter352&(66clockreset%(*,1,)reset 17+(1count "000"(/6,)clock(9(17$1clock 17+(1count count1(1,)(1352&(66data_o reg:+(1count "111"(/6("00000000"(1arch

(17,7

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Implementation

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Description of finite state machines

u finite state machines important in hardware design for design of control units

u finite state machines = FSMu two types of FSM

Mealy FSM Moore FSM

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Mealy finite state machines

u outputs of the Mealy FSM depend on the currentstate of the machine and on the current inputs

Inputs InputLogic

State Register

OutputLogic

Present state

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Moore finite state machines

u outputs of the Moore FSM depend only on thecurrent state of the machine

Inputs InputLogic

State Register

OutputLogic

Present state

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VHDL description styles of FSM

u FSM description style depends on number of state signals

one signal for modeling both current and next state of theFSM

two signals used for describing current and next state of theFSM

number of processes in the architecture how combinational and sequential logic are

allocated to processes

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Explicit description(17,7

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Resulting design

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$5&+,7(&785(separate2) fsm ,67

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Resulting design

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Separated sequential and combinational logic$5&+,7(&785(reg2)fsm,67

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Separated in three processes$5&+,7(&785(three2)fsm,67

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Resource Sharing


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Resource sharing

u single functional unit used several times fromdifferent design parts

for example, for two + in source codesometimes can be used the same adder

u resource sharing (RS) tries to allocate differentoperators to same functional unit

u the quality of resource sharing depends on thesynthesis tool

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How resource sharing works

u in most synthesis tools resource sharing depends onresults of static analysis

resource sharing generated only for staticallydisjoint operations

for example, in different branches of IF and CASEstatements

u resource sharing introduces multiplexors tomultiplex various inputs to the shared unit

multiplexor introduces additional delay

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Resource sharing example: accumulator

u implement 8-bit accumulatoru synchronous resetu adds or subtracts input

operations + or - selected with signal FWO add if FWO

subtract if FWO

u both operations should use the same add/subtractunit

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RS example: VHDL description(17,7

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RS example: optimized designu RS introduced in optimization

resource report lists shared units and operationsmapped to them

only one unitfor add and subtract

operations

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Resource sharing in Synopsys

u options no RS automatic RS user controlled RS

u automatic RS used by default only if design timing allows introduction of

additional delay for multiplexor RS problem for time constrained designs

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Time constrained designs

u automatic RS can be problem for timing criticaldesigns

RS introduces multiplexor for differentresource inputs design slowed down

even a minimal timing violation eliminates RS possible result resource explosion solution: user controlled RS

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User controlled resource sharing

u synthesis tool sometimes generates no RS does not recognize that a functional unit can be

sharedu user can still control synthesis tool to introduce RS

introduced by describing it in VHDL programsu user defines resources which are to be shared

using VHDL construct DWWULEXWH VHDL description has to be modified

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Automatic RS example: VHDL source

/,%5$5

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No RS example: VHDL source

/,%5$5

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User controlled RS example: VHDL source/,%5$5

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What resources can be shared

u not all resources can be sharedu RS possible for units with similar functionalityu typically

+ and + + and - - and - > and > > and

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Selecting resource implementation

u resource implementation can be selected indirectly by setting constraints

e.g. for fast design, FOD model is chosen e.g. for small design, USO model is included

directly modifying the VHDL description to select the desired

implementation forbidding the optimizer to use slow implementations, e.g.

using command to forbid ripple carry modelVHWBGRQWBXVHVWDQGDUGVOGEUSO

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(

Exercise 3Design reuse and integration


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Design reuse and integration

u design a digital thermometeru thermometer can display temperature in C or Fu advantageous over analog thermometer

selection F/C with switch = 0, output in F, convert input from C to output in F = 1, output in C, no conversion required

A/D IC BCDget_datavalid valid

data data_out

F/C BCD

)&

)&

)&

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Design overview

u conversion formula F = C * 2 + 32

FSMget_data

validvalid

datadata_out

C/F

ALU

Mux

REG.file

ALU command RegAdr

F/C BCD

constants

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(

Explanation of functional units

u design an FSM for controlling designu design reuse use existing designs for

ALU register file

u use ALU from exercise 2 functionality must not be changed

u use register file from DesignWare library use component :BUDPBVBG data sheet for component

in Synopsys online documentation

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Control flow of the thermometeru start A/D converters using signal JHWBGDWDu wait for results from the A/D converter

signal YDOLG data available signal GDWD temperature in C

u convert the temperature from C into F if required, i.e., signal = 0 use register file for storing intermediate results

u send data to BCD display signal GDWDBRXW temperature in F or C signal )&%& display temperature scale

u repeat steps for new temperature input

)&

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VHDL description

u describe FSM as a separate entityu integrate all components of the system using

structural VHDLu VHDL components reference existing designs

ALU register file FSM

u implement required glue logic in the VHDL net list

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u design the control unit for this design as FSM inVHDL

u integrate all components in a single designu simulate the design to validate functionalityu synthesize the designu simulate synthesis results

Table of ContentsVHDL PrimerVHDL SimulationExercise 1VHDL SynthesisSynthesis with SynopsysExercise 2Sequential Logic and FSMResource SharingExercise 3

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Vhdl Synthesis