Vhdl Basics With Examples

7/29/2019 Vhdl Basics With Examples

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INTRODUCTION TO VHDL (WITH SOME

EXAMPLES)

HISTORY OF VHDL

In the mid-1980s the U.S. Department of Defense ( DoD) and the IEEE sponsored the

development of the hardware description language with the goal to develop very high-speed

integrated circuit, which brought result in the form of VHDL. It has become now one of

industrys standard languages used to describe digital systems. The other widely used

hardware description language is Verilog. Both are powerful languages that allow you to

describe and simulate complex digital systems. A third HDL language is ABEL (Advanced

Boolean Equation Language) which was specifically designed for Programmable Logic

Devices (PLD). ABEL is less powerful than the other two languages and is less popular in

industry.

WHATS VHDL

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description

Language. Its a hardware description language that is specifically designed to describe the

organization & function of digital hardware system .In sort ,VHDL is a hardware description

language that can be used to model a digital system .the digital system can be as simple as

logic gate as complex as a complete electronic system.

CAPABILITIES OF VHDL

Implementation of any circuit idea like complete robot design.

Microprocessor of your own configuration.

Direct hardware interaction.

SPECIFIC FEATURES OF VHDL

Portability Each level of abstraction.

Not technology specific.

IEEE & ANSI standardized.

Large projects can be easily designed.


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VHDL DESIGN HIERARCHY

ENTITY DECLARATION

The entity declaration defines the NAME of the entity and lists the input and output ports.

The general form is as follows,

entity NAME_OF_ENTITY is [ generic

generic _declarations);]

port (signal _ names:modetype;signal _ names:mode type;

:

Signal _names:mode type);

end NAME_OF_ENTITY ;

An entity always starts with the keyword entity, followed by its name and the keyword

is. Next are the port declarations using the keywordport. An entity declaration always

ends with the keyword end.

ARCHITECTURE BODY

The architecture body specifies how the circuit operates and how it is implemented. As discussed

earlier, an entity or circuit can be specified in a variety of ways, such as behavioral, structural

(interconnected components), or a combination of the above.

The architecture body looks as follows,

Architecture architecture_name of NAME_OF_ENTITY is

-- Declarations

-- components declarations

-- signal declarations

beginStatements;

end architecture_name;


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EX:> architecture Structural of fulladder iscomponent halfadder_str_us_xorPort ( a: in STD_LOGIC;

b : in STD_LOGIC;

sum : out STD_LOGIC;carry : out STD_LOGIC);

end component; //componentdeclarations

component orgatePort ( a4: in STD_LOGIC;

b4 : in STD_LOGIC;

c4 : out STD_LOGIC);end component;

signal s1,g,h:STD_LOGIC; //signaldeclarations

beginstatements;end Structural;

SIGNALS

Signals connect design entities together and communicate changes in values between

processes.They can be interpreted as wires or busses in an actual

circuit.Signals can be declared in packages , entities , architectures and blocks. The syntax is :

Signal signal_name {signal_name} :type[:=value];

DESIGN DESCRIPTION METHODS

A digital system can be represented at different levels of abstraction [1]. This keeps the

description and design of complex systems manageable. Figure 1 shows different levels of

abstraction.


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Figure 1: Levels of abstraction: Behavioral, Structural and Physical

**The highest level of abstraction is the behavioral level that describes a system

in terms of what it does (or how it behaves) rather than in terms of its components and

interconnection between them. A behavioral description specifies the relationship

between the input and output signals. This could be a Boolean expression or a more

abstract description.

VHDL allows one to describe a digital system at the structural or the behavioral level. The

**behavioral level can be further divided into two kinds of styles: Data flow and

Algorithmic.

*The dataflow representation describes how data moves through the system.This is typically done in terms of data flow between registers (Register Transfer level). The

data flow model makes use of concurrent statements that are executed in parallel as soon

as data arrives at the input.

On the other hand , sequential statements are executed in the sequence that they are specified.

VHDL allows both concurrent and sequential signal assignments that will determine the

manner in which they are executed. Examples of both representations will be given later. as

the Register Transfer or Algorithmic level.

As an example, let us consider a simple circuit that warns car passengers when the door is

open or the seatbelt is not used whenever the car key is inserted in the ignition lock,

At the behavioral level this could be expressed as,

Warning = Ignition_on AND ( Door_open OR Seatbelt_off)

**The structural level, on the other hand, describes a system as a collection of gates and

components that are interconnected to perform a desired function. A structural description

could be compared to a schematic of interconnected logic gates. It is a representation that is

usually closer to the physical realization of a system.

For the example above, the structural representation is shown in Figure 2 below.


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Figure 2: Structural representation of a buzzer circuit.

SEQUENTIAL STATEMENTS

If Statements

The if statement executes a sequence of statements whose sequence depends on one or

more conditions. The syntax is as follows:

ifconditionthen

sequential statements;

[else ifconditionthen

sequential statements ]

[else

sequential statements ]

end if;

EX:>(if statements for xor gate)EX:>(if statements for xor gate)EX:>(if statements for xor gate)EX:>(if statements for xor gate)

if(a='1'and b='0')thenif(a='1'and b='0')thenif(a='1'and b='0')thenif(a='1'and b='0')then

c


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Case statements

The case statement executes one of several sequences of statements, based on the value of a

single expression. The syntax is as follows,

caseexpression iswhenchoices =>

sequential statements

whenchoices =>

sequential statements

-- branches are allowed

[ when others => sequential statements ]

end case;

EX:>case s iscase s iscase s iscase s is //HERE S IS THE INPUT OFCOMBINATION OFTHREE BITS//HERE S IS THE INPUT OFCOMBINATION OFTHREE BITS//HERE S IS THE INPUT OFCOMBINATION OFTHREE BITS//HERE S IS THE INPUT OFCOMBINATION OFTHREE BITS

when "000"=>when "000"=>when "000"=>when "000"=>

d

d

d

d

d

d

d

d //THIS STATEMENT IS MUST.//THIS STATEMENT IS MUST.//THIS STATEMENT IS MUST.//THIS STATEMENT IS MUST.null;null;null;null;

end case;end case;end case;end case;


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Dataflow Modeling

Concurrent Statements

Behavioral modeling can be done withsequentialstatements using the process construct or

with concurrent statements. The first method was described in the previous section and isuseful to describe complex digital systems.

In this section, we will useconcurrent statements to describe behavior. This method is

usually called dataflow modeling. The dataflow modeling describes a circuit in terms of its

function and theflow of data through the circuit. This is different from the structural

modeling that describes a circuit in terms of the interconnection of components.

Concurrent signal assignments are event triggered and executed as soon as an event on one of

the signals occurs. In the remainder of the section we will describe several concurrent

constructs for use in dataflow modeling.

Simple Concurrent signal assignments.(DATA FLOW MODELLING)

In this section we will review the different types of concurrent signal assignments.

A simple concurrent signal assignment is given in the following examples,

Sum


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Structural Modeling

A structural way of modeling describes a circuit in terms of components and its

interconnection. Each component is supposed to be defined earlier (e.g. in package) and can

be described as structural, a behavioral or dataflow model. At the lowest hierarchy eachcomponent is described as a behavioral model, using the basic logic operators defined in

VHDL. In general structural modeling is very good to describe complex digital systems,

though a set of components in a hierarchical fashion.

A structural description can best be compared to a schematic block diagram that can be

described by the components and the interconnections. VHDL provides a formal way to do

this by

Declare a list of components being used

Declare signals which define the nets that interconnect components

Label multiple instances of the same component so that each instance is

uniquely defined.

The components and signals are declared within the architecture body,

architecture architecture_name of NAME_OF_ENTITY is

-- Declarations

component declarationssignal declarations

begin

-- Statements

component instantiation and connections;

end architecture_name;

Component declaration

Before components can be instantiated they need to be declared in the architecture

declaration section or in the package declaration. The component declaration consists of the

component name and the interface (ports). The syntax is as follows:

component component_name

port (port_signal_names:modetype;

port_signal_names:mode type;

:

port_signal_names:mode type);

end component ; //here not write end component_name

in the last statement

The component name refers to either the name of an entity defined in a library or an entity

explicitly defined in the VHDL file (see example of the four bit adder).


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The list of interface ports gives the name, mode and type of each port, similarly as is done in

the entity declaration.

A few examples of component declaration follow:

component OR2port (in1, in2: in std_logic;

out1: out std_logic);

endcomponent;

component FULLADDER

port(a, b, c: in std_logic;

sum, carry: out std_logic);

end component;

As mentioned earlier, the component declaration has to be done either in the architecture

body or in the package declaration. Generally for simplicity we used to defined component

declaration in the architecture body.

CONCLUSION

VHDL has been at the heart of electronic design productivity since initial

ratification by the IEEE in 1987. It can be said that VHDL fuelled modern

synthesis technology and enabled the development of ASIC semiconductor

companies. From the beginning VHDL has been a powerful language with

numerous language constructs that are capable of describing very complex

behavior, this leadership of VHDL community has assured open and

internationally accredited for the electronic design engg. community. The legacy

of team work continue to benefit the design community today as the benchmark

by which one measures openness.


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FUTURE PROSPECTS

Each device microprocessor controlled is designed by VHDL.

Future: an electronics world.

International endorsement: a positive response.


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SOME EXAMPLES

BEHAVIORAL MODELLING

1. XOR GATE

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity xorgate isPort ( a : in STD_LOGIC;

b : in STD_LOGIC;

c : out STD_LOGIC);end xorgate;architecture xora of xorgate isbeginprocess(a,b)beginif(a='1'and b='0')thenc


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2.FULL SUBSTRACTOR

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity fullsubst is

Port ( a : in STD_LOGIC;b : in STD_LOGIC;bi : in STD_LOGIC;d : out STD_LOGIC;bo : out STD_LOGIC);

end fullsubst;architecture Behavioral of fullsubst isbeginprocess(a,b,bi)beginif((a='0' and b='0' and bi='1')or(a='0' and b='1' and bi='0') or (a='1'and b='1' and bi='1'))thend


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bo


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use IEEE.STD_LOGIC_UNSIGNED.ALL;entity compar is

Port ( a : in STD_LOGIC_VECTOR (15 downto 0);b : in STD_LOGIC_VECTOR (15 downto 0);

s : in STD_LOGIC_VECTOR (3 downto 0);y : out STD_LOGIC);end compar;architecture Behavioral of compar isbeginprocess(a,b,s)begincase s iswhen "0000"=>

if(a/=b)then--unexpected eqy


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when "0101"=>if(a


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4.DEMULTIPLEXER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity decoder is

Port ( s : in STD_LOGIC_VECTOR (2 downto 0);

d : out STD_LOGIC_VECTOR (7 downto 0));end decoder;architecture Behavioral of decoder isbeginprocess(s)begincase s iswhen "000"=>dd


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when "010"=>dddddd

null;end case;end process;end Behavioral;

5.EVEN PARITY GENERATOR

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;


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use IEEE.STD_LOGIC_UNSIGNED.ALL;entity evenpargen is

Port ( a : in STD_LOGIC;b : in STD_LOGIC;

c : in STD_LOGIC;d : in STD_LOGIC;p : out STD_LOGIC);

end evenpargen;architecture Behavioral of evenpargen isbeginprocess(a,b,c,d)beginif((a='0' and b='0' and c='0' and d='1') or(a='0' and b='0' and c='1'

and d='0')or (a='0' and b='1' and c='0' and d='0')or (a='0' and b='1'and c='1' and d='1') or (a='1' and b='0' and c='0' and d='0')or (a='1'and b='0' and c='1' and d='1')or (a='1' and b='1' and c='0' andd='1')or (a='1' and b='1' and c='1' and d='0'))thenp


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DATAFLOW MODELLING

1.BINARY TO GRAY CODE CONVERTOR

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity bintogray is

Port ( b3 : in STD_LOGIC;b2 : in STD_LOGIC;b1 : in STD_LOGIC;b0 : in STD_LOGIC;g3 : out STD_LOGIC;g2 : out STD_LOGIC;g1 : out STD_LOGIC;g0 : out STD_LOGIC);

end bintogray;architecture dataflow of bintogray isbeging3


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2.DECIMAL TO BINARY ENCODER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dectobcd_encoder is

Port ( d0 : in STD_LOGIC;d1 : in STD_LOGIC;d2 : in STD_LOGIC;d3 : in STD_LOGIC;d4 : in STD_LOGIC;

d5 : in STD_LOGIC;d6 : in STD_LOGIC;d7 : in STD_LOGIC;d8 : in STD_LOGIC;d9 : in STD_LOGIC;a3 : out STD_LOGIC;a2 : out STD_LOGIC;a1 : out STD_LOGIC;a0 : out STD_LOGIC);

end dectobcd_encoder;architecture dataflow of dectobcd_encoder is


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begina3


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d0 : out STD_LOGIC;d1 : out STD_LOGIC;d2 : out STD_LOGIC;d3 : out STD_LOGIC;

d4 : out STD_LOGIC;d5 : out STD_LOGIC;d6 : out STD_LOGIC;d7 : out STD_LOGIC;d8 : out STD_LOGIC;d9 : out STD_LOGIC);

end bcdtodecimal;architecture decoder of bcdtodecimal isbegin

d0


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4.MULTIPLEXER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux8_1 is

Port ( i0 : in STD_LOGIC;

i1 : in STD_LOGIC;i2 : in STD_LOGIC;i3 : in STD_LOGIC;i4 : in STD_LOGIC;i5 : in STD_LOGIC;i6 : in STD_LOGIC;i7 : in STD_LOGIC;s2 : in STD_LOGIC;s1 : in STD_LOGIC;

s0 : in STD_LOGIC;y : out STD_LOGIC);


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end mux8_1;architecture dataflow of mux8_1 isbeginy


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Port ( d1 : in STD_LOGIC;d2 : in STD_LOGIC;d3 : in STD_LOGIC;d4 : in STD_LOGIC;

d5 : in STD_LOGIC;d6 : in STD_LOGIC;d7 : in STD_LOGIC;d8 : in STD_LOGIC;d9 : in STD_LOGIC;a3 : out STD_LOGIC;a2 : out STD_LOGIC;a1 : out STD_LOGIC;a0 : out STD_LOGIC);

end parityen;architecture dataflow of parityen isbegina0


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STRUCTURAL MODELLING1.FULL ADDER


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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fulladder isPort ( k : in STD_LOGIC;

l : in STD_LOGIC;cin : in STD_LOGIC;sout : out STD_LOGIC;cout : out STD_LOGIC);

end fulladder;architecture Structural of fulladder iscomponent halfadder_str_us_xor

Port ( a: in STD_LOGIC;b : in STD_LOGIC;

sum : out STD_LOGIC;carry : out STD_LOGIC);

end component;component orgatePort ( a4: in STD_LOGIC;

b4 : in STD_LOGIC;

c4 : out STD_LOGIC);end component;signal s1,g,h:STD_LOGIC;beginL0:halfadder_str_us_xor port map(k,l,s1,g);L1:halfadder_str_us_xor port map(s1,cin,sout,h);L2:orgate port map(g,h,cout);end Structural;

PROGRAM FOR COMPONENT halfadder

library IEEE;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity halfadder_str_us_xor is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;sum : out STD_LOGIC;


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carry : out STD_LOGIC);end halfadder_str_us_xor;architecture Structural of halfadder_str_us_xor iscomponent xorgate

Port ( a1 : in STD_LOGIC;b1 : in STD_LOGIC;c1 : out STD_LOGIC);

end component;component andgatePort ( a2 : in STD_LOGIC;

b2 : in STD_LOGIC;c2 : out STD_LOGIC);

end component;beginL0:xorgate port map(a,b,sum);L1:andgate port map(a,b,carry);end Structural;

PROGRAM FOR COMPONENTxorgatelibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xorgate is


end xorgate;architecture dataflow of xorgate isbeginc1


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end andgate;architecture dataflow of andgate isbeginc2


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component andgatePort ( a : in STD_LOGIC;

b : in STD_LOGIC;c: out STD_LOGIC);

end component;component orgatePort ( a1 : in STD_LOGIC;

b1 : in STD_LOGIC;c1: out STD_LOGIC);

end component;component notgatePort ( a2 : in STD_LOGIC;

c2: out STD_LOGIC);

end component;signal s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13: STD_LOGIC;beginl0:notgate port map(rl,s1);l1:andgate port map(din,rl,s2);l2:andgate port map(s1,q2,s3);l3:orgate port map(s2,s3,s4);l4:dff port map(clk,s4,q1);l5:andgate port map(rl,q1,s5);l6:andgate port map(s1,q3,s6);

l7:orgate port map(s5,s6,s7);l8:dff port map(clk,s7,q2);l9:andgate port map(rl,q2,s8);l10:andgate port map(s1,q4,s9);l11:orgate port map(s8,s9,s10);l12:dff port map(clk,s10,q3);l13:andgate port map(rl,q3,s11);l14:andgate port map(s1,din,s12);l15:orgate port map(s11,s12,s13);

l16:dff port map(clk,s13,q4);end Structural;

PROGRAM FOR COMPONENTdff

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff is


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Port ( clk1 : in STD_LOGIC;d : in STD_LOGIC;q : buffer STD_LOGIC);

end dff;

architecture Behavioral of dff isbeginprocess(clk1)begin--q


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end orgate;

architecture Dataflow of orgate isbeginc1


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#EXERCISE

(FULLADDER,HALF ADDER,HALF SUBSTRACTOR,FULLADDER,HALF ADDER,HALF SUBSTRACTOR,FULLADDER,HALF ADDER,HALF SUBSTRACTOR,FULLADDER,HALF ADDER,HALF SUBSTRACTOR,MULTIPLEXER ,ALLMULTIPLEXER ,ALLMULTIPLEXER ,ALLMULTIPLEXER ,ALL

GATES,COUNTER,COMPLEX DIGITALGATES,COUNTER,COMPLEX DIGITALGATES,COUNTER,COMPLEX DIGITALGATES,COUNTER,COMPLEX DIGITAL CKTS,FLIPCKTS,FLIPCKTS,FLIPCKTS,FLIP----FLOP,PARITYFLOP,PARITYFLOP,PARITYFLOP,PARITYGENERATOR,PARITY CHECKER ,DEMULTIPLEXERGENERATOR,PARITY CHECKER ,DEMULTIPLEXERGENERATOR,PARITY CHECKER ,DEMULTIPLEXERGENERATOR,PARITY CHECKER ,DEMULTIPLEXER

,DECODER,ENCODER,KMAP PROBLEMS,BINARY TO GRAY,DECODER,ENCODER,KMAP PROBLEMS,BINARY TO GRAY,DECODER,ENCODER,KMAP PROBLEMS,BINARY TO GRAY,DECODER,ENCODER,KMAP PROBLEMS,BINARY TO GRAY

CONVERSION,REGISTER,COMPARATOR,ALU(ARITHEMATIC AND LOGICALCONVERSION,REGISTER,COMPARATOR,ALU(ARITHEMATIC AND LOGICALCONVERSION,REGISTER,COMPARATOR,ALU(ARITHEMATIC AND LOGICALCONVERSION,REGISTER,COMPARATOR,ALU(ARITHEMATIC AND LOGICAL

UNIT)UNIT)UNIT)UNIT))


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Vhdl Basics With Examples