Jim Duckworth, WPI Verilog for Advanced Testing - Module 81

Verilog for Advanced Testing

Module 8

Simulating with DCM

Jim Duckworth, WPI Verilog for Testing and Modeling - Module 82

Simulation waveform

• Add clk_20M and cntr to waveform

• Restart, run 1us

Jim Duckworth, WPI Verilog for Testing and Modeling - Module 83

Test Bench – System Tasks

• Verilog provides system tasks ($keyword) to write out information, monitor, and end simulation

• $display – display strings, expression or values to standard output – adds newline at end – $write is similar but no newline

• $display(“This is an example string”);

• $display(“The value is %h at time %t”, q, $time);

– Format specifier %d, %b, %h, %o, %t

• $monitor – same as display but displays when any of the values change, very useful!

• $monitor($time, “: R0 = %b, R1 = %b ”, r0, r1);

• $stop – suspend simulation, put in interactive mode

• $finish – stop simulation altogether

Jim Duckworth, WPI Verilog for Advanced Testing - Module 85

Additional Verilog System Tasks

• @ (posedge clk) – event control, wait for rising edge of clk

• wait (state == ENTER && ready == 1’b1) – wait for

specific condition

• #123 – wait for 123 ref time units (123 ns)

• $time and $realtime

• $fopen and $fclose

• Integer log_file = $fopen(“my_log”)

• $readmemb and $readmemh

Jim Duckworth, WPI Verilog for Advanced Testing - Module 86

Test Bench Example – Shift Register

Jim Duckworth, WPI Verilog for Advanced Testing - Module 87

Jim Duckworth, WPI Verilog for Advanced Testing - Module 88

Jim Duckworth, WPI Verilog for Advanced Testing - Module 89

(

Jim Duckworth, WPI Verilog for Advanced Testing - Module 810

Jim Duckworth, WPI Verilog for Advanced Testing - Module 811

Verilog task

• Like a procedure (pass in inputs, carry out operation, and

generate outputs)

– Must be called with a statement

Jim Duckworth, WPI Verilog for Advanced Testing - Module 812

Task example and writing to file

Open file for writing

Call task “CHECK_y”

Jim Duckworth, WPI Verilog for Advanced Testing - Module 813

Task example (continued)

Task declaration

Jim Duckworth, WPI Verilog for Advanced Testing - Module 814

Simulation Results

Jim Duckworth, WPI Verilog for Advanced Testing - Module 815

VHDL for Synthesis

Jim Duckworth, WPI Verilog for Advanced Testing - Module 816

Decoder Test Bench in Verilog with Files

Jim Duckworth, WPI Verilog for Advanced Testing - Module 817

test_vec.txt File

• Format is

– 3 bits for SEL input

– 8 bits for expected output

00000000001

00100000010

01000000100

01100001000

10000010000

10100110000

11001000000

11110000000

Jim Duckworth, WPI Verilog for Advanced Testing - Module 818

Opening file in Verilog

Jim Duckworth, WPI Verilog for Advanced Testing - Module 819

Jim Duckworth, WPI Verilog for Advanced Testing - Module 820

Waveform Generated

Jim Duckworth, WPI Verilog for Advanced Testing - Module 821

Console (and results file)