Verilog Design Entry, Synthesis, and Behavioral Simulationaboutme.samexent.com/classes/fall08/ee4301/labs/lab01e.pdf · Verilog Design Entry, Synthesis, and Behavioral Simulation-----PURPOSE

Lab #1 - EE4301 - ECE - UMN Verilog Design Entry, Synthesis, and Behavioral Simulation

Verilog Design Entry, Synthesis, and Behavioral Simulation

-------------------------------------------------------------PURPOSE - This lab will present a brief overview of a typical design flow and then will start to walkyou through some typical tasks and familiarize you with the user interface of Project Navigator of XilinxIntegrated Software Environment (ISE) 8.2i. You will design a very simple circuit during the DesignEntry, Synthesis, and Functional Simulation. You will also learn how to use ModelSimfor behavioral simulation of Verilog designs.

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1. Introduction

Fig.1 presents the basic steps we have to perform when we design circuits we want to implement onField Programmable Gate Arrays (FPGAs) or Complex Logic Devices (CPLDs).

Figure 1 Typical design flow

The ISE suite has been designed to effectively assist in development of FPGA projects. The finalresult of such projects is a bit stream file that can be downloaded into a re-programmable FPGAdevice.

The following steps represent a typical design flow:I. Creating the initial description of the design -- this operation is called Design Entry. The ISE

suite supports many design flows. One of them is the Xilinx Synthesis Technology - XSTVerilog. During this step we will usually use Verilog to completely describe the functionalityof our designs.

II. Design Synthesis


III. Functional simulation of the design. The design is simulated to verify the correctness of theHDL description. In case of errors (our description does not perform as intended) we go backto the Design Entry step and make the necessary corrections.

IV. Editing design constraints and controls.V. Optimizing the design for certain FPGA device.VI. Design Implementation - basically means Placement & Routing of the design.VII. Timing simulation of the design, based on the post-layout timing netlist. The timing netlist

contains timing information extracted from the files generated during the Place & Routeprocessing. Simulation based on such netlists describes the circuit behavior far more accuratelythan functional simulation.

For performing all the above steps we will use Xilinx Integrated Software Environment (ISE) 8.2i.ISE starts in the Project Navigator. From the Project Navigator you can organize and track your projects.You can work with editors, and simulators to define your project to meet your particularspecifications. A series of implementation tools are available to compile and redefine aspects of yourdesign. When your design meets specifications, you can download the final design to your device.

2. To organize your work, ISE groups all related files into separate logic units called projects. Aproject is a collection of design files stored in a separate subfolder, called project working directory,which is treated as a separate logic unit and includes among others:-- source files-- output and intermediate files (netlists, report and log files, bit stream files)-- configuration files

Your design is represented in various ways. Those representations are called sources. A source isany element in the design such as an HDL file, schematic, or simulation file. Sources are displayed in theSources in Project window. Sources include not only the description of the circuits, as represented byschematics and hardware description languages, but also include simulation testfixtures and documentation of the design. All these pieces are part of the whole design.

The design description (logic) for a project is contained within the following types of sources• Schematics• HDL files (VHDL, Verilog, or HDL-ABEL)• EDIF

One source file in a project is the top-level source for the design. The top-level source defines theinputs and outputs that will be mapped into the device, and references the logic descriptions contained inlower-level sources. The referencing of another source is called "instantiation." Lower-level sources can also instantiate sources to build as many levels of logic as necessary to describeyour design.

During this lab you will describe a very simple circuit using Verilog. You will learn about thislanguage during the class. Further information about Verilog can be found in the references at the end ofthis lab as well as on the class web page. The Appendix contains information aboutelementary Verilog constructs.


NOTE: To organize your work during the laboratories of this class, create a directory called labs inyour account and then create directories labi, i=1…11, (one separate folder for each lab). Duringeach lab save your projects and any file to the corresponding directory.

3. Start ISE by clicking on the Project Navigator icon on your desktop or by:Start->Programs->Xilinx ISE 8.2i->Project Navigator.

Figure 2 Project Navigator window

The Project Navigator window, shown in Figure 2, should pop up.NOTE: Take a little time and get familiar with the Project Navigator window and its menus.

4. Select File->New Project.The New Project dialog window should pop up.5. Type in the project name: adder_verilog.6. Select as location YourAccount\lab1\adder_verilog.7. Select HDL Top-Level Source Type, Click Next.8. Select Spartan3E as Device Family.9. Select XC3S100E as Device.10. Select VQ100 as the package.


11. Select -4 as the speed grade.12. Select XST (VHDL/Verilog) as Synthesis Tool.13. Select Modelsim-XE Verilog as Simulator, Click Next.14. Click Next. 15.Click Next.16. Click Finish.17. In what follows you will describe your adder as an all HDL-design. Basically, the Design Entrystep consists of adding Verilog files to the HDL Flow project.

18. Entering the design18.1. Use Notepad text editor to create the following two files, which shall be saved in the

adder_verilog directory.

File 1: Name it full_adder.v and type in the following Verilog code:

// Uncomment the following lines to use the declarations that are// provided for instantiating Xilinx primitive components.//library UNISIM;//use UNISIM.VComponents.all;

module full_adder (sum, co, i1, i2, ci );

output sum;output co;input i1;input i2;input ci;

wire sum;wire co;

assign {sum}=((i1 ^ i2) ^ ci);

assign {co}=(((i1 & i2) | (i1 & ci)) | (i2 & ci));

endmodule

File 2: Name it fourbit_adder.v and type in the following Verilog code:

// component declarationmodule fourbit_adder ( y, a, b, ci,);

output [3:0] y ;input [3:0] a ;input [3:0] b ;input ci;

wire carry0;


wire carry1;wire carry2;wire [3:0] y;

full_adder bit0( y[0], carry0, a[0], b[0], ci );

full_adder bit1( y[1], carry1, a[1], b[1], carry0 );

full_adder bit2( y[2], carry2, a[2], b[2], carry1 );

full_adder bit3( y[3], co, a[3], b[3], carry2 );

endmodule

18.2. Add the above source files to your project by selecting:Project->Add SourceFrom the window that pops up, select the two files and click Open. Select default settings.

18.3. The alternative to using Notepad to type in Verilog source files is the use of the HDLEditor. As a tool inside ISE, the HDL Editor is a text editor designed for editing HDL sourcefiles. In addition to regular editing features, the editor provides syntax coloring. The syntaxcoloring feature supports three languages: Verilog, ABEL and VHDL. The HDL Editor willoperate as a standard text editor as well.

Double-click on the name of any of the above two files to open it with the HDL Editor.

NOTE: Take a little time to get familiar with HDL Editor. Select Help->ISE Help ContentsThen, click on HDL Editor icon.

18.4. Remove full_adder.v from your project by selecting the file, right-click, and Remove.Recreate the full_adder.v file by selecting: Project->New Source

Select Verilog Module. Name the file appropriately and follow the next step, which is self-explanatory. You should end up with a Verilog skeleton file open in the HDL Editor. Type inthe rest of the full_adder.v file as described at Step 18.1 above.

From now you should use this way of creating and adding Verilog files to your projects.

So far you wrote the Verilog description of a simple four-bit adder (adding integer numbers andwith no overflow signaling) which performs a simple addition a+b=y. We first built afull_adder entity. Then we used it (four instances) to build the fourbit_adder entity.

19. Analyzing Design File SyntaxTo check your source files for syntax errors select file in Module View panel of Project Navigatorwindow, right click on Synthesize XST-> Check Syntax inside Process View panel of ProjectNavigator window, select Run.


20. Performing HDL Behavioral SimulationWhile writing Verilog descriptions you usually verify their correctness (to see that they behave

in the desired fashion) via simulation. You will use ModelSIM simulator (of ModelTechnology).

20.1. Start the ModelSim simulator by clicking on the icon on your desktop or by:Start->Programs->ModelSim XE III 6.0 d ->ModelSim and choose Run ModelSim.

20.2. As in the case of Project Navigator environment, ModelSim works with projects too. So, inorder to simulate a design you will have to create first a project. A project is a collection entityfor an HDL design under specification or test. It has a root directory, a work library and sessionstate which is stored in a .mpf file located in the project's root directory. Aproject may also consist of:

-- HDL source files-- subdirectories-- Local libraries-- References to global librariesTo create a new project select Create a Project in the dialog window that popped up.Clicking the Create a Project button opens the Create a New Project dialog box and a project

creation wizard. The wizard guides you through each step of creating a new project, helping youcreate and load the project and providing the option of entering Verilog or Verilogdescriptions.

NOTE: The Create a New Project dialog box can also be accessed by selectingFile->New->New Project from the ModelSim Main window.

20.3. Select to create a new project from scratch.20.4. Specify the New Project's Name, as fourbit_adder.20.5. Specify the New Project's Home.20.6. Click OK.

20.7. Add the two Verilog source files to your project, by selecting:Project->Add Existing File to ProjectBrowse for your files and add them as Copy to project directory.

NOTE: Take a little time and get familiar with the menu options of the main window ofModelSim.

20.8. If you want to edit any of your files double-click on them inside the main window ofModelSim.

20.9. Your next step is to compile the components of your project into its work library.Select Compile ->Compile All

If the compilation is not successful correct any errors (errors declared by ModelSim may nothave been declared as errors inside ISE!), which you might have inside your source files.


20.10. Once compilation is finished, click the Library tab and you will see the two filescompiled.

Now let's Simulate the design unit. Select the Simulate button from the toolbar or selectSimluate −> Start Simulation from the menu. It lets you select the library and top-leveldesign unit to simulate. You can also select the resolution limit for this simulation. Bydefault, the following will appear for this simulation run:

• Simulator Resolution: default (the default is 1 ps)• Design Unit: work.fourbit_adder

Select the entity fourbit_adder and Click OK ( Accepts Defaults for other tabs ).

20.11. Next, select View-> Debug Windows -> All Windows from the Main window menu toopen all ModelSim windows. (Optional)NOTE: Take a little time and get familiar with each window opened in the ModelSim.

20.12. From the Sim window menu, select Add->List->Selected Instance. This commanddisplays the top-level signals in the List window.

20.13. Next, add top-level signals to the Wave window by selecting Add->Wave-> SelectedInstance from the Sim window menu.

20.14. Before running the simulation you have to apply stimulus at the input ports of yourcircuit. Create with a text editor a file with the following content:

force a 0000 0, 0001 10, 0010 20, 0011 30force b 0000 0, 0010 10, 0010 20, 0010 30force ci 0 0, 1 10

and save it as forcefile.txt under the directory of your project.

20.15. Type in the main simulation window:do forcefile.txtrun 60

20.16. Next examine the Wave window. Right Click to Zoom In. Click in the Wave window tomove a draggable cursor into the display. The cursor controls the signal values beingdisplayed. Convince yourself that your design performs as desired.

20.17. To exit the simulation, select File -> Quit from the Menu.

NOTE: Take a few minutes and play with ModelSim windows. Read Help->Documentation, selectTutorial and learn how to simulate your design without creating the forcefile.txt.

21. Synthesizing the DesignAfter the design files have been successfully analyzed, the next step is to translate the design intogates and optimize it for the target architecture. These steps are performed by running the Synthesisphase. But before doing that you will edit your pin assignments as follows.


Locking in pinsAfter all of the Verilog design files are added and correctly analyzed, you need to specify the XC3S100Epin numbers that you wish to use. To specify the pin numbers you want to use you haveto add and edit the User Constraint File (UCF) for the current project.

Select Project->New Source and select Implementation Constraints File. Name it fourbit_adder.ucfand click ok. Associate this implementation constraint file with fourbit_adder in the next dialogthat pops up. We will add our pin constraints to this file.

Select fourbit_adder.v file in the source window and double click on User Constraints->EditConstraints (Text).The fourbit_adder.ucf is opened and you can modify it according to your needs. Edit this file bytyping in, at the end of it, the following lines:

#################################################### This lines for locking pins only...# DIP SWITCH CONNECTIONS# Any line starting with "#" is a comment line!# P7, P8, P9, P6 correspond to DIPSW<0, 1, 2, 3> on BasysE boardNET 'a<0>' LOC = 'P38';NET 'a<1>' LOC = 'P36';NET 'a<2>' LOC = 'P29';NET 'a<3>' LOC = 'P24';# P77, P66, P70, P69 correspond to DIPSW<4, 5, 6, 7> on BasysE boardNET 'b<0>' LOC = 'P18';NET 'b<1>' LOC = 'P12';NET 'b<2>' LOC = 'P10';NET 'b<3>' LOC = 'P6';# INDIVIDUAL LED CONNECTIONS (ACTIVE-LOW)# You will see that in lab4NET 'y<0>' LOC = 'P15';NET 'y<1>' LOC = 'P14';NET 'y<2>' LOC = 'P8';NET 'y<3>' LOC = 'P7';# Push Button on basysE boardNET 'ci' LOC = 'P69';# Led 7 on the basysE boardNET 'co' LOC = 'P2';###################################################

NOTE: You have to use the "<" and ">" brackets. Now save the file fourbit_adder.ucf and exit theediting program. The reason you choose the pin assignments above will become clearer during thefourth lab!

What you did above is one way of locking pins. You can set even more synthesis constraints byusing the Constraints Editor. To start the Constraints Editor select:Double click on the file fourbit_adder.ucf in the source window.


NOTE: Take a little time to get familiar with the Constraints Editor. Browse all its panels and try tofigure out how you could have done the pins locking using it. Also read the Help documentation.

After you are done with setting constraints for your design, you can run the Synthesis. Before yousynthesize your design, you can set a variety of options for Synthesize - XST. Synthesize - XST is •Xilinx tool that synthesizes HDL designs. For detailed information about Synthesize - XST, referto the Synthesize - XST User Guide.To set Synthesize - XST options:

• Select your top-level design in the Source window of Project Navigator.• To set the options right-click on Synthesize in the Process window of Project Navigator, or

select Synthesize in the Process window of Project Navigator.• Select Properties to display the Synthesis Options in the Process Properties dialog box.• Set the desired Synthesis, HDL, and Xilinx Specific options.•

By default, Advanced properties are not shown in the Process Properties dialog box. To view theAdvanced properties, from the Edit drop down menu, select Preferences. For a complete description ofthese options, refer to Synthesize - XST User Guide. Take a look at but leave the Synthesize -XST options as they are.

Run the synthesis of your top-level design: select Synthesize - XST, right click, and Run, insideProcess View panel of Project Navigator. Browse any output files that may be created by thesynthesis process. Especially go through the Synthesis Report and by double clicking on:Synthesize - XST -> View Synthesis Report. See how the high level logic is synthesized intogeneric and FPGA specific constructs (ex. LUTs). Also, note the number of IO buffers used.

Today you will stop here.Close the Project Navigator. In the next laboratory you will continue your design with theimplementation step.

NOTE: ISE is a quite big software package with many tools and features. It is not possible to covereverything about it within the labs. However, the labs will cover the basics. That is why it is highlyrecommended to go through Help-> Software Manuals and Help-> Tutorials -> Tutorials on Webduring your off-labs time. You will find plenty of extra information!

----------------------------------------------------------------------------SUMMARY -- This laboratory wanted to teach you how to perform Design Entry (using the HDL Editortool), Behavioral Simulation (using ModelSim simulator of Model Technology), andSynthesis using ISE 8.2i of Xilinx.

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REFERENCES[1] In Project Navigator select: Help-> Tutorial -> Tutorials on Web.[2] Verilog Help.a) Text bookb) Web sites indicated on class' web page.c) Appendix (lab #1) for a quick Verilog template reference.


A p p en d ix

Verilog template reference:

This is just an introductory level tutorial to the Verilog language. The reader is encouraged togo through the following Verilog tutorials to understand the language better:

1. Module:

A module is the basic building block in Verilog. It is defined as follows:module <module_name> (<portlist>);

.

. // module components

.endmodule

The <module_name> is the type of this module. The <portlist> is the list of connections, or ports,which allows data to flow into and out of modules of this type.

Verilog models are made up of modules. Modules, in turn, are made of different types ofcomponents. These include

•••••••

2. Ports:

ParametersNetsRegistersPrimitives and InstancesContinuous AssignmentsProcedural BlocksTask/Function definitions

Ports are Verilog structures that pass data between two or more modules. Thus, ports can be thoughtof as wires connecting modules. The connections provided by ports can be either input, output, or bi-directional (inout).


Module instantiations also contain port lists. This is the means of connecting signals in the parentmodule with signals in the child module.

3. Nets:

Nets are the things that connect model components together. They are usually thought of as wires in• circuit. Nets are declared in statements like this:

net type [range] [delay3] list of net identifiers ;

Example:

wire w1, w2;tri [31:0] bus32;wire wire_number_5 = wire_number_2 & wire_number_3;

4. Registers:

Registers are storage elements. Values are stored in registers in procedural assignment statements.Registers can be used as the source for a primitive or module instance (i.e. registers can beconnected to input ports), but they cannot be driven in the same way a net can.

Registers are declared in statements like this:

reg [range] list_of_register_identifiers ;

Example:

reg r1, r2;reg [31:0] bus32;

5. Operators in Verilog:

Logical, arithmetic and relational operators available in Verilog are described in Table 1.


Verilog Unary Operators:

Table 1 Verilog Operators

6.. Continuous assignments:

Continuous assignments are sometimes known as data flow statements because they describe howdata moves from one place, either a net or register, to another. They are usually thought of asrepresenting combinational logic. In general, any logic functionality which can be implemented bymeans of a continuous assignment can also be implemented using primitive instances.

A continuous assignment looks like this:

assign [delay3] list_of_net_assignments ;

Examples:

assign w1 = w2 & w3;assign #1 mynet = enable; // mynet is assigned the value after 1 time unit.


7. Procedural Blocks:

Procedural blocks are the part of the language which represents sequential behavior. A module canhave as many procedural blocks as necessary. These blocks are sequences of executable statements.The statements in each block are executed sequentially, but the blocks themselves are concurrent andasynchronous to other blocks.

There are two types of procedural blocks, initial blocks and always blocks.

initial <statement> always <statement>

There may be many initial and always blocks in a module. Since there may be many modules in amodel, there may be many initial and always blocks in the entire model. All initial and alwaysblocks contain a single statement, which may be a compound statement, e.g.

initialbegin statement1 ; statement2 ; ... end

a. Initial Block:

All initial blocks begin at time 0 and execute the initial statement. Because the statement may be acompound statement, this may entail executing lots of statements. There may be time or eventcontrols, as well as all of the control constructs in the language. As a result, an initial block maycause activity to occur throughout the entire simulation of the model.

When the initial statement finishes execution, the initial block terminates. If the initial statement is acompound statement, then the statement finishes after its last statement finishes.

Example:

initial x = 0; // a simple initialization

initial beginx = 1;y = f(x);

#1 x = 0;y = f(x);

end

// an initialization

// a value change 1 time unit later

b. Always Block:

Always blocks also begin at time 0. The only difference between an always block and an initialblock is that when the always statement finishes execution, it starts executing again. Note that ifthere is no time or event control in the always block, simulation time can never advance beyond time0. Example,


always#10 clock = ~clock;

8. Behavioral modeling constructs:

a. Conditional if-else construct:

The if - else statement controls the execution of other statements in a proceduralblock.

Syntax:if (condition)statements;

if (condition)statements;

elsestatements;

if (condition)statements;

else if (condition)statements;

................

................else

statements;

Example:// Simple if statementif (enable)

q <= d;

// One else statementif (reset == 1'b1)

q <= 0;;else

q <= d;

// Nested if-else-if statementsif (reset == 1'b0)

counter <= 4'b0000;else if (enable == 1'b1 && up_en == 1'b1)

counter <= counter + 1'b1;else if (enable == 1'b1 && down_en == 1'b1);

counter <= counter - 1'b0;


elsecounter <= counter; // Redundant code

b. Case statement:

The case statement compares an expression to a series of cases and executes the statement orstatement group associated with the first matching case. Case statement supports single or multiplestatements. Multiple statements can be grouped using begin and end keywords.

Syntax:

case (<expression>)<case1> : <statement> <case2>: <statement>.....default : <statement>endcase

Example:

module mux (a,b,c,d,sel,y);input a, b, c, d;input [1:0] sel;output y;reg y;always @ (a or b or c or d or sel)case (sel)0 : y = a;1 : y = b;2 : y = c;3 : y = d;default : $display("Error in SEL");

endcase

endmodule

9. Module instantiations and hierarchies:

Verilog allows you to represent the hierarchy of a design. A more common way of depictinghierarchical relationships is:


We say that a parent instantiates a child module. That is, it creates an instance of it to be a submodelof the parent. In this example,

system instantiates comp_1, comp_2comp_2 instantiates sub_3

Modules in a hierarchy have both a type and a name. Module types are defined in Verilog. Therecan be many module instances of the same type of module in a single hierarchy. The moduledefinition by itself does not create a module. Modules are created by being instantiated in anothermodule, like this:

module <module_name_1> (<portlist>);..

<module_name_2> <instance_name> (<portlist>);..

endmodule


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Verilog Design Entry, Synthesis, and Behavioral Simulationaboutme.samexent.com/classes/fall08/ee4301/labs/lab01e.pdf · Verilog Design Entry, Synthesis, and Behavioral Simulation-----PURPOSE