University of South Florida

Introductory Verilog Tutorial by Example

Presenter - Soumyaroop RoySeptember 17, 2007

Computer System Design Lab, 4203L

Instructor: Prof. S. Katkoori

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Objectives

The objectives of this tutorial are to:

introduce some basic constructs in Verilog

elaborate on structural and behavioral design styles

introduce testbenches

enable attendees to design the ALU from Lab 1 and its testbench.

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Verilog HDL

“The designers of Verilog wanted a language with syntax similar to the C programming language so that it would be familiar to engineers and readily accepted”

– Article on Verilog, Wikipedia

However, since Verilog is used to describe hardware, its behavior is different from that of the C language.

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Verilog Language Organization

Concurrent Statements – executed in parallelModules – models functional entities

Concurrent Assignment Statements

Primitives

Sequential Statements – executed linearlyBehavioral statements – if-then, for-loop

Data types – used to model simple hardware entities like ports, wires, registers, etc.

The concepts mentioned above are described with the help of examples in this tutorial.

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Inverter Example

// module definition for the invertermodule inv (inp, op);

// port definitionsinput inp; // input port “inp”output op; // input port “op”

// concurrent assignment statementassign op = ~inp; // ‘~’ is the unary “not” operator

// indicates the end of a moduleendmodule

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Inverter using primitives

module inv (inp, op);input inp; output op;

// primitive statement// similar to module instantiation (illustrated later)// other primitives are – and, or, etc.not (op, inp);

endmodule

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Multiplexer Example

// module definitionmodule mux2_1_bo(mux_in, sel, mux_out);

// port definitionsoutput mux_out;input sel;input [1:0] mux_in;

// concurrent assignment statementassign mux_out = (~sel & mux_in[0]) & (sel & mux_in[1]);

endmodule

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Design Styles – Structural vs. Behavioral

Structural design stylethe structure of the design is described based on the structural information of its building blocks

Behavioral design stylefunctionality of the behavior of the design is described algorithmically

The next example shall illustrate that

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Multiplexer Example - Behavioral

// module definitionmodule mux2_1_pa(mux_in, sel, mux_out);

// port definitionsoutput mux_out;input sel;input [1:0] mux_in;

// register definition; required for signals which are writtenreg mux_out;

// always block sensitive to// sel and mux_inalways @(sel or mux_in)begin// sequential statementif (sel == 1’b0)mux_out = mux_in[0];

else if (sel == 1’b1)mux_out = mux_in[1];

end

endmodule

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Multiplexer Example – Case Stmt

// module definitionmodule mux2_1_pa(mux_in, sel, mux_out);

// port definitionsoutput mux_out;input sel;input [1:0] mux_in;

// register definition; required // so that it can be written into // by a seq. statementreg mux_out;

// always block sensitive to// events on sel and mux_inalways @(sel or mux_in)begin// case statementcase (sel)1’b0: mux_out = mux_in[0];1’b1: mux_out = mux_in[1];default: mux_out = 1’bz;

endcase;endendmodule

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D-Flip Flop Example

// D flip flop modulemodule dff (q, d, clk); input d, clk; output q;

reg q;

always @(posedge clk) // positive edge triggeredbegin q = d;

end endmodule

Sensitivity list in the always block

Event triggered

always @(clk)Sensitive to both 1→0 and 0→1 transitions of clk

always @(negedge clk)Sensitive to only 1→0 transition of clk

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Testbench

Testbench is a behavioral Verilog code that supplies stimuli to the design under test (DUT) and tests its outputs (“how it behaves”) based on its functional specifications (“how it should behave”).

The next example shall illustrate it.

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Inverter Testbench

// initial blockinitial begin

inv_inp = 0; #10 inv_inp = 1; #10 inv_inp = 0;

// inv_op will be driven by u_inv

#10 $finish; // end simulationend

endmodule

// testbench module definitionmodule test_inv;

// stimulus for inverter inputreg inv_inp; // output of inverterwire inv_op;

// inverter instantiationinv u_inv (.inp(inv_inp)), .op(inv_op));

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// full adder using half adders - structuralha u1_ha(c1, s1, a_in, b_in);ha u2_ha(c2, sum, c_in, s1);or (carry, c1, c2);

// note that the “or” primitive does not need an instance name

// parameters; similar to arguments to functions in Cparameter width = 4; // parameter values can be configuredwire [width-1:0] inp; // from the instantiating module

// generate clockalways #10 clock = ~clock // where clock is defined as a reg

Miscellaneous Examples

HAab

sc

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In Lab 2, you shall design the 4-bit ALU from Lab 1 in verilog and write a testbench to simulate it.

As mentioned earlier, the design can be described structurally or behaviorally.

4-bit ALU from Lab 1

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Components needed (for one of the design options)

4-bit inverterinverter

4-bit ripple carry adderfull adder

4-bit 2-to-1 multiplexer

4-bit 4-to-1 multiplexercan be constructed out of 2-to-1 multiplexers

Note: for internal wire definitions, use the keyword “wire”

4-bit ALU - Structural

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Algorithmic description using functional operators in Verilog:

case (mode)

0 : out = bitwise invert of A

1 : out = A + 1

2 : out = A - 1

3 : out = 2*A

endcase

4-bit ALU - Behavioral

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Q & A