VCDS Tool Demonstration

Rafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka

Semiconductor Technology Academic Research Center (STARC) Abstract

The VCore(*) based Design Methodology developed in the VCDS(**) project is a novel design methodology utilizing VCores. VCores are reusable functional cores defined at high level. We designed a SoC for Wearable Computer as a vehicle application in the pilot project (Figure 1), and compared our proposed methodology with a conventional RTL based design methodology by measuring the design productivity. We

obtained very promising prospects that the design productivity could be improved 20 times for the enhanced VCDS (Figure 2). We will make a demonstration of the implemented pilot tool to show how effective our proposed methodology is. (*) VCore: Virtual Core (**) VCDS: Virtual Core based Design System

SoCSoC

Image of Application ProductsImage of Application Products

<Business Model><Business Model><Child Model><Child Model>

<Vehicle : Wearable Computer (W-Com)>Most suitable application for the evaluation of the VCDS;

- Effectiveness of design methodology – Design flexibilityDesign productivity

- VCore Reusability

Figure1. Pilot Design Project

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Figure 2. Effectiveness of VCore based Design - Productivity -

Estimation from the W-Com Design: Design productivity would be improved 20 times.

VCDS Prototype(Measured)(Assum.: Coefficientof VCore reuse = 90%)

ConventionalDesign Method(Assum.: Coefficientof IP reuse = 30%)

0.000 0.200 0.400 0.600 0.800 1.000 1.200

0.22(Productivity = 4.6)

1.0

System Verification (Co-Sim)RTL Synthesis

SW Synthesis

H V-Core Design

F & S V-Core Verification

F & S V-Core Design

Architecture Synthesis

System Spec. Definition

VCDSConventional

System Spec.&Architecture Design

HW Verification

HW Design

SW Verification

SW Design

Man-hour for Design (Relative)

Enhanced VCDS (Estimated)(Assum.: Coefficientof VCore reuse = 90%)

0.05 (Productivity = 20)

New

V-C

ore

Desig

n

×

× }

}H V-Core Verification

Design for Testability