1. HIGH SPEED CMOS PRODUCT GUIDE

TypeNumber

Function Numberof Pins

Page

TC74HCOoP/F

TCT4HCO2PIF

TC74HC03P/F

TCT4HCO4PIF

TCT4HCTO4P/F

TCT4HCUO4P/F

TC74HC08P/F

TC74HC10PlF

TC74HC1lPlF

TC74HC14PlF

TC74HC20PlF

TC74HC21PlF

TC74HC27PlF

TC74HC30P/F

TC74HC32PlF

TC74HC42PlF

TC74HC51P/F

TC74HC73PlF

TC74HC74PlF

TC74HC75PlF

TC74HC76PlF

TC74HC77PiF

TC74HC85P/F

TC74HC86P/F

TC74HC107P/F

TC74HC109P/F

TC74HC112PlF

TC74HC1 13P/F

TC74HC123PlF

TC74HC125PlF

OUAD 2.INPUT NAND GATE

OUAD 2-INPUT NOR GATE

OUAD 2. INPUT NAND GATE (OPEN DRAIN)

HEX INVERTER

HEX INVERTER

HEX INVERTER (SINGLE STAGE)

OUAD 2.INPUT AND GATE

TRIPLE 3. INPUT NAND GATE

TRIPLE 3- INPUT AND GATE

HEX SCHMITT INVERTER

DUAL 4-INPUT NAND GATE

DUAL 4.INPUT AND GATE

TRIPLE 3.INPUT NOR GATE

S.INPUT NAND GATE

OUAD 2.INPUT OR GATE

BCD TO DECIMAL DECODER

DUAL 2W-21 AND/OR INVERT GATE

DUAL J-K FLIP.FLOP WITH CLEAR

DUAL D FLIP-FLOP WITH PRESET AND CLEAR

4.BIT D-TYPE LATCH

DUAL J-K FLIP-FLOP WITH PRESET AND CLEAR

4-BIT D.TYPE LATCH

4.BIT MAGNITUDE COMPARATOR

OUAD EXCLUSIVE OR GATE

DUAL J.K FLIP.FLOP WITH CLEAR

DUAL I -R TLIP-FLOP WITH PRESET AND CLEAR

DUAL J.K FLIP.FLOP WITH PRESET AND CLEAR

DUAL J.K FLIP-FLOP WITH PRESET

DUAL MONOSTABLE MULTIVIBRATOR

OUAD BUS BUFFER (3-STATE)

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 4

1 6

1 4

1 4

1 4

1 6

1 6

1 4

1 6

1 4

1 4

1 6

1 6

1 4

1 6

1 4

107

1 1 0

1 1 3

117

120

123

125

129

132

1 3 5

1 3 9

142,

1 4 5

1 4 8

1 5 1

1 5 4

1 5 8

162

167' t 72

177

182

187

192

1 9 6

201

206

211

216

224

TypeNumber

Function Numberof Pins

Page

TC74HC126PlF

TC74HC131PlF

TC74HCr32PlF

TC74HC133P/F

TC74HC137PlF

TC74HCT137PlF

Tg74HC138P/F

TC74HCT138P/F

TC74HC139P/F

TC74HC147PlF

TC74HC148PlF

TCT4HC1slP/F

TC74HC153P/F

TC74HC154P

TC74HC155P/F

TC74HC157PlF

TC74HCls8P/F

TC74HC160P/F

TC74HC161P/F

TC74HC162P

TC74HC163P/F

TC74HC164PlF

TC74HC165P/F

TC74HC166P/F

TC74HC173PlF

TC74HC174PlF

TC74HC175PlF

TC74HC181P

TC74HC182PlF

TC74HC190PlF'

OUAD BUS BUFFER (3.STATE}

3-TO€ LINE DECODER/LATCH

OUAD 2.INPUT SCHMITT NAND

l3- INPUT NAND GATE

3-TOA LINE DECODER/LATCH

3-TO€ LINE DECODER/LATCH

3-TO-8 LINE DECODER

3-TO€ LINE DECODER

DUAL 2-TO4 LINE DECODER

1O.TO4 LINE PRIORITY ENCODER

8-TO-3 LINE PRIORITY ENCODER

S.CHANNEL MULTIPLEXER

DUAL 4 -CHANNEL MULT IPLEXER

4.T0-16 LINE DECODER

DUAL 2.TO4 LINE DECODER

OUAD 2.CHANNEL MULTIPLEXER

OUAD 2.CHANNEL MULTIPLEXER ( INV.) ,

SYNC. DECADE COUNTER WITH ASYNC. CLEAR

SYNC. BINARY COUNTER WITH ASYNC. CLEAR

SYNC. DECADE COUNTER WITH SYNC. CLEAR

SYNC. BINARY COUNTER WITH SYNC. CLEAR

8-BIT SIPO SHIFT REGISTER

8.BIT PISO SHIFT REGISTER

8-BIT PISO SHIFT REGISTER

OUAD D-TYPE REGISTER (3-STATE)

HEX D FLIP.FLOP WITH CLEAR

OUAD D FLIP-FLOP WITH CLEAR

AL ITHMETIC LOGIC UNIT

LOOK AHEAD CARRY LOGIC

BCD UP/DOWN COUNTER

1 4

1 6

1 4

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 6

24

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 4

1 6

1 6

1 6

1 6

1 6

24

1 6

1 6

224

229

235

239

,242

248

254

259

264

268

272

277

282288

293

297

297

302

302

302

302

512

317

323

329

334

339

344

355

362

TypeNumber Function

Numberof Pins

Page

TC74HC191P/F

TC74HC192PlF

TC74HC193P/F

TC74HC194PlF

TC74HCl95P/F

TC74Hg221PlF

TC74HC237PlF

TC74HC238PlF

TC74HC240PlF

TCt4HCT240P

'tc74HC241PlF

TC74HCT241P

TC74HC242PlF

TC74HC243PlF

TC74HC244PlF

TC74HCT244P

TC74HC245PlF

TC74HCT245PlF

TC74HC251PlF

TC74HC253PlF

TC74HC257PlF

TC74HC258PlF

TC74HC259PlF

TC74HC273PlF

TC74HC279PlF'TC74HC280PlF

T.cta{czegplr

TC74HC298P/F

TC74HC299P

TC74HC323P

4-BIT BINARY UP/DOWN COUNTER

SYNC. UP/DOWN DECADE COUNTER

-"ilYll.g'.-uP/"P.9Jx-,"atNARY,"c.*o",!llf IFF4.BIT PIPO SHIFT REGISTER

4.BIT PIPO SHIFT REGISTER

DUAL MONOSTABLE MULTIVIBRATOR

3-TO€ LINE DECODER/LATCH

3.TO-8 LINE DECODER

OCTAL BUS BUFFER (3.STATE/INV.}

OCTAL BUS BUFFER (3-STATE/INV.I

OCTAL BUS BUFFER (3-STATE)

OCTAL BUS BUFFER (3-STATE)

OUAD BUS TRANSCEIVER (3-STATE/INV.)

OUAD BUS TRANSCEIVER (3.STATE)

OCTAL BUS BUFFER (3-STATE)

OCTAL BUS BUFFER (3.STATE}

OCTAL BUS TRANSCEIVER (3-STATE)

OCTAL BUS TRANSCEIVER (3.STATE)

8-cHANNEL MULTrPueien (3-srATE)

DUAL 4-CHANNEL MULTIPLEXER (3.STATE)

OUAD 2-CHANNEL MULTIPLEXER (3.STATE)

OUAD 2.CHANNEL MULTIPLEXER (3.STATE/ INV.)

8.BIT ADDRESSABLE LATCH

OCTAL D FLIP-FLOP WITH CLEAR

OUAD S.R LATCH

9-BIT PARITY GENERATOR/CHECKER

4.BIT BINARY FULL ADDER

OUAD 2.CHANNEL MULTIPLEXER/REGISTER

8-BIT PIPO SHIFT REGISTER

8.BIT PIPO SHIFT REGISTER

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 6

20

20

20

20

l4

14

20

20

20

20

1 6

1 6

1 6

1 6

1 6

20

1 6

1 4

1 6

1 6

20

20

362

372

372

381

387

393

401

107

411

117

411

117

122

422

4il

417

127,

432

437

282

442

442

447

453

458

462

466

470

475

475

TypeNumber Function Number

of PinsPage

TC74HC3ilP/F

TC74HC356P/F

TC74HC365P/F

TC74HC366P/F

TC74HC367P/F

TC74HC368P/F

TC74HC373P/F

TC74HCT373PlF

TC74HC374PlF

TC74HCT374PlF

TC74HC375P/F

TC74HC377PlF

TC74HC386P/F

TC74HC390P/F

TC74HC393P/F

TC74Hc/.23PlF

TC74HC533P/F

TC74HC534P/F

TC74HC540P/F

TC74HCT540P/F

TC74HC541PlF

TC74HCTs41PlF

TC74HC563P/F

TC74HCT563P

TC74HCs64P/F

TC74HCT564P

TC74HCs73P/F

TC74HCT573P

TC74HC574PlF

TC74HCT574P

S.CHANN E L MU LTIPLEX ER/REGISTER

S.CHANNEL MULTIPLEX ER/REG ISTER

HEX BUS BUFFER I3-STATE}

HEX BUS BUFFER (3-STATE/INV.I

HEX BUS BUFFER (3.STATE)

HEX BUS BUFFER (3.STATE/INV.)

OCTAL D-TYPE LATCH (3-STATE}

OCTAL D.TYPE LATCH (3-STATEI

OCTAL D.TYPE FLIP.FLOP (3-STATEI

OCTAL D.TYPE FLIP.FLOP (3-STATE}

OUAD D.TYPE LATCH

OCTAL D-TYPE FLIP.FLOP

OUAD EXCLUSIVE OR GATE

DUAL DECADE COUNTER

P.-y. 3L Bl NARY CouNrrER.".-.- .DUAL MONOSTABLE MULTIVIBRATOR

OCTAL D.TYPE LATCH (3.STATE/INV.)

OCTAL D-TYPE FLIP.FLOP (3-STATE/INV

OCTAL BUS BUFFER (3-STATE/INV.)

OCTAL BUS BUFFER (3.STATE/INV.)

OCTAL BUS BUFFER (3.STATE}

OCTAL BUS BUFFER (3.STATE}

OCTAL D-TYPE LATCH (3-STATE/INV.)

OCTAL D.TYPE LATCH (3.STATE/INV.)

OCTAL D.TYPE FLIP-FLOP (3.STATE/INV

OCTAL D.TYPE FLIP-FLOP (3-STATE/INV

OCTAL D-TYPE LATCH (3-STATE)

OCTAL D-TYPE LATCH (3.STATEI

OCTAL D.TYPE FLIP-FLOP (3.STATE}

OCTAL D-TYPE FLIP.FLOP (3-STATE)

20

20

1 6

16

1 6

1 6

20

20

20

20

1 6

20

1 4

1 6

1 4

1 6

20

20

20

20

20

20

20

20

20

20

20

20

20

20

485

191

497

197

502

502

507

5 1 4

5 1 9

526

532

536

541

545

552

5s8

507

5 1 9

566

571

566

571

507

576

5 1 9

582

507

576

5 1 9

582

TypeNumber

Function Numberof Pins Page

TC74HC590P

TC74HC592P

TC74HC593P *

TC74HC595P

TC74HC597P/F

TC74HC620P

TC74HC623P

TC?4HC640P/F

TCT4HCTilOP/F

TC74HC643PtF

TC74HCT643PlF

TC74HC646P

TC74HCT646P

TC74HCil8P

TC74HCT648P

TC74HC651P

TC74HCT651P

TC74HC652P

TC74HCT652P

TC74HC670P

TC74HC688P/F

TC74HC690P

TC74HC691P

TC74HC692P

TC74HC693P

TC74HC696P

TC74H0697P

TC74HO698P r

TC74HO699P'

TCT4H@,0p,2PIF

8-BIT BINARY COUNTER/REGISTER (3.STATE)

8.BIT REGISTER/BINARY COUNTER

8.BIT REGISTER/BINARY COUNTER (3-STATE)

8.BIT SHIFT REGISTER/LATCH (3-STATE}

8.BIT LATCH/SHIFT REGISTER

OCTAL BUS TRANSCEIVER (3.STATE/INV.)

OCTAL BUS TRANSCEIVER (3-STATE)

OCTAL BUS TRANSCEIVER (3.STATE/INV.}

OCTAL BUS TRANSCEIVER {3-STATE/INV.)

OCTAL BUS TRANSCEIVER (3-STATE)

OCTAL BUS TRANSCEIVER (3-STATE)

OCTAL BUS TRANSCEIVER/REGISTER (3-STATE)

OCTAL BUS TRANSCEIVER/REGISTER {3-STATE)

OCTAL BUS TRANSCEIVER/REGISTER (3-STATE/INV.}

OCTAL BUS TRANSCEIVER/REGISTER (3.STATE/INV.)

OCTAL BUS TRANSCEIVER/REGISTER (3-STATE/IITIV.}

OCTAL BUS TRANSCEIVER/REGISTER f3-STATE/INV.)

OCTAL BUS TRANSCEIVER/REGISTER (3.STATE)

OCTAL BUS TRANSCEIVER/REGISTER (3-STATE}

4-WORD x 4-BlT REGISTER FILE (3-STATEI

8-BIT EOUALITY COMPARATOR

DECADE COUNTER REGISTER (3.STATEI

4.BIT BINARY COUNTER REGISTER (3.STATEI

DECADE COUNTER REGISTER (3.STATE)

4-BIT BINARY COUNTER REGISTER (3.STATE}

U/D DECADE COUNTER/REGISTER (3.STATEI

U/D 4.BIT BINARY CTR./REGISTER (3.STATE}

U/D DECADE COUNTER/REGISTCN (3-STATEI

U/D 4.BIT BINARY CTR./REGISTER (3-STATEI

DUAL +INPUT NOR GATE

1 6

1 6

20

1 6

1 6

20

20

20

20

20

20

24

24

24

24

24

24

24

24

1 6

20

20

20

20

20

20

20

20

20

1 4

s88

596

604

612

620

620

427

452

127

132

625

633

625

633

611

649

61r

619

657

661

668

668

680

680

692

692

703

TypeNumber Function

Numberof Pins

Page

TC74HO.l017PlF

TC74HC4020PlF

TC74HC4022PIF

TC74HC4024PlF

TC74HC4028PlF

TCT4HC40/,OPIF

TC74HC4049PlF

TC74HC40s0P/F

TC74HC4051P *

TC74HC4052P *

TC74HC4053P r

TC74HC4060P/F

TC74HC4066P/F

TC74HC4072PlF

TC74HC4075PlF

TC74HC4078PlF

TC74HC/,O94PlF

TC74HC40102P

TC74HC40103P

TC74HC4511PlF

TC74HC4514P

TC74HC4515P

TC74HC4518PlF

TC74HC4520PtF

TC74HU538P/F

TC74Hc4il3PlF

TC74HCT70o7PlF

TC74HC7266P/F

TCt4HC7292P

TC74HC729ttP

DECADE COUNTER/DIVIDER

14-STAGE BINARY COUNTER

OCTAL COUNTER/DIVIDER

7-STAGE BINARY COUNTER

BCD-TO-DECIMAL DECODER

12.STAGE BINARY COUNTER

H E X B U F F E R ( I N V . )

HEX BUFFER

S.CHANNEL ANALOG MULTIPLEXER

DUAL 4.CHANNEL ANALOG MULTIPLEXEB

TRIPLE 2-CHANNEL ANALOG MULTIPLEXER

14.STAGE BINARY COUNTER/OSCILLATOR

OUAD BILATERAL SWITCH

DUAL 4- INPUT OR GATE

TRIPLE 3- !NPUT OR GATE

S. INPUT.OR/NOR GATE

8.BIT SIPO SHIFT REGISTER/LATCH (3-STATE}

DUAL BCD PROGRAMMABLE DOWN COUNTER

8.BIT BINABY PROGRAMMABLE DOWN COUNTER

BCD TO 7 SEGMENT L/D/D (LED}

4-TO-16 LINE DECODER/LATCH

4.T0-16 LINE DECODER/LATCH ( !NV.)

DUAL DECADE COUNTER

DUAL 4.BIT BINARY COUNTER ,

DUAL MONOSTABLE MULTIVIBRATOR

BCD TO 7 SEGMENT LIDID (LCD}

HEX BUFFER

OUAD EXCLUSIVE NOR GATE

PROGRAMMABLE DIV IDER/TIMER

PROGRAMMABLE DIVIDER/TIMER

1 6

1 6

1 6

1 4

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 6

1 4

1 4

1 4

1 4

1 6

1 6

1 6

24

24

24

1 6

1 6

1 6

1 6

l 4

14

t 6

1 6

706

7 1 2

7 1 7

723

728

733

738

738

u,748

753

757

761

765

772

772

785

790

790

795

795

802

8 r 0

8 1 6

E r 9023E2g

Note: 1. All DIP 24 pin products service as an enclosure of the narrow type (300mil)2. * denotes the products under development

2. HIGH SPEED CMOS SETECTION GTIIDE

FTJNCTTON TYPE N['MBER,

GATE NANDNORANDORII{VERTER

74HC{n, 74HC'03, 74HC1 0, 7 4Hc,;O, 74HC30, 7 4HCl337 4H@2, 7 4HC27, 7 4HC4002, 7 4HC407 874HC08,74HCll, 74HC2l7 4HC32, 7 4HC407 5, 7 4HC407 2, 7 4HC407 I74HCU04, 74HCI)4, 7 4HC|O4

SCHMITT TRIGGER 74HCt4,74HCt32

MULTIFUNCTION 74HC5 l, 74HC86, 74HC386, 7 4HC7 266

BI,JFFER 7 4HC4049, 74HC4050, 7 4HCT7 007

3.STATE 7 4HCt25, 7 4HCl26, 7 4HC240, 7 4HCT 240, 7 4HC24l,7 4HCT24 t, 7 4HC244, 7 4HCT24 4, 7 4HC3 6 5, 7 4HC3 66, 7 4HC367,74HC368, 74HC540, 74HCT540,'.| 4HC54l, 74HCT541

BIDIRECTIONAL 7 4HC242, 7 4HC243, 7 4HC245, 7 4HCT24 5, 7 4HC6207 4HC623, 7 4HC640, 7 4Hef 640, 7 4HC643,'t 4HCT 643

FLIP.FLOP J-K, FLIP-FLOP 7 4HC7 3, 7 4HC7 6, 7 4HCt07, 7 4 HC I 09, 7 4HCt 12, 74HCl I 3

D F L IP-FLOP 7 4HC7 4, 7 4HCt7 4, 7 4HCL7 5, 7 4HC27 3,',t 4Hc37'.l

3.STATE 74HC374,74HCT37474HC574,74HCT57474HCT648, 74HC651

7 4HC534,',t 4HC564, 7 4HCT 5 64,7 4HC646, 7 4HCT646, 7 4HC648,74HCT65 l, 7 4HC652, 7 4HCT652

LATCH

I rsrarE

7 4HC7 5, 7 4HC7 7, 7 4HC259, 7 4HC27 9, 7 4HC37 S

7 4HC37 3, 7 4HCt 37 3, 74HC5 3 3, 7 4HC5 63, 74HCT5 6 3,'t4HC573,74HCT573

MULTIVIBRATOR 7 4HCt23, 7 4HC22t, 7 4HC423, 74HC45 38

DECODER

I z-sncrtrnxr

7 4HC42, 7 4HCl3l, 7 4HCt37, 7 4HCT 137, 74HC1 38,74HCT1 38, 74HCl 39, 7 4HCr 54, 74HC1 55, 7 4HC237,7 4HC2?8, 7 4HC4028, 7 4HC4 5 | 4, 74HC45 r 5

74HC45t1,74HC4543

ENCODER 74HC147,74HC148

REGISTER 7 4HCt 64, 74HCt 65, 7 4HCt 66, 7 4HCt7 3, 7 4HCI94, 74HC1 95,7 4HC299, 7 4HC323, 74 HCs 95, 7 4HC5 97, 7 4HC67 0, 7 4HC409 4

COUNTER BINARY 7 4HCt6t, 7 4HCt 63, 74HCl 9 1, 7 4HCt93, 7 4HC393, 74HC5 90,7 4HC592, 74HC5 9 3, 7 4HC69 t, 7 4HC693, 7 4HC697, 7 4HC699,74HC4520

DECADE 7 4HC I 60, 7 4HCt 62, 74HC1 90, 7 4HCt92, 74HC390, 74HC690,7 4HC692, 7 4HC696, 7 4HC698, 74HC45 I 8

DIVIDER 7 4HC4017, 7 4HC4020, 7 4HC4022, 7 4HC4024, 74HC4040,7 4 HC4060, ? 4 HC40 I 0 2, 7 4HC40 tO3, 7 4HC7 292, 7 4HC7 29 4

MULTI.PLEXER ANALOG 74HC405 1, 7 4HC4052, 74HC4053, 7 4HC4066

DIGITAL 74HC15 1, 74HCl 5 3, 74HCl 5 7, 74HC1 5 8, 7 4HC2SI, 7 4HC25?,7 4HC257, 74HC25 8, 7 4HC298, 7 4HC354, 74HC356

OTHERS CQMPARATOR 74HC85,74HC688

ADDER 74HC283

ALU 74HC181,74HCt82

PARITY TREE 74HC280

l 0

GATETypeNumber

Function EquivalentLSTTL

EquivalentcMos.

PinNumber

74HC 0074HC 0374HC 1074HC 2074HC 30T A H C I 3 i

QUAD 2-INPUT NAND GATEQUAD 2-TNPUT NAND GATE (oPEN DMrN )TRIPLE 3-INPUT NA}ID GATEDUAL 4-INPUT NAND GATE8-INPUT NAND GATEl3-INPUT NAND GATE

LSOOLSO3LS]-OLS2OLS3OLS133

4011, 740O,k40107, '15029

402340L24068

L4T414T4I41 6

7 4HC 0274HC 2774HC4002TLHe.ttOTR

QUAD 2-INPUT NOR GATETRIPLE 3-INPUT NOR GATEDUAL 4-INPUT NOR GATE8-INPUT OR/NOR GATE

LSO2LS27

*LS25

40014025,*4000

40024078

14L4L414

74HC74HC74HC

08112L

QUAD 2-INPUT AND GATETRIPLE 3-INPUT AI{D GATEDUAL 4-INPUT AND GATE

LSOSLS11LS21

408140734082

T4L4L4

74HC 3274HC407574HC407274HC4078

QUAD z-INPUT OR GATETRIPLE 3-INPUT OR GATEDUAL 4-INPUT OR GATE8-INPUT OR/NOR GATE

LS32407 540724078

7 L4014L414

41

74HC74HC74HC

04T04u04

HEX INVERTERHEX INVERTERHEX INVERTER (SINGLE STAGE)

LS04LS04

*LS04

*4069U*4069U

4069u.7404u

L414I4

74HC 5174HC 8674HC726674HC 386

DUAL 2W-2I AND/OR INVERT GATEQUAD EXCLUSIVE 0R GATEQUAD EXCLUSM NOR GATEQUAD EXCLUSIVE OR GATE

LS51LS86 , LS386

*LS266

LS86 . tS385

*4085403040774030

L41414I4

HC L474HC I3274 HEX SCHMITT INVERTER

QUAD 2-INPUT SCHMITT NANDLS14LS132

45844093

1414

* Suggested alternative

GATE

QUAD 2.INPUT NAND GATE00

P o s i t i v e ' l o g i c : Y = A E

QUAD z-INPUT NOR GATE02

P o s i t i v e l o g i c : Y = A + E

3A

11

GATE (Cont inued)

0uAD 2-TNPUT NAND GATE (0PEN DRArN)

03

P o s i t i v e l o g i c : f =

vcc 4E} 44 4Y 3B

AB

3A 3Y

HEX INVERTER04T04u04

P o s i t i v e l o g i c : f :vcc 6A 6Y 5/, 5Y

F4A 4y

QUAD 2.INPUT AND GATE08

P o s i t i v e l o g i c : f = AB

3AvCC 49 4A ay 38

TRIPLE 3. INPUT NAND GATEt 0

P o s i t i v e l o g i c : Y = A B d

vcc 1c LY 3C 38 3A

TRIPLE- 3-INPUT AND GATE

l 1

P o s i t i v e ' l o g i c :

ABC

1Y

HEX SCHMITT INVERTER

1 4

P o s i t i v e l o g i c : Y r

5Y 4A

12

GATE (Cont inued)

DUAL 4.INPUT NAND GATE20

Posi t ive ' log ' ic : Y = IBCD

vcc zD zc Nc pB zA zy

DUAL 4-INPUT AND GATE21

Posi t i ve ' log i

c : Y = ABCD

vcc 2D 2c Nc ?B 2A

TRIPLE 3- INPUT NOR GATE

2 7

P o s i t i v e ' l o g i c :

Y = A+B+C

vcc l-c lY

8-INPUT NAND GATE30

Posit ive log' ic: Y =TBCDEFGH

V C C N C H G N C N C Y

QUAD z.INPUT OR GATE32

P o s i t j v e l o g i c : Y = A + B

VCC 48 4A 4Y 3B 3A 5Y

Ii-l '-.; , t--'

: f t i' " - - f ' _ ! ' -

r, : . . i I i' -j '',--

i it ;II

DUAL 2 WIDE-2 INPUT AND/OR INVERT GA-

5 l

P o s ' i t i v e l o g i c : 1 Y = f f i

2Y=2[-291fi.fi

1 3

GATE (Cont inued)

QUAD 2-INPUT EXCLUSIVE-OR GATE

86

Posi t ive logic: Y=A@B=AB+AE

VCC 48 4A 4Y 38 3A 3Y

QUAD 2-INPUT SCHMITT NAND GATE

132

P o s i t i v e l o g i c : Y = T B -

VCC 48 4A 4Y 3B 3A 3Y

I3- INPUT NAND GATE. |33

Positive logic: Y=ABCDEFGHTJK[]*f

V C C M L K J I H Y

QUAD 2-INPUT EXCLUSIVE-NOR GATE7266

Positive logic: Y=[-@-9=43+ffi

VCC 48 4A 4Y 3Y 3B 3A

QUAD z-TNPUT EXCLUSTVE-OR GATE

386

Posi t ive logic: Y=AOB=AB+AB-

vcc 48 +t ax 3Y 38 3A

DUAL 4-INPUT NOR GATE4002

Posit ive logic: Y=ATBTCTD

vcc 2y 2A 28 2C 2D

1 4

GATE (Cont inued)

DUAL 4-INPUT OR GATE407?

Posit ive logic' Y=A+B+C+D

vcc 2Y 2D 2c 28 2A

TRIPLE 3.INPUT OR GATE

4075

Pos i t i ve log ic : Y=A+B+C

vco 3c 3E| 3A 3Y

8-INPUT NOR GATE

4078

P o s i t i v e l o g i c :

V C C X H

Y=A+B+C+D+E+F+G+H

G F E N C

N C G N D

1 5

BUFFER

TypeNumber

Function EquivalentLSTTL

EquivalentcMos.

PinNumber

7 4HCr7 00i74HC404974HC4050

HEX BUFFERHEX BUFFER (INVERTING)HEX BUFFER

* LS0T40494050

L41616

74HC L2574HC L2674HC 24074HCT24074HC 24L74HCT24L74HC 24474HCr24474HC 36574HC 36674HC 36774HC 36874HC 54074HCT54074HC 54r74HCT54L

QUAD BUS BUFFERQUAD BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFERHEX BUS BUFFERHEX BUS BUFFERHEX BUS BUFFERHEX BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFEROCTAL BUS BUFFER

(II{VERTING)(INVERTING)

(INVERTI}IG)

(INVERTII.IG)(rlrvERTrNG)(INVERTING)

LS125LS126LS24Ors240LS24LLS24IL5244L5244LS3654LS366ALS367ALS368ALS540LS540LS541LS541

50245025

50r_2

L4L42020202020201616161620202020

74HC 24274HC 24374HC 2457 4HCT24574HC 62074HC 62374HC 64074HCT64074HC 64374HCT643

QUAD BUS TMNSCETVER (INVERTING)

QUAD BUS TRANSCEIVEROCTAL BUS TMNSCEIVEROCTAL BUS TMNSCEIVEROCTAL BUS TMNSCEIVEROCTAL BUS TRANSCEIVEROCTAL BUS TMNSCEIVEROCTAL BUS TRANSCEIVEROCTAL BUS TRANSCEIVEROCTAL BUS TMNSCEIVER

(TNVERTTNG)

(INVERTING)(INVERTING)

L5242LS243L5245L5245LS62OL5623LS64OLS640LS643LS643

L4L42020202020202020

* Suggested alternative

BUFFER

HEX BUFFER.

T7007

P o s i t i v e l o g i c :

v c c 6 A 6 Y 5 A

Y = A

QUAD BUS BUFFER125

P o s i t i v e ' l o g i c :Y = A

5 Y 4 A 4Y

r.-e l,c, t y zd zt 2Y GND

l 6

BUFFER (Cont i nued )

QUAD BUS BUFFER

126

P o s i t i v e ' l o g i c :

vcc L G 4 A 4 Y 3 G 3 Y

I A I Y 2 G 2 A 2 Y

OCTAL240T240

BUS BUFFER ( INVERTING)

v"o eo rTr a.g ttezns rW eez lt{ 2A"r

rE r,c,r z1+ ua ?ft rAs zre t* e?r el.ro

OCTAL BUS BUFFER241T241

tG l.Al 2y4 IAZ zys l-AS 2y? 1A4 Ayl oND

20 lYl 2A4 IYz 2A3 1Y5 2|A I.r4 2AI

QUAD BUS TRANSCEIVER ( INVERTiNG)

242

vcc N C 1 B 2 B 3 B 4 B

QUAD BUS TRANSCEIVER

24sOCTAL BUS BUFFER244T244

v"s zd- t-yt ?A4 lYz 3A3 IW 2A2 r-Yt 2AL

rG ]-A.I ZYL IA?" ?Y3 1A5 ?YZ IA4 2Y1 OND

1 7

BUFFER (Cont inued)

OCTAL BUS

245

T245

vcc c

TRANSCE I VER

B 1 B 3 Py ' . B.5 B 6

D I R A 1 jtz A g A4 A 6 L 7 A 8

HEX

365

BUS BUFFER

HEX BUS BUFFER

366

( I N V E R T I N G )

Q 2 6 A 6 Y 4 A 4 y

HEX BUS

367

BUFFER

vcc c 2 6 A O Y 5Y 4A

H E X B U S B U F F E R ( I N V E R T I N G )

368

1 A 1 v 2 A 2 Y 3 Y

OCTAL BUS BUFFER ( INVERTING)

540

T540

v"" Ea ?r Tz -ys

T+ yo tb y? V R

A f A Z A 4 A5 A 6 A 1 A 8

t 8

BUFFER (Cont i nued)

OCTAL BUS BUFFER

541

T54t

VOc OZ y1 yz Y4 Y 5

olf, al- az !|.6 A7 A8 GND

OCTAL BUS TRANSCEIVER ( INVERTING)

620

ENABLE GBA

A I

GABENABLE

OCTAL BUS TRANSCEIVER

623

ENABLE GAB

OCTAL BUS TRANSCEIVER

640

T640

vcc c B t 92 B3 84

( I N V E R T I N G )

B 5 B ? B 8

D I R A I L 2 A 3 A 4 A 5 A 6 A 7 A 8

OCTAL

643

T643

BUS TRANSCEIVER HEX BUFFER/CONVERTER ( INVERTING)

4049

6 Y 6 A N C 5 Y 5 A + Y 4 A

vcc 1 Y l - A 2 Y 2A 3 Y

l 9

) " :BUFFER (Cont inued)

HEX BUFFER/CONVERTER

4050

20

F L I P-FLOP

lYpeNumber Function

EquivalentLSTTL

EquivalentCMOS.

PinNumber

74HC 7374HC 76

74HC rO774HC LOg

74HC LLz

74HC LL3

DUAL J-K FLIP-FLOP WITH CLEARDUAL J-K FLIP-FLOP WITH PRESET

AND CLEARDUAL .J-K FLIP-FLOP WITH CLEARDUAL J-R FLIP-FLOP WITH PRESET

AND CLEARDUAL J-K FLIP-FLOP I^IITH PRESET

AND CLEARDUAL J-K FLIP-FLOP WITH PRESET

LS73A , LS107 t

LS76A , LS l12d

LS107A , LS73 r

LSlO9A

LS76A ,LS112 r

LS113A

4027 ,7 47 (

4027 ,7 47 C

L4

1 6

L4

L 6

I 6

L4

t4HC t4

74HC l-7474HC L7574HC 27374HC 377

DUAL D FLIP-FLOP WITH PRESETAND CLEAR

HEX D FLIP.FLOP T{ITH CLEAR

QUAD D FLIP-FLOP WITH CLEAROCTAL D FLIP-FLOP WITH CLEAROCTAL D-TYPE FLIP.FLOP

LS744

LSIT 4L5175L5273

4013

4017 44017 5

L4

L6162020

74HC 37474HCT37474EC 53474HC 56474HCT56474HC 57474HCT57 474HC 6467 4HCT64674HC 64874HCT64874HC 65L74HCT65174HC 65274HCT652

OCTAL D-TYPE FLIP.FLOP (3-STATE)OCTAL D-TYPE FLIP-FLOP (3-STATE)OCTAL D-TYPE FLIP.FLOP (3-STATE/INV. )OCTAL D-TYPE FLIP.FLOP (3-STATE/INV.)OCTAL D-TYPE FLIP-FLOP (3-STATE/INV. )ocTAL D-TYPE FLrP-FLOP (3-STATE)ocTAL P-TYPE FLrP-FLOP (3-SrAru;OCTAL BUS TRANSCEIVER/REGISTEROCTAL BUS TMNSCEIVER/REGISTEROCTAL BUS TRAI{SCEIVER/REGISTER (INV.)OCTAL BUS TMNSCEIVER/REGISTER (INV.)OCTAL BUS TRAI{SCEIVBR/REGISTER (INV.)OCTAL BUS TMNSCEIVER/REGISTER (INV.)OCTAL BUS TMNSCEIVER/REGISTEROCTAL BUS TRANSCEIVER/REGISTER

LS37 4,L557 4LS37 4,L557 4

LS534'LS564

LS564LS37 4 ,L557 4LS374 , LS574

LS646LS646LS648LS648LS651LS651LS652L5652

20202 020202020242.4242424242424

* Suggestedalternative

FL I P-FLOP

CLEAR DUAL DCLEAR

74

L

73

vcc eclF eo ecx EFn zQ ZC

rET rdlF rx vcc Zd zcr,F ar

21

FLIP-FL0P (Cont inued)

DUAL J-KCLEAR

76

FLIP-FLOP hl ITH PRESET AND DUAL107

J - K FLIP-FLOP WITH CLEAR

_ 9 ^ vvcclcLR lc1( 2K zcLR-""

DUAL J-R- FLIP-FLOP t^lITH PRESETCLEAR

1 0 9

yqg krcl,R ZJ zK acK zpR ze zq

DUAL J-K FLIP-FLOP WITH PRESETCLEAR

112

vcc LCLRecmZcr ar Z; 'Zen zq

DUAL J-K FLIP-FLOP t ,JITH

l l 3

lQ GND

HEX D FLIP-FLOP I ' ' | ITH CLEAR

174

vcc 6e 6D 5D oe 4D 4e CI.oCK

k aCLR

22

FLIP-FLOP (Cont inued)

QUAD D FLIP-FLOP WITH CLEAR

1 7 5

dr.een rq rE- ro 2D ?0

OCTAL D FLIP-FLOP WITH CLEAR

273

7 D ? Q 6 Q 6 D

OCTAL D374T374

FLrP-FLoP (3-STATE) OCTAL D FLIP-FLOP

377

5Q CI,oK

ocrAL D FLrP-FL0P (3-STATE/rNV.)

534

Q4 CTOCX,

Q1 de

OCTAL D FLIP-FLOP (3.STATE/INV.)

564T564

voo d6 oJ qT G a4 G G GoLosK

23

FLIP-FL0P (Cont inued) '

0CTAL D FLIP-FL0P (3-STATE)

574

T57 4

Q 4 Q6 Q7 cIOCKQlvcc

OCTAL BUS TRANSCEIVER REGISTER( 3-STATE )

646

T646 crc&aBlcrVccBA I o Bl BA BS 84 BO 86 87 BB

JAFryFryry Fryryry tr.'t r r r r l l l l l l : J :| |

. ' u o . * o 8 1 B z B s 8 4 D t , B c B r y l i I

i t-1'* '" I Il l I *ABDIRAT Az As 44 Ab A6 A? As I i

l \-Twl_iMG]iTEb-TiIjJ

"i"f- "+fl.fi A.r A2 43 A 4 A5 46 A? A8 GND

OCTAL BUS TRANSCEIVIR REGISTTR(3-STATE/ INV. )

648

T648

A f A 2 A 3

. DIRECTION

C B A S B A B f 8 2 B 5 8 4 8 5 8 6 B ?

cAB 88

SAB DIR A1 A;E A3 A4 A5 A6 A7 A8

OCTAL BUS TRANSCI IVER REGISTIR( 3-srATE/ I NV . )

65. |

T65l '10:*CLOCK TENABL,E

vcc M i GBA Bl- Ba Bs 84 B5 86 B? BB

, t4 lTl tTl tTryqqF,Tl FqEtiab=r| | c a e c e e B 1 8 2 B s 8 4 8 5 B 5 E l

l l lI I

G B A

ldcAB *l-J Il l l s A B o A B A r A z A s A 4 A 5 A 6 A z A 8 | |

"T{rt#fffiEAr Aa As A4 A5 .c'6 A? AB GND

OCTAL BUS TRANSCEIVERS REGISTER( 3-STATE )

652

T652 sELEcrcTPcK;h'IABLE

vcc s I llne ar na Bg 84 E|5 86 B7

cl,oq( | ENABLE AL A2AB I GAB

SELECTAB

CBA SBA B1 BA B3 84 B5 86 gIC}BA

CAB

8A3 CIAB Af A2 A5

24

M U L T I V I B R A T O R

TypeNumber

FunctionEquivalentLSTTL

EquivalentCMOS.

PinNumber

74HC l2374HC 22L74HC 42374HC4538

DUAL MONOSTABLE MULTIVIBMTORDUAL MONOSTABLE MULTIVIBRATORDUAL MONOSTABLE MULTIVIBMTORDUAL MONOSTABLE MULTIVIBMTOR

LSl23LS22LL5423

:tLS423

rt4538 ,*4528*4538,*4528*4538,x4528

4538, 4528

16161616

+ Suggestedalternative

MULTIVIBMTOR

DUAL RETRIGGERABLE MONOSTABLE MULTI-VIBRATOR

123

F U N C T I O N T A B I , E

I N P U T S O U T P U T S

ci.nen A B e e ,LH

H

HHr

X XH XX LL J

1 _ Hl r n

I , HI , Hr . H

JL .|'f

J L 1 rn ' r r

X : D O N ' T C A . R E

]*/"*."* ro zi

DUAL MONOSTABLE MULTIVIBRATOR

221

F U N C T I O N T A B I J E

X : D O NtRdcx

lCx

T CA-RE

2Q 2Q zCLR 28

I N P U T S O U T P U T S

CIJEAR BA c eL

HHH_f

x xH XX LL l :1 _ HI , H

! HL Hl r Hft 1rJL 1.r-rL 1r

DUAL RETRIGGERABLE MONOSTABLEV I BRATOR

4?3F U N C T l O N T A B , ] , E

MULTI .

X : D O Nlpt/cx

VCC f0x

CARE

ra Eb2CLR

I N P U T S O U T P U T S

1B lcLR

DUAL RETRIGGERABLE MONOSTABLEV I BRATOR

4538F U N C T I O N T A B L E

MULTI .

X : DON T CAREaCD 2A?1I'r ztz

I N P U T S O U T P U T S

A B e , qIJH

HH

H

X XH XX L! J L

- f H

I , HL HI , HJt 1fJ L 1 r

25

MULT I PLEXER

DpcNumbcr Functlon

EquivdentLSTTL

EquivalontcMos.

PinItLmbcr

74HC405L74HC405274HC405374HlC4066

8-CHANNEL AI.IALOG MULTIPLEXERDUAI 4-CIHNNEI AIIALOG MULTIPLEXERTRIPLE 2-CIIANNEI AI.IAIOG MULTIPLEXERQUAD BII.ATEMI ST{ITCH

405L40524053

4016.4066

16t 61614

74rrc 15174HC 15374HC L5774HC 15874HC 25L74rrc 25374rrc 25774HC 258

74EC 29874HC 35474HC 356

8-CITANNEL MI'LTIPLEXERDUAI 4-CIIANNEL MULTIPLEXERQUAD 2-CHANNEL MULTTPLEXERQUAD 2-CIIANNEL MULTIPLEXER (II\VERTING8-CTIANNEL MULTIPLEXER (3-STATE)DUAL 4-CHAI{NEI MULTIPLEXER (3-STATE)

QUAD 2-CHANNEI MULTTPLEXER (3-SrArn)

QUAD 2-CHANNEI MUTTTPLEXER(3-STATE II\IVERTING)

QUAD 2-CHANNEL MULTIPTEXER/REGISTER8-CHANNEL MULT IPLEXER/ REGI STER8-CI{ANNEL MULTIPLEXER/ REGISTER

LS151rs153rsL57LS158rs25LLS253L5257

LS258LS298LS354LS356

{.45L24539

,c45L2,t4539

)t.45L2*45L2

16161516161616

16162Q20

r Suggcsted altcrnativc

MULTI PLEXER

8-CHANNEL MULTIPLEXER

l 5 l

D s ' c

D Z D l D 0 y w S

DUAL 4-CHANNEL MULTIPLEXER

1 5 3

vcc 20 A 3cg 2c? zcl 2c0

QUAD z-CHANNEL MULTIPLEXER157 NONINVERTED DATA OUTPUTS

ffiEEvcc 4A 48 4Y gA 3B 3Y

O 4 A 4 8 4 Y 3 A 3 B

QUAD z-CHANNEL MULTIPLEXER.I58 INVERTED DATA OUTPUTS

2A 2S 2Y oND

vo ffi ar ls E g.A, ss

fA 18 lY 2A 28 2Y

26

MULTIpLEXER (Cont inued)

8-CHANNEL MULTTPLEXER (3-STATE)

251

D 4 D 5 D 6 D ? A B

D 3 c

D2 D], DO Y ]Y ST

DUAL 4-CHANNEL MULTTPLEXER (3-STATE)

253

vcc 2G A zcs 2c2 ?cI ?c0

QUAD z-CHANNEL MULTTPLEXER (3-STATE)

257 NONINVERTED DATA OUTPUTS

SELECT IA ?A 2B 8Y OND

3A

oE 4A 48 4y 3A gB

s 3 Y

1A 1B lY 2A ?B 2Y

QUAD z-CNANNEL MULTTPLEXER (3-STATE)

258 INVERTED DATA OUTPUTS

OE 4A 48 4Y gA 3B

S 3 Y

IA 1B ]Y ?A 2B ?Y

QUAD z.CHANNEL MULTIPLEXERS WITHOUTPUT REGISTER

298

IXORDSELECT

lm aA aB Qc qP 6-Locx cl

A Q B Q C ( D C K I [ s

2 C I

A2 AT BI C2 D2 D]

D2

B.CHANNEL MULTIPLEXER WITH LATCH( 3-srATE )

354

ef

Y w oS 02 01 so s1s2

m s c

D 6 F D 4 B D 2 D l D O D C

27

MULTIPLEXER (Cont inued)

8-CHANNEL MULTIPLEXER WITH FLIP-FLOP( 3-STATE )

356

S2

ED6

Y w 0 3 G 2 G - t S O S l S 2

F D5 D4 D3 D2 D]. DO CK

B-CHA.NNEL ANALOG MULTIPLEXER4051

CONTROL

/+v c c z 7 0 3 A B C

+ 6 C O l , { O N 7 5y'o , * rB IT t *

2 7 0 3 A B

? o I l : H

DUAL 4-CHANNEL ANALOG MULTIPLEXER

4052

COI\mROL

vcc zx rx col9oN ox sx ?-

Ix co{-x ox 3x

OY

2Y CO,r-y gy fy 1NH

TRIPLE z-CHANNEL ANALOG MULTIPLEXER

4053

12 col"4,,tct'l oz it'tHlgttwE

ccDd-Y coM-x l-x ox A B

I Y C

o Y 1 Z ^ ^ - . _ o ZUr rr-1r I NH

QUAD BILATERAL SWITCH

4066

tv'o tq,/t zo/r zy'o

28

C O U N T E RTypeNumbet Function

EquivalentLSTTL

E'Cuir.'alent

civlus.PinNumber

74HC 16174HC L6374HC LgL74HC 19374HC 39374HC 59074HC 59274HC 59374HC 69L74HC 69374HC 6977 4HC 69974HC4520

SYNC. BINARY COUNTER WITH ASYNC. CLEARSYNC. BINARY COUNTER WITH SYNC. CLEAR4-BIT BINARY UP/DOWN COUNTERSYNC. UP/DOWN BINARY COUNTERDUAL BINARY COUNTER8-BIT BINARY COUNTER/REGISTER (3-STATE)8-BIT REGISTER/BINARY COUNTER8-BIT REGISTER/BINARY COUNTER (3-STATE)4.BIT BINARY COUNTER REGISTER (3-STATE)4-BIT BINARY COUNTER REGISTER (3-STATE)U/D 4-BIT BINARY CTR.IREGISTER(3-STATE)U/D 4-BIT BINARY CTR. /REGISTER(3-STATE)DUAL 4-BIT BINARY COUNTER

LS161ALS163ALS191LS193LS393rs590LS592rs593LS691LS693LS697LS699

4016140 r63*451640193*1+520

4520

1 6161616L416162020202020L6

74HC 1607 4rrc 16274HC L9O74HC L9274HC 39074HC 69074HC 69274HC 69674HC 6987 4HC45L8

SYNC. DECADE COUNTER WITH ASYNC. CLEARSYNC. DECADE COUNTER WITH SYNC. CLEARBCD UP/DOWN COUNTERSYNC. UP/DOWN DECADE COUNTERDUAL DECADE COUNTERDECADE COUNTER REGISTER (3-STATE)DECADE COUNTER REGISTER (3-STATE)u/D DECADE COUNTER/nrCrSrrn (3-Sretn)U/D DECADE COUNTER/REGISTER (3-STATE)DUAL DECADE COUNTER

LS162ALS19OLS192LS39OLS69OL5692LS696LS698

OA6LS1 4015040L62*451040L92

4518

161 61616162020202016

74HC40L774He402074HC402274HC402474HC404074HC406074HC40L0274HC40L0374HC729274HC7294

DECADE COIJNTER/DIVIDERl4-STAGE BINARY COUNTEROCTAL COUNTER/DIVIDER.7-STAGE BINARY COI]NTER12-STAGE BINARY COUNTER].4-STAGE BINARY COUNTER/OSCILLATORDUAL BCD PROGRA},IMABLE DOWN COUNTER8-BIT BINARY PROGM},IMABLE DOWN COUNTERPROGM},IMABLE DIVIDER/TIMERPROGM},IMABLE DIVIDER/ TIMER

*LS2g2*LSzg4

40L74020402240244040

40LO2401_03

1616r.6L416161616l_616

* Suggested alternative

COUNTER

PRESETTABLE

I 60 DECADE,I 6 l B I N A R Y ,

162 DECADE,

I 6 3 B I N A R Y ,

4 .BIT COUNTER

ASYNCHRONOUS CLEARASYNCHRONOUS CLEAR

SYNCHRONOUS CLEAR

SYNCHRONOUS CLEAR

sYN. 4 -BIT UP/DO" ,JN C0UNTER

1 90 BCD

I 9 I B I N A R Y

CLOCKCLEAR

C D EMEE GNDP

MAVfuIN

A cK RcoMNT LOAD CM I N

6 u

DOWN

QAWOA @ QC AD T

CL LOAD

c K A B C . D P

A B

29

COUNTER (Continued)

SYNC.1921 9 3

4-B ITBCD

BINARY

UP/DOWN COUNTER

Q/\ uouNDOml

colrNt ^^ QDUP VV

ar{ u ru( I ,^^* cBORROW LvAu

COI'NT DCOUNI UP

PROGRAMMABLE DIVI DER/TIMER

7292 FRoM 22 b 231

B E TPl cLKT T

CLKE

C D T P S C L R A

B

TP2

PROGRAMMALBE DIV IDER/TIMER

7?g4 FR0M 22 to 2I5

dffiF'NC

TP CLKICLK2

B A TP OIJ(ICLKSNC Q OND

DUAL DECADE COUNTER

390 (Br-QUINARY 0R BCD)

z-cl,deF fribcKB

ICLEAR

DUAL 4-BIT BINARY COUNTER

393

8-BIT BINARY COUNTER I^IITH OUTPUTREGTSTER (3-STATE)

590

vcc eA 6 ncncrrnx-coccdilLnnd6

OA e RoK ccK ccLRCCKEN

nP RCO

Qc aD @r aF aG arr

QO

30

COUNTER (Continued)

8-BIT BINARY COUNTER }IITH INPUTREGISTER

592

CI,(h,D CCKBNvc A RcK ccx

6-qnT6-o

A Rcr. Ccr

C D E F O E

8-BIT BII{ARY COUI{TER }IITH INPUTREGISTER (1,il'LTIPLEXED 3-STATE

oTJTPUTS)593

ffintrcrccf,pr COr g.n nE

A/eA c/ac E/aE q/@ aB/tts Qr'cD F/{OF H/@

e o,/ rcr crxgrf acr ocLRt l

rcf,Er IA c{xaN R0

v@ E&B q/@ cLm

SYNCHRoNoUS C0UNTERS/REGTSTER LTITHI'IIJLTIPLEXED 3-STATE OUTPUT

690 DECADE, DIRECT CLEAR691 BINARY, DIRECT CLEAR692 DECADE, SYNCHROI{OUS CLEAR693 BINARY, SYNCHRONOUS CLEAR

ENABI,B

A D TB/t

sBLngtRIPPLE

vccNqa en ec

RCO qA QB S QD BNT LOAD O

6 K A B c D E N p R t L R R c K

s YNC HRo]r0r,s u P/ Dollr{ cor,l{TERs/ REG r sTE R}IITH II'LTIPLEXED 3-STATE CI'TPUTS

696 DECADE, DIRECT CLEAR697 Btrt{ARY, DIRECT CLEAR698 DECADE, SYNCHR0]{0US CLEAR699 BINARY, SYNCHRONOI'S CLEAR

RIFPLFifrfrFi= W\EI^B ifr

vcc qA qB qc QD T E,m6.srragr

QA QB QC QD F| TI)AD

DECADE COUNTER/DIVIDER401 7

CARRY Q9 A{OUT

Or ao @ Ao qf, qg

I4-STAGE BINARY COUI{TER

4020

vcc au aro aB € ar*Anclc*-

Q8 q9 CtR Cx

QI2

Q13 Qrr A0 as (rt ar

QrS QIr a0 a5 qt a+ oND

3l

COUNTER (Cont inued)

OCTAL COUNTER/DIVIDER4022

urocr6IIEIE-

vcc oLEAR cr,ocr | %mt

CLR CK CE CARtrQ4 Q7OUT

Ql

eO Qz Q5 Q6 Qs

7-STAGE BINARY COUNTER

4024

CTOCK CLEAX Q?

Q] Q2 Q3

CK

.CLR Q? Q6 Q5 Q4

Iz-STAGE BINARY COUNTER4040

vcc ett eto eB e9 cluen cr,odn or

Q]l QlO Q8 Q9 CLR CK

Q]? Q f

Q6 Q5 qt Q4 Q3 Q2

I4.STAGE BINARY COUNTER/OSCILLATOR

4060

Q13 Q15 Q14 Q6 Q5

vcc q1O e8 e9

12 Q13 QI4 Q6 Q5 Q7 Q4

DUAL DECADE COUNTER

15.| BDUAL BINARY COUNTER4520

26 28 ?Ql zQo

PROGRAMMABLE DOL.JN COUNTER

4O1O? DUAL BCD4OI03 B-BIT BINARY

- Eonnvcc sPE

-- ' -12 J6

S P E J 7coy'o

c/cnCLR JO

APE

J 1 J 2 J 3

32

ENCODERTypeNumber Function

EquivalentLSTTL

EquivalentcMos.

PinNumber

7 4HC7 4HC

r47148

1O-TO-4 LINE PRIORITY ENCODER8-TO-3 LINE PRIORITY ENCODER

LS147LS148 *4532

L61 6

* SUGGESTED ALTERNATIVE

ENCODER

IO-TO-4 L INE PRIORITY ENCODER

147

B.TO-3 L INE PRIORITY ENCODER

1 4 8

OUTPUT INPI]TS OUTPUTA

OUTPUTS II ' IPUTS OUT?UT

\ 4 5 I ? 8__9 .___9-o l to

INPUTS OUTPUTS INPUTS OUTPUTS

D 3 2 T 9

5 6 7 8 C 8

C " S , 5 z i - 0

a A O

5 6 7 E l r A 2 A _ t

33

DECODE RTypeNumber Function

EquivalontLSTTL

EquivalentcMos.

PinNumber

74HC 4274HC L3t74HC L3774HCT13774HC 13874HCT13874HC 13974HC 15474HC 15574HC 23774HC 23874HC402874HC45L474HC4515

BCD TO DECIMAL-DECODER3-TO-8 LINE DECODER/LATCH3-TO-8 LINE DECODER/LATCH3-TO-8 LINE DECODER/LATCH3-TO-8 LINE DECODER3-TO-8 LINE DECODERDUAL 2-TO-4 LINE DECODER4-T0.16 LINE DECODERDUAL 2.TO-4 LINE DECODER3-TO-8 LINE DECODER/LATCH3.TO-8 LINE DECODERBCD-TO DECIMAL DECODER4-T0-16 LrNE DECODER/IATCH4-T0-16 LINE DECODER/IATCH

LS42LS131LS137LS137LS138LS138LS139LS154LS155

*LS154, ' tLS159*LS154, *LS159

*4028

4556, *4555'k4515

*4556, *4555

402845r44515

16161 616161616241616t51 62424

74HC4511

74HC4543

BCD TO 7 SEGMENT LlDID (LED)

BCD TO 7 SEGMENT LIDID (rCD)L S 4 7 . L S 4 8 . L S 4* ' * ' *L S 4 7 , L S 4 8 , L S 4

45114s43

161 6

t Suggestedalternative

DECODER

BCD TO DECIMAL DECODER

42

A B C D

YOYfY2!3 l4F]6 Y']B 19

Yo Y1 Ya vs it vs i6 QID

3.TO-B LINE DECODER/LATCHl 3 l

Y! Yl Y2 Y3 Y4 Y5

B C C K C l 2 0 1 r t

3-TO-8 LINE DECODER/LATCH

1 3 7

& o r

3-TO-8 LINE DECODTR1 3 8Tl 38

B C OQA O2B Cl Y'/

oEe oae or rr sxo

34

DECODER (Cont inued)

BCD451 I

TO SEGMENT LATCH/DECODER/DRI VER

! E a b o a l

O L T B I L E D A

4-TO-I6 LINE DECODER/LATCH

45.| 4

INHIBITvcc D c sto su s8 s9 slA sl5 sla sl3

Sz sO 85 s4 Sg S1 Sa SO orO

IMI D C Slo Su S8 89 gl4 St5 Sl2

A B V S 6 S S 4 S g S l S e S o

4-TO-16 LTNE DECODER/LATCH451 5

INHIBIT

INII. D O SI)S,1 S8 S9 SU, 815 Sl2

A B S ? S 6 8 E S 4 S . g S I S A S O

BCD.TO.7 SEGMENTDRIVER

4543

LATCH/DECODER/ LCD

f g 6 d o b

Lr' a

O B D A P I I B I

35

DECODER (Cont i nu6d)

DUAL1 3 9

2-T0.4 LINE DECODER

zYO 2Y1 tt? 2Y3

lYO lYL 1Y21Y3 oND

YO Y] Y? Y3

4-TO- I6 L INE DECODER. |54

S ? E E % F r F Y r E F t u o u

e2 0]Y15)14 flSYJzYl]

B C D @ elu5Y14u3

Y 2 1 6 Y 4 1 5 1 6 y / 1 8 ) B

DUAL 2-TO-4 LINE DECODER3-TO.B LINE DECODER. |55

f f iF -mzf r

1 c r-e frs 1E M. ffi eno

3-TO-B LINE DECODER/LATCH

237

YO Y I Y g Y4 Y 5 Y 6

Y O Y l Y 2 Y 3 Y 4 Y 5

3-TO-B LINE DECODTR

238

vcc Yo Yl Y2 Yg 14 Y5 Y6

A Y 6

B C E?A E?B Gl Y?

6Eq ifrB er Yl

BCD-TO-DECIMAL DECODER

4028

Y S Y l B C D A Y S

Y2 YO Y' I Y9 Y5 Y6

't4 Y 2 Y O Y 9 Y 5

36

COMPARATORTypeNumber Function

EquivalentLSTTL

EquivalentcMos.

PinNumber

74HC 8574HC 688

4-BIT MAGNITUDE COMPARATOR8-BrT EQUALTTY COMPARATOR

LS 85LS688

x4063, *4585 1620

* Suggested alternative

COMPARATOR

4-BIT MAGNITUDE COMPARATORB5

. v c c A S 8 2 A ? A 1 B f A o B o

ns <F r- Ds Ds F.e(pexo+

CASE,ADE INPI'TS OIITPUTS

ADDE R

B.BIT EQUALITY COMPARATOR

6BBv"6 F= Q Q' / P ' / Q6 P6 Q5 P5 QL P4

A 5 B 2 A ? A 1 8 1 - A O

B 3 B O

Ke l: DB DB rru,qGIIJ IN IN our. ou,r Offi

= Q Q 7 P 7 Q 6 P o Q 5 P s Q 4

e P 4

P o Q o P l Q f P e Q ? P 3 Q 3

TypeNumber Function

EquivalentLSTTL

EquivalentCMOS.

PinNumber

74HC 283 4.BIT BINARY FULL ADDER ts283 , LS83 4008 1 6

ADDER

4-BIT BINARY FULL ADDER

283

Bg AS Zs t+ s+ 2+

2z c4

Bz A? Jr et nr oo

37

ALUTYPClhmbcr

FunctionEquivdentISTTL

EquivalentcMos.

Pinlfumber

74HC7Atrc

181182

ARITII}IETICLOOK AIIEAI)

LOGIC ITNITCARRY LOGIC

LS181LSl82

2416

ALU

ARITM.IETIC LOGIC UNIT/FUNCTIONGENERATOR

LOCK AHEAD CARRY GENEMTOR

l82r8l *: OPFI DRAIN CT'TPITT

v* Fa o? cnGu+r&+y-o c.."

B-o fr ss sa sr so ca n rT F-t F? oro

ff s:I A-a ila e-s Fs d crn++ i ril eT

A O s g S ? $ 1 S O c D I F O F I F ?

pe o? cn culr(bry o

P } O O P O O S P S P

ol pl oo po og pg p (}rD

PAR I TY TREETypelrlumbcr

FunctionEquivdentI.STTL

EquivalentcMos.

PinNumbcr

74HC280 9-BIT PARITY GENERATOR/CIIECKER LS28O *4531 14

* Suggested alternative

PARITY TREE

9-BIT oDD/EVEN PARITY GENERAToR/CHECKER

280Y @ F E I T c B A

F B D C B

&%-*

38

LATCHTYFf.Iumbcr

Rmtio EquinhotISTTL

nquinlcntcuos.

Plnl{umber

74HC 7574EC 7774HC 25974HC 27974EC 375

4-BTT TTYPE I.ATTE4.BIT IFfi?E I.ATCII8-BIT ADI}RESSABI.E I.ATCNqIAD s-R'r,ATCHOUAI) IFTYPE I.ATCH

LS75LS77LS259LS279LS375

*4042*4042*4099

*4043,*4044

1614t616r 6

74nC 37374ncr37374EC 53374HC 56374HCT56374AC 57374HCT573

OCTAL IFTTPE I.ATGE (3-STATE)OCTAL IFTTPE I,ATSN (3-STATE)oimr. rFTrpE LATCH (3-srATE/rNV.)ocral, rFrIr"E r.arcH (3-STATE/rNV. )OCTAL IFIYPE I.ATCN (3-STATE/IN\I.)OCTAL IFTYPE IATCE (3-STATE)OCTAL IFTYPE I,ATCN (3-STATE)

rs373,LS573LS373,LS573

LS533LS563LS563

LS373,LS573LS373.LS573

202020202A2020

r $tgggstcd dbrnetivr

LATCH

4-BIT LATCH75

FUi l GT IO } I TABI ,E

X : D O N ' TCARE

+ qI Q 2 Q 2 q d t . z o r f ) S q 3 Q

I a I D ? D F 3 4 g D I D a Q

ITTPUTS OIITPT'TS

D o qcL EE SX L

L H

H I ,

an d-n

4-BIT LATCH

77F U T I C T I O I I TABI ,E

X:IX)NI T

CARE

tQ aQcl.a ( i lD xC sq 1 q

rD 2lrg3-ll Ycc sD aD l lc

IIIPT'TS OI'TPUTS

D G 0Q,

L SS EX L

L EE L

Q n G

8-BIT ADDRESSABLE LATCH

15s

ql Q2 q3 (xil)

qo (&@Q3 a*qss cr?

qrAD s-R LATCH279FI IUCTIOI I TABI ,E

* FOR IrATCEES TIlgDOUBLE F INTUTS:

rFH)Tts F TIrotSHIOE

IJ:OXE OT DOTIIIUPIITS I,OT

vo rE rF rq s32 sEr si sq

ITIPUTS OUTPUTRs a

u aL SH I ,r, I,

qnELs

rF rEr r& ro aF zE 8q tlrto

39

LATCH (Cont inued)

0CTAL LATCH (3-STATE)

373 NONINVERTED DATA OUTPUTS

T373

Dl" D 3

0CTAL LATCH (3-STATE)

533 INVERTED DATA OUTPUTS

QUAD LATCH

375

2 Q <u ' D

0crAL LATCH (3-STATE)

563 INVERTED DATA OUTPUTS

T563

2

& o 3 o ? 0 5 ' F . o ?

OCTAL LATCH (3-STATE)

573 NONINVERTED DATA OI, ITPUTS

T573

40

REG I STERTYpeNumber

FunctionEquivalentLSTTL

EquivalentCMOS.

PinNumber

74HC L6474HC L6574HC L6674HC L7374HC L9474HC L9574HC 29974HC 32374HC 59574HC 59774HC 67074HC4094

8-BIT SIPO SHIFT REGISTER8-B IT P ISO SHIFT REGISTER8-B IT P ISO SHIFT REGISTER

QUAD D-TYPE REGISTER (3-STATE)

4-BIT PIPO SHIFT REGISTER4-BIT PIPO SHIFT REGISTER8-BIT PIPO SHIFT REGISTER8-BIT PIPO SHIFT REGISTER8.BIT SHIFT REGISTER/LATCH (3-STATE)

8-BIT LATCH/SHIFT REGISTER4 I^IORD X 4-BIT REGISTER FILE(3-STATE)8-BIT SIPO SHIFT REGISTER/LATCH

(3.STATE)

LST64LS165LS166L5173LS194ALS195AL5299LS323LS595LS597LS67O

*403414014 , *402Lk4014,x402L

407 64OL94, ,k40104

*4035ik4034*4034

4094

T4L 6I 6L61616202016L616

L6

* Suggestedalternative

REGISTER

8-BIT SERIAL- IN/PARALLEL OUT SHIFTREGISTER

164

Vcc AJ{ QC QF QE CLEAR CIIJCX

QH QG QF QE

c,1{

B Q A Q B A O O !

8-BIT PARALLEL-IN/SERIAL-OUT SHIFTREGISTER

1 6 5

cLoct(v"gINHIBIt o

SERIALINPUT

CKINH

{rclK

D C B A S I

ofi

E F G H O H

B.BIT PARALLEL- IN/SERIAL-OUT SHIFTREGISTER

1 6 6

SEIVvcc-foAD H en o F Eeffi-

SERIALI N

H Q H C F E

SI CLR

CK CKA B c D I N H .

CLOCK CNDINH. CIOCK

QUAD D FLIP-FLOP (3-STATE)

1 7 3

DATA EbIABI,EINPUTS

vcccLEAR ].D ?D 3D 4D & (}1

oIJEA.R lD 2D 3D 4D

4Q CI.0CK or.rD

41

REGISTER (Cont inued)

4-BIT BIDIRECTIONALREGISTER

I 9 4

UNIVERSAL SHIFT

CLEARSHIIIIRIOilT

D SHIFT Cil[DLEFT

qA QB QC Ou

"_*

tl

CLEAR SO

S R A B C D S L

4-BIT PARALLEL- I N/PARALLEL-OUTREGISTER

1 9 5

SHIFT

QA eB ec QD 0D oK

gLEAR 6

J K A B C D

8-BIT BIDIRECTIONAL UNIVERSAL SHIFTREGTSTER (3-STATE)

299 DIRECT CLEAR323 SYNCHRONOUS CLEAR

sHIFr ' '{qo^'^^cIocr flf[ffivcc st LEFT e,, ty'on{a{ --/w----

.g--&rsloo {qe , r/o.l or'sm oNoOIITPUT VACCONTROLS

s] sL aH' ly'av nlatroo{as cr

so sR

s s/qo daadqc/a^a^' aL

8.BIT SHIFT REGISTER/LATCH (3-STATE)

595

SCLRvCC eA SI

-O nCr SCX OH/

QA sI o RcK ScK scLF

a

QO QD QE QF' QG QH

QB

8-BIT LATCH/SHIFT REGISTER

597

SLOADRCK $(:KSCLR OH.

A sI sLoADRcK scK SclJt

B Q H ,

C D E F O H

4 WORD670

BIT REGISTER FILE(3-STATE)

WRITESELECiI ENABLE ouTpUTs

DAfA.-r-D1 wa wBmIffiRffi af aPvcc

Dl W.e, WB Ow OR Q1

m a z

B , D 4 R B R 6 Q 4 O g

D 2 D 5 D 4 R B . R A Q 4 Q 3-

, - t

42

REGISTER (Continued)

8-BrT SERIAL IN/PARALLEL-0uT SHIFTREGTSTER/LATCH (3-STATE)

4094

oE q5 Q6 q? Q8 Qsl

8T QS

r o K Q r Q z 0 S A r

ou)G gr qa q3 qa (x|D

43

3. OUTLINE OF PRODUCTS

3.1 Naming Method of TC74HC Ser ies

TC74HC Ser ies was named by the Standard naming method of JEDEC.

Its formal type number i-s as shor^rn below.

(Example) rcz+ttcT24OF

High speed C2UOS IC which is p in and funct iona l ly compat ib le

wi th the b ipo lar 74LS24O dev ice.

Input is des igned wi th TTL leve1, and d i rect dr iv ing f rom

LSTTL i s poss ib l e .'

Package type is plast ic l l ini Flat Package.

(1 ) Hc , Hcu , HCT

In the high speed CIvlOS, HC series, there are HCU type and HCT

type beside the fundamental HC type. These sections l^/ere decided

by JEDEC in order d prevent the d i f ference i -n e lect r ica l

per formance produced by input leve l and ex is tence of buf fer even

in t he case o f CMOS o f same func t i on .

TC7 4

( 5 ) 0 the r sec t i ons

(4) Sect ions for Package type( P o r F )

(3) Change contrr.r l symbol (blankwhen there is no change. )

(2) F igures showing funct ions

( f ) Type c l ass i f i ca t i on by JEDEC.(HC, HCU, HCT)

44

TyPe In terna l s tageInput thresholdvol tage

HC

HCU

HCT

T\ro stages andabove

One stage

T\^ro stages andabove

CMOS level

CMOS 1evel

TTL level

Taking inverter as an exampl-er w€ can show the dif ference of

these types as fo11ows.

(2 ) C lass i f i ca t i on o f f unc t i ons

Funct ions are expressed by Engl ish numera ls o f two to f ive , f igures.

In the case of TC74HC Series, there are provided the product

having same pin connecti-on and function with LSTTL, and the

product hav ing same p in connect ion and f r :nc t ion wi th 40008/45008

ser ies o f s tandard CD' IOS.

00 n,999 Product o f sanp p i -n connect ion and same

funct ion wi th 74LS ser ies

(Example) 74L5240 <--+ 74HC24O

TC74HCO4 TC74HCUO4 TC7 4HCTO4

Logic Di-agram w -+"- wInput -Output

Vol tagetransfercharacter -i s t i c s

Erir

?I

2.5V

vr l l

45

4OOOq4O199 . ... Product of satp pin coanection and sane

4500{4599 frnction with standard C}I)S 4ffiOB/45OOB series.

(Erample) 401028 .-* 74EG4Q!O?

TOOO 7999 .. .. . Frnction proper to 74HC series. Eouever, sorc

function approaches ISTIT,.

(Exemple) Sam fincElon yith 748C7266 ++ 74LS266.

Eoryener, output is of nornal buffer' structure.

(not open drain structure.)

(3) Change control symbol

Ttris syfrol is given to clarify the rewision of product stren in-

proverent strLch sill remarkably change the characteristics of

product is "rade. Nornally, it is blank, but if there is a chauge,

hglish characters are given successively from A.

(4) Partitiou for package designator

English characters shorring type of package.

P . . . . . . . dual ln l ine package (DIp) plast ic

F . - .. .. . nini flat package (l,FP) plastic

In 1f,748C series, arrow 3fi) nil-l type 24 pfn..package nas

newly developed. By this development, in' the case of rrprt

tyPe, l4lf:6l20l24lpil;s are all unified into 300 nill Eidrh

(7 .62 rm width) .

Alsor'in the case of mini flat "Ft' type , L4lL6l20 pins are all

uaified iito ErA"r 30o nil1 type package (TypE I[, Form A).

46

rn the case of both DIP and MFP types, pin arrangement of samewidth and sarr= pitch is adopted regardless of pin nrrmberr andso i t is possible to arrange the parts systemat ical ly whendesigning the printed boJrd, and automatic rnor.rnting can beeasi ly made.

(5) Other part i t ions

In the case of mini f lat IC Taping specification, the followlngindicat ion is added to the parts name.

fPl or - W2 (Di f ference in st icking direct ion)

3-2. Features

Tg74HC Series has the following features in conparlson with otherstandard Logic IC;

(1) Hlgh Speed operat ion : Same as LSTTL

(2) Low Power Dissipat ion: Same as standard CInCS ser ies (ut{)

(3) Output Dr ive Capabi l i ty :Capable of d i rect ly dr iv ing 10 LSTTL

loads (Standard output type).

Capable of directly driving 15 TSTTL

loads (Buffer butput rype).

(4) High Noise Immunity : HC /nCU Type . . . 45y" VCC (Typ.)

HCT Type . . . . . 25% VCC (Typ. )

(5) Wide Operating Vulrage Range i t

HC/HCU Type . . . 2 to 6V

H C T T y p e . . . o . , 4 . 5 t o 5 . 5 V

(6) tl ide operating Temperature Range z -40 to *g5oc

47

( 7 ) Se l f - con ta i - ned s ta t i c e l ec t r i c i t y p ro tec t i ve c i r cu i t :

+2000V (min) (All inputs and Outputs)

by EIAJ method

(8) Ample Latch up Capaci ty : Tota l input a70mA and above (Rest r ic ted

by i npu t p ro tec t i ve res i - s tance )

Total output +300 mA and above.

(9) Based on the same pin connection and function with LSTTT..

(10) Wide L ine up, and products amount ing to 180 k inds.

Table 3-1 shows compari-son of characterist ics of various logic

fami l i -es .

Table 3-1 Performance Comparlson of Each Loglc Famlly

ParamterHS-Cal,os

(rc74rrc)' s e r l e sLSTTL

HS-C2l0S

(1'C40H )' se r t esc2los Condit ion

Propagation delay t imeGAIE (C1=15PF) SnstYP 9ns typ 15ns tYP 1 25ns t lp vDD = 5.ov

Ta = 25"CMaxlmum clock freqencyJ /K r 'F (C1=5Op ; 60t'ctztYP 4SwtztyP 201'fiztYP zyftlztyp

QuiescenE Supply Current(GAIE) 0.01uWtYP SmI^ItYP 0.01uwtvP 0.01uWtYP

Total temperature voltagerange

Input Vol tageVIH 3.5Vmin 2.OVmin 4.OVmin 3.SVrn in vDn=5.0v

vtl 1 .5Vmax 0.8Vmax I .0Vmax 1 .5Vmax Total temperature range

48

ParameterHS-CzMOS

(rc71Hc)aer1-es

LSTII.HS-CzMOS

/TC40H \t se r i es 'CzMoS Condit ion

Output CurrentlronI 46min*l 6.4,,,4min*2 0.36nrAmin*36.12r4nin*3

*1 Vcc=4.5V*2 YcC=4.75Y*3 V6g=5Y

Total temper-ature range

rot 4611min 4r6min g.gnxlmin g.36o,4min

Operating Voltage Range 2 " v 6 y 4 .7 5q '5 .25Y 2 ' r ,8V 3 ̂ , 18V

Operating TemperatureRange

-40 ,r, 85 "C 0, r , 70"C -40 'r, 85 "C -40^85 "C

4. EXPLANATIONS OF RATINGS AND STANDARDS

4-I. Maximum Ratings

Regarding C MOS IC, the maximum Rating is regulated for each

p r o d u c t .

In general, the rnaximum rating value should not be exceeded in

order to guaranlee the l i fe and rel iabi l i ty of integrated circui t

products. Here is adopted the not ion of absolute maximum rat ing

as the maximuur rating.

Absolute Maximum Rating should not be exceeded even for a rnoment,

and any one standard of rat ings should not be exceeded.

When the unit is used in excess of the maximum rating, the

characterist ic wi l l nbt recover sonptimes, and in an extreme case,

permanent breakage wil l be caused.

In des ign ing the c i rcu i t , therefore, i t i s necessary to pay at -

tent ion to the f luc tuat ion o f supply vo l tage, character is t ics o f

connecting parts, ambient temperature, and surge of input and out-

put siganl l iner so that the maximum rating not be exceeded.

49

Table 4-I indicates cormron rnaximum ratings of TC74HC series.

When the maximum rating of each unit and common rat ing dif fer,

the former sha l l cont ro l . As for the meaning of each i tem,

. re fer to Table 4-2.

Table 4-L Absolute Maximum Rating

Pararne ter Symbol Value Unit

Supply Voltage Range vcc - 0 .5 t ' J V

DC Input Voltage vtu -0 .5 ' ' , VCC + 0.5 V

DC Output Voltage vout -0 .5 ' \ , VCC + 0.5 V

Input Diode Current rrk +20 mA

Output Diode Current rot< +20 mA

DC Output Current rout +25 (Standard)+35 (Buf f er) mA

DC VCC/GND Current rcc +50 (Standard)Tzd (Buf fer)

mA

Power Diss ipat ion Pps00 (D IP) *180 (IfrP) m['l

Storage TemPerature Tstc -65 ^, 150 O C

Lead Temperature (10sec) Tf 300 oc

* 5 0 0 m W i n t h e r a n g e o f T a = 4 0 o C T , 6 5 o C . I n t h e r a n g e o f T a = 6 5 ' C

to 85"C, derat ing fac tor o f -10mW/"C shal l be appl ied unt i l 300mt l .

50

a

Table 4-2

Pararneter Symbol Explanation

Supply Voltage vcc

the voltage range in which IC does

breakage, deter iora t j -on o f character -

fa l l 'o f re l iab i l i ty when vo l tage is

on Vgg termi-nal.

Ind icates

not cause

is t ics and

impressed

DC InpuntVoltage

DC OutputVoltage

Vttt

vout

the voltage range in which IC does

breakage, deteriorat ion- of character-

fa l1 o f re l iab i l i ty when vo l tage is

on input and output terminals.

Ind icates

not cause

i s t i c s and

impressed

Input

Diode Current

Output

Diode Current

rtx

ror

Ind icates the cur rent va lue at which IC does

not cause breakage due to latch up when input

current or output cur rent is fed.

* Pract ica l ly , the des ign in which DC current

f lows is not recomnendable. When f low of cur-

rent cannot be prevented, adopt the ctrrrent

va lue lower than th is .

DC Output

Current

Vgg/Gl.Io Current

rout

rcc

Output current indicates the current value which

can be f ed f o r one ou tpu t .

As VCC/CIUO current includes output current, in

the case of IC having rnany output terminals,

substant ia l output cur rent is cont ro l led by i t .

PowerDiss ipat ion

Pp

Indicates consumption power not causing break-

age of IC in the entire operating temperature

range

51

Parameter Sumbol Explanation

Storage

TemperatureTs tg

Indicates the ambient temperature range not

caus ing deter iora t ion o f character i -s t ic and fa l l

o f re l iab i l i ty when le f t for a long t ime in the

state not impressed wi th supply vo l tage.

Load Temper-

ature TimeT1 Ind icates the condi t ions when so lder i -ng is car -

r ied out a f ter IC is mounted on pr in ted board.

4-2. Reconrnended Operat ing Condi t ions

This is the range in which the operat ion o f 74HC ser ies is

guaranteed, and when th is range is exceeded, the operat ion is

not guaranteed even i f i t is within the maximum rating of 4-I.

Cornmon recommended operating condit i-on of 74HC seri,es is shown

in Table 4-3. When recommended operat ing condi t ion o f each un i t

and common reconmended operat ing condi t i -on d i f fers , the former

shal l cont ro l . As for the meaning of each i tem, re fer to Table

4 - 4 .

Table 4-3 Common Recommended Operating Condit ion

(a) 74HC Type

Parameter Symbol L im i t Unit

Supply Vol tage vcc 2 c ' 6 V

Input Vol tage vtu 0 ^, VCC V

Output Vol tage vout 0 n, VCC V

Operating Temperature Topr -40 tu 85 oc

Input Rise and Fal1 T imet r r t f 0q,1000 (VCC=2.0V)

0 'v 500 (VCC=4.5V)0n, 400 (VCC=6.0V)

N S

52

(b) 74HCT Type

Parameter Symbol L im i t Uni t

Supp l y Vo l t age vcc 4 . 5 t u 5 . 5 V

Input Vol tage vtu O T V C C V

Outpu t Vo l t a te Vout O .u VCC V

Operat ing Temperature Topr -40 tu 85 . C

Input Rise and Fal l ing T ime tr tf 0 t u 5 0 0 ns

Table 4-4

Parameter Symbol Explanat ion

Supply Vol tage Vcc Ind icates supply vo l tage range guarantee ing

no rma l t heo re t i ca l ope ra t i on o f IC .

Input Vol tage

Ou tpu t Vo l t age

vrnVout

Ind icates vo l tage range guarantee ing normal

t heo re t i ca l ope ra t i on and e lec t r i c cha rac -

t e r i s t i c o f I C .

0pe ra t i ng Tempera tu re Topr

Ind icates operat ing temperature range guar-

antee ing normal theoret ica l operat ion and

elec t r i .c charac ter is t ic o f IC .

Input Rise and Fal l

Time

( ,uInd icates r is ing and fa l l ing t ime range of

i npu t s i gna l no t caus ing ma l f unc t i on due t o

o s c i l l a t i o n o f o u t o u t .

53

4-3 . DC charac ter is t i cs

Table 4-5 shows DC characterist ics of HC Type. As for the meaning

of each i tem, re fer to Table 4-7. Table 4-5 is a s tandard DC

character is t ics Tab1e, and when i t d i f fers f rom ind iv idua l

character is t ic , the la t ter sha1l cont ro l . DC character is t ics is

regula ted by JEDEC ( In ternat iona l s tandards) . In TC74HC ser ies ,

al l units satisfy this international standard value, and some items(guarantee the character is t ics surpass ing the in ternat iona l

s tandards. Table 4-6 ind icates character is t ics Table s tandard ized

by JEDEC.

Table 4-5 TC74HC Ser ies DC Character is t ics Table

DC E lec t r i ca l cha rac te r i s t i c s

Parameter Symbol Test Condi t i -on t; Ta = 25"C Ta=-40tu85 "CUnit

M I N . T Y P . },IAX. M I N . MAX.

High-1eve1

Input Vol tagevtH

2 . 0

4 . 5

6 . 0

1 . 5

3 . 1 5

4 . 2

1 . 5

3 . 1 5

4 . 2

V

**Low-leve1

Input Vol tagevtt

2 . 0

4 . 5

6 . 0

0 . 5

1 . 3 5

1 . 8

0 . 5

1 . 3 5

1 . 8

V

**High-leve1

Output Vol tagevoH vrN=

V1g orvtl

roH=-2ouA2 . 0

4 . 5

6 . 0

1 . 9

4 . 4

5 . 9

2 . O

4 . 5

6 . 0

, 1 . 9

4 . 4

s . 9V

I8fi::19;A*

4 . 5

6 . 0

4 . 1 8

s . 6 8

4 .3 r5 . 8 0

4 . L 3

s .63

** Low-level

Output Vol tage VolvrN=

VIH orVtt

rol=2ouA2 . O

4 . 5

6 . 0

0 . 0

0 . 0

0 . 0

0 . 1

0 . 1

0 . 1

0 . 1

0 . 1

0 . 1V161={41*

IOL=5 .2mAtr4 . 5

6 . 0

o. r70 . 1 8

0 2 6

0 . 2 6

0 33

0 . 3 3

54

Parameter Symbol Tesr Condir ion I uaa

Ta = 25"C Ta=-40.r85"CUnitM I N . TYP. MAX. M I N . MAX.

3 Sta te Output0 f f -s ta teCurrent

rozVIN = V1g or Vf l

vour=vcc or GND6 . 0 { . 5 + 5 . 0

uA

Input LeakageCur ren t

r tu VIN = VCC or GND 6 . 0 -rc.1 + 1 . 0

**Quiescent

Supply Currentrcc

vrN =

VCC or cND

GATE 6 . 0 1 . 0 1 0 . 0

FF 6 . 0 2 . 0 20 .o

MSI 6 . 0 4 . 0 4 0 . 0

Note ) * Bu f f e r Type assumes 1 .5 t imes va lue , r espec t i ve l y .

( l r O H | = I O L = 6 d , 7 . 8 m A )

** I tems guarantee ing the character is t ics surpass ing JEDEC standards.

Table 4-6 JEDEC Standard No. 7A

DC E lec t r i ca l cha rac te r i s t i c s

Parameter Symbol T e s E C o n d i t i o n VccTa = 25"C Ta=-40185 "C Uni tM I N . TYP. MAX. MIN. MAX.

High-1evel

Input Vol tagevtH

2 . 0

4 . 5

6 . 0

1 . 5

3 .1s

4 .2

1 . 5

3 . 1 5

4 . 2

V

Low- leve1

Input Vol tageVtl

2 . 0

4 . 5

6 . 0

0 . 3

0 . 9

r .2

0 . 3

0 . 9

L . 2

V

High-leve1

Ou tpu t Vo l t ageVoH vrN=

V1g or

Vtl

roH=-2ouA2 . 0

4 . 5

6 . 0

1 . 9

4 . 4

5 . 9

1 . 9

4 . 4

5 . 9 V

IOH=-4mA*

IoH=-52mA*

4 . 5

6 . 0

3 . 9 8

s .483 . 8 4

5 . 3 4

55

Parameter Symbol Test Condi t ionvcc

Ta = 25oC Ta=-40-85tUnit

M I N . TYP. IqAX. M I N . MAX.

Low- leve l

Ou tpu t Vo l tage vor,VrN=

V1g or V11

rol=2oue2 . 0

4 . 5

6 . 0

0 . 1

0 . 1

0 . 1

0 . 1

0 . 1

0 . 1 V

I91=(nxtr*

IOL=5.2mA*

4 . s

6 . 00.26

0.26

0.33

0.33'-BF?:?"!;'n"t

Currentroz VIN = V1g o r V11

VOUT= Vgg or GND6 . 0 ] { . 5 + 5 . 0

UA

I npu t l eakageC u r r e n t I tlt VIN = VCC Or GND 6 . 0 - t { .1 + 1 . 0

Q u i e s c e n t

S u p p l y C u r r e n tIcc

T/GATE- 6 . 0 2 . 0 2 0 . 0

V66 or GNDFF 6 . 0 4 . 0 4 0 . 0M S I 6 . 0 8 . 0 8 0 . 0

N o t e ) *

Tab le 4 -7

Buffer Type assumes

( l r O H l = I o l = 6 m A ,

1 .5 t imes va lue , r espec t i ve l y .

7 . 8 m A )

Parame te r Symbol Explana t ion

H igh l eve l

I npu t

Vo l t age

T h i s i s a n i n p u t v o l t a g e c a p a b l e o f j u d g i n g i n p u to f IC as r rH r t l eve l , and t he m in imuu va lue i sgua ran teed . Judgemen t i n t h i s case i s made bycon f i rm ing t ha t i t i s above t he p resc r i bed VOHwhen ou tpu t vo l t age shou ld be a t r r 11 i l l eve l , andbe low the p resc r i bed Vg1 when ou tpu t vo l t age

s h o u l d b e a t ' r l ' t 1 e v e 1 .

56

Parameter Symbol Explanation

Low 1eve1

Input

Vol tage

vtt, This is an i -nput vo l tage capable o f judg ing input

of IC as t 'Ltt level, and the maxi-mum value is

guqranteed. In th i ls case, the judg ing method is

sarrn as VIH.

High 1evel

Output

Vo1 tage

voH This is an output voltage when each input ter-

minal is connected to VtH or Vtf, so that the out-

put leve l becomes r rg f r . In th is case, there is

guaranteed the min imum va lue of output vo l tage

obta inable when the spec i f ied output cur rent

( IO t t ) i s f l own ou t .

Low level

Output

Vol tage

Vol This is an output vo l tage when each input

nal is connected to V1g or V11 so that the

1eve l becomes r r l . r r . I n t h i s case , t he re i s

anteed the minimum value of output voltage

ta i -nable when the spec i f ied output cur rent

is f lown in .

Lermi-

output

guar-

ob-

( rol,)

Input Current rtu This is the current f lowing in the input terminal

when the vo l tage is impressed on the input ter -

mina l o f IC. Norma1ly , th is cur rent is so smal l

that measurement is nnde with the maximum value

o f supp l y vo l t age .

3-s ta te

O u t p u t O f f -

leak Current

Toz leakage current f lowing in the output

when the output has become h igh imped-

the dev ice hav ing three s ta te output

o r open d ra in ou tpu t t e rm ina l .

This i-s a

termina l

ance , i n

termina l

57

Parameter Symbol Explanation

Quiescent

Supply

Current

rcc This is a current f lowing from vgg terminal into

IC when V6g or GND level is held without chang_

ing IC input, and the maximum value under al l

theoret ica l condi t ions a l lowable for measured rc

i s gua ran teed .

4 - 4 . A C C h a r a c t e r i s t i c s

AC character is t ics guarantees t rans ient character is t ic o f produts .

rn genera l , impressed input waveform is so set as to have

ampl i tude of vcc-cun leve l and r is ing and fa t l t ime of 6ns.

Table 4 '8 shows the meani .ng of each i tem of AC character is t ics ,

F ig . 4- I ind icates the output connect ion d iagram of measur ing

t ime , and F ig . 4 -2 i l l u s t ra tes t he measu red wave fo rm .

Table 4-8

Parame ter Symbol Explana t ionDrawing No.

Output

Rising Time

Output Fal1-

ing Time

trlH

TTHL

Ind icates the t ime dur ing which the out -

put vo l tage (VOl , VOH) r ises f rom L0% to

9O7", and the t ime during which the output

vo l tage fa l ls down f rom 90" / " to LOZ.

58

Parameter Symbol Explana t ionDrawins No.

HC HCT

Propaga t ion

Delay Time

tpLH

tpHL

Ind i ca tes t he de lay t ime , i . e . , a f t e r i n -

put signal is given and unti l output re-

sponse is made. tpLH is the case in which

the output changes f rom t r t r r r leve l to r r11t f

level, and tpHL is the case in which the

output changes f rom r rHr f leve l to 1 tL"

( 1 ) -

( i )

( 2 ) -

( i )

0utpu t d is -

able Time

tPLZ

tpHZ

I n d i c a t e s t h e d e l a y t i m e , i . e . , a f t e r a

s ignal is g iven to the output cont ro l t€r -

minal and unti l 3 state output becomes

high impedance s ta te . ( r ) -( i i i )

( 2 ) -

( i i i )

Output

Enable Time

t pzL

tpzH

I n d i c a t e s t h e d e l a y t i m e , i . e . , a f t e r

s igna l is g iven to the output cont ro l

termina l and unt i l 3 s ta te output be-

comes r t t r f r leve l or t tHt t leve l f rom the

h igh impedance s ta te .

Minimum

Set up

Time

t g Regard ing a cer ta in data, ind i -cates the

time in which the data must be added and

held , before the input regard ing that data

(c l ock i npu t , e t c . ) changes . Fo r i n -

s tance , when the da ta i s r ead i n a t a

r i se o f nex t c l ock pu l se , i t i s neces -

sary to add data before the r is ing o f

c l ock pu l se , max imum va lue o f t s .

( 1 ) -

( i i )

( 2 ) -

( i i )

Minimum Hold

Time

rh Regard ing a ce r ta i n da ta , i nd i ca tes t he

t ime in which the data must be he ld even

af ter the input regard ing that data

( c 1 o c k i n p u t , e t c . ) h a s t h a n g e d .

59

Parameter Symbol Explanation Drawing No.HC HCT

Minimum

Rernoval Time

t rem I nd i ca tes t he m in imum t ime , i . e . , a f t e r r e

leas ing of asynchronous input (cJ-ear , pre-

se t i npu t , e t c . ) and un t i l r ece i v i ng o f

nex t ope ra t i on i npu t ( c l ock , e t c . )

( 1 ) -

( i i )

( 2 ) -

( i i ;

Minimum

Pulse

I^Iidth

tw Indicates the minimum pulse width at which

i lock input , e tc . is accepted as a normal

s i gna l .

Max. Clock

Frequency

fuRx Ind icates a l imi t c lock f requency at which

IC carr ies out normal opera i ton.

Input

Capacitancectu

Ind icates the capac i ty between input and

GND.

Fig.4-1 Output Connect ion Diagram.

M e a e u r i n g

P o i n t

To. outputTe rm i na 1

i . i eaeur in r4P o r n t

i ' o ou tpu t

Te rm i na L

r'"CMOS Outpu t

To Ou tqu t

T e r m i n a f

Open Outpu t

M e a s u r i n s

P o i n t

contains the capacity

p r o b e , e t c .

vcc

TI

s1 J

Note) C1

o fR -- ' . L

TL

3 s t a t e

cL 1""

60

vcc

ou tpu t

F i g . 4 - 2

(1) HC

Switching Character ist i .cs Test l r laveform

TyPe

tTLH, tf iIL, tpLH, tpHLi . )

I NPUT

] N V E R T I N GC U T P U T

i i ) t w r t " ,

t , 1

C L O C K

INPUT

DATAINPUT

OUTPUT

t h , t r em

6 n s

vcc

GND

voH

6 n s

eo%o.%

vcc

C}ND

vcc

G N D

voit

vot

vcc

GND

50%

t t H l

SET , RESEToT PRESET

t 1 6 n s

90%50|/a

trul ro%

61

iii) tpLZ, tpl/.Zt tpL, tpZJ/.

t r 6 n e

CUTPUTDISABLE

OUTPUT: LOWTO OFF

n r t m n r r m i ' i i r n r rv U I r U l . - t : l - L \ t . r l

T O O F F

t 1 6 n sV n n

qND

v6H(4ss )

vor,

vott

v61(4No)

OUTPUTSENABIJED

(2) HCT Type

i) tTLH, ttttl, tpLH, tpHL

INPUT

INVERTING

OUTPUT

50%

f*PLZ

OUTPUTSDISABLED

t y 6 n s

62

i i ) twr t " t , thr t rem

CLCCKINPUT

DATAINPUT

OUTPUT

sET,RESETor PRESET

iii) tpLZ, tpHZ, tpZL, tpZll

t r 6 n g

OUTPUTDISABIJE

OUTPUT: IrOWTO OFF

OUTPUT:HIGHTO OFF

3.0v

GND

&ov

GND

von

vcl

&ov

GND

t1 ' 6ns

\pzr

tpzu

3V

GND

von(lvcc )

vor,

vott

Vol(:<cll l)

6 n s

t r r ( l )

tpul

OUTPUTS

63

OUTPUTS

5. How TO READ LOGIC SYMBOL AND TRUTH TABLE

5-1. How to read Logic Symbols

Tab le 5 -1 shows the bas i c l og i ca l b l ock used i n h i gh -speed CMOS

rc. The theoret ica l char t pr in ted in ind iv idua l technica l

da ta o f each p roduc t i s composed o f t he - bas i c b l ock shown i n

the t ab1e . Th i s l og i ca l cha r t i s based on M IL -STD-806B , and

c locked i nve r te r and t r ansm j - ss ion ga te . emp loy spec i f i c symbo l .

Tab le 5 -1 Bas i c Log i ca l C i r cu i t s

Log i c Symbo l Log i ca l Equa t i on o r T ru th Tab le

Inve r t e r A=>r B a--o)-n

NAND Gate f-D,'- c f; _D-c

$=Nn--c $ €-c

f i {F-c t _D*c

i -Dci-5o_c

C = A B = A * B

NOR Gate C = A * B = A

AND Gate A + B

A - . 8

X : D o n t t C a r e

Z z H i g hImpedance

6 A BH H L

H L H

L X Z

ClockedInver ter

( N o t e 1 )

. t d L d -a*fo B A --Xt t

A

AB

F-#F't 6

:fD-c

Transm iss ionGa te

( N o t e 2 )

X : D o n t t C a r e

Z z H i g hImpedance

6 A BH H HH L L

L X Z

EXCLUS IVE-ORGate C = ( A + B ) ( A + B )

64

Table 5-1 (Cont inued)

C i r cu i t Func t i on Logic Symbol Logical Equation or Truth Table

EXCLUSIVE-NORGate $ :1f>-. c = ( a . B ) + ( A . B )

D-Type

Fl ip Flopaa

X: DodtCare

A: NoChange

S R D CK aH L x X H

L H X X L

L L H -r H

L L L .r L

L L X -t-QnA

J/K Type

F l ip F lop

J

CKK

aJ- cKaK

xAV

Donr t Ca reNo ChangeToggle

S R J K CK aH L X X X H

L H X X X L

L L L L -|- qnA

L L L H _r L

L L H L -r H

L L H H _r QnvL L x X -l_

QnA

Note 1) Clocked Inverter

Clocked inverter ha3 the circuit shown in

F ig . 5 -1 . I n t h i s f i gu re , Q l and QZ a re

' P-channel MOS FET, and Q3 and Q4 are

ll-channel MOS FET, and four FET are all con-

nected in ser ies f rom Vg6 to GND.

-s o-1

I f 6 s igna l

oDr and can

composed of

i-s

be

Qz

at rr11rr level, Ql and Q4 turn

regarded as a mere inverter

and Q f .

vcc

" {

s*1

65

Fig. 5-1 Clocked Inver ter

When I s i gna l i - s a t rT , f t l eve l , bo th Q f and Q+ tu rn o f f , and

irrespective of the condit ion of A i-nput, the output B becomes

high impedance condit ion cut off from both Vgg and GND.

That is to ssy, c locked inver ter can be appl ied as a swi tch to

cu t o f f i npu t and ou tpu t ,

Note 2) Transmission Gate

Transmiss ion gate has the c i rcu i t shornrn in F ig . 5-2 . As shown

in this f igure, Ql is P channel MOS

FET and QZ i.s N channel I.OS FET, and

these are connected in para1 le1.

I f d s igna l is a t "H" leve l , both Qf rN ' /our

and QZ turn on, and a signal can be

given f rom e i ther d i rect ion. Fur ther ,

vcc z. l

Tn.

cuT,/lN

/ Gllr)

i f 6 s ignal is at t t l t t level , both Q1 Fig.5_2 Transmission Gateand QZ turn off , and a si-gnal cannot

b e p a s s e d .

5-2. How to Read Truth Table

Table 5-2 indicates the explanation of symbols described in

Truth Table.

Table 5-2

Synbol Explana tion

H High Level ( Ind icates s ta t ionary input or output leve l )

L Low Lerre l ( Ind icates s ta t ionary input or output leve l )

-J- Indicates leading edge changing from ft lrr to rt11rr.

66

Symbol Explana t ion

-1_Ind icates t ra i l ing edge changing f rom "Ht ' to t t l r t

X D o n r t c a r e ( n i t h e r t t H t t o r I t L r f )

z High impedance state

a . . . . h Inpu t l eve l o f s t a t i ona ry s ta te o f each i npu t o f A t o H .

QoLevel o f Q jus t before the rea l izat ion o f input condi t ionind icated in Truth Table .

Qn Leve l o f Q jus t be fore input t ing o f ac t i ve edge (Jor l_ l .

JL One t l l t t leve1 pu lse

Lf One t t l . t t l eve l pu lse

6. COMMON ELECTRICAL CHARACTERISTICS

6 -1 . Supp l y Cu r ren t Cha rac te r i s t i c s

(1) Qui -escent supply cur rent

In the case of CI '{OS, under the condit ion in which input is

f ixed at tT , t t or , t tHt ' leve l , e i ther N-channel FET or P-channel

FET turns o f f . For th is reason, the cur rent

fo l lowing f rom Vg6 to GND becomes on ly the reverse-d i rect ion

saturated current o f PN junct ion and the sur face leakage cur-

rent due to the s ta in o f ch ip sur face a lone, and becomes the

current o f less than severa l nA at room temperature.

(2 ) ope ra t i ng supp l y cu r ren t

The operating supply current of high speed CMOS fC can be

cons idered as the sum of the fo l lowing t ta t t and r rbr r .

67

rrafr The switching current to charge and discharge each

capacity added to the gate output when the gate in the

c i - rcu i t inc lud ing output buf fer makes invers ion.

tt6rt The through current f lowing when P-channel FET and

N-channel FET which eonsti tute gate during inversion t ime

turn on transi.ently at the same t ime.

When rise t ime and fa1l t ime of input signal are small (about

6 ns) r through current of gate is usually negl igibly small

in comparison with switching current. For the reason, the

operating supply current is governed by internal capacity of

IC And charg ing and d ischarg ing current o f load capac i ty .

By obta in ing the to ta l sum (Power Diss ipat i .on Capac i tance:CPD)

of the capacity connected as a load to the gate operating in

the c i - rcu i t , the mean operat ing supply cur rent can be dec ided

as f o l l ows :

IOO (opr . ) = f in .CpO.VCC ( 6 - 1 )

For . the invers ion of gate output f rom low leve l to h igh leve l ,

i t is necessary that the electr ic charge

corresponding to CI .VCC is suppl ied f rom

corresponds to the mean current to be

supplied from Vgg l ine to IC during that

pe r i od .

vcc

68

rn the actual rc, operating gate exists in plural number,and their respective load capacity and inversion frequencyare di f ferent. Therefore, operat lng supply current as rc isas fo l lows:

rno (opr) = VcC.lrrr.ar'

As fn is certainly ai.r i" ible by integer of input frequency( . f in1 , the gate operat ing wi th fn /m f requency can be cons ideredequiva lent ly as rhe capac i ty o f

+ .Hence, the above equation can be developed as

Ioo (opr) = VCC.f in . i C*

I m

rn equat ion (6-1), the f inal i tem is def ined as cpD.

Here, cpf and rcc (opr) are obrained by raking TC74Hc74pas an example- connection diagram at the measurementt ime is shown in F ig .6 , and i t i s assumed tha t 265t t lwas obtained in the measured rcc (opr) . rn th is case,CL = 0, and ICC is negl ig ib le.

Thus, from the aboveequa t ion,

^*_ rcc (opr . )UPD = @Tf fN

265 x 10-6E -

s ' (T;107

= 53 (pF)

f:] rrdHz

f

z

Cf,n

.trrt

CK

D

F i g . 6 - 1

69

Next, by VCC = 5V, f IN = 8MHz, CPD = 53pF ( t is ing gnly one

circui t ) , ICC (opr) at the t ime of load capaci ty Ctr =

50pF (Q output only) can be obtained as follows:

ICC (opr . ) = CpD'VCg ' f in * Ct r 'Vgg ' fOUT

= ( 5 3 x 1 0 - 1 t ) . 5 . ( 8 x 1 0 u ) + ( 5 0 x 1 0 - r 2 )

. 5 . ( 4 x 1 0 6 )

= 3 . I 2 ( m A )

As Cpp under standard operating condit ion is described in a

separate data sheet , operat ing supply cur rent can be ca lcu la ted

for each un i t separate ly .

However , in the spec i f ic appl icat ion such as crys ta l osc i l -

la t ion, i t becomes supply cur rent character is t ics cont ro l led

by through current, and the calculat ion result by Cpp cannot

be used .

6 -2 . Ou tpu t cu r ren t cha rac te r i s t i c s

The output cur rent character is t ics o f TC74HC ser ies can be

devided into standard type and buffer type.

IC of s tandard type is capable o f d i rect ly dr iv ing 10 LSTTL,

and gua ran tees VOO-VOU:0 .37V , VOL -<0 .33V i n t he en t i r e t emper -

a tu re range . A l so i i n bu f f e r t ype , i t i s poss ib l e t o d i r ec t l y

dri .ve 15 LSTTL under the same condit ions.

70

Fig. 6-2 shows the s tandard output cur rent character is t ics o f

each type when used at the supply vo l tage of 4 .5V.

F ig . 6-2 Standard Output Current Character i -s t ics

High leve l output cur rentcharacter is t ics

Low level output currentcharacter is t ics

TyPe

Low level output currentcharac ter ist ics

High leve l outputcharac ter is t ics

( i ) Standard

current

( f i ) Bu f fe r Type

o u t p u t v o f t o g e V g H - V g g ( V )- 3 - 2 . . 1 0

P ad <9 EH . v

. ^ ! E- I U . { / \

O F I

P

- 2 0 P 'P

o

- t n d- " 0 )

o_l

- 4 0 su

,.1

Ta:gb 'C( MIN. )

Ta:zb"dtyp. )

p ^ A Ac {

t v; J

5 . Y q . nC ) F

P

p 2 0FI

-to ] n

q)r-l

0 1 2 -IJow leve l ou tpu t

3 4 5v o l t o g e V o L ( V )

ta:?fc(TYP. )

1 a : g 5 l ( M I N . )

I i q h f e v e - l - o u t p u t v o f t o g e V o g V g g ( V )

0

. 1 0

2 0

. _ a n

P , ^i <o El r v

O H

P

P

-l0)

|-'

b0+'1a:2 5lQ( TYP VgC:45V

I e v e l - o u t p u t v o l - t o q e V g 1 ( V )

+ : {F E t nO v E "t F J

c) --

PJ o n

P

" 1 0-1c)> oo -

e1

F

'-l Low

ta:a s"C( t ..p )

1a:35'Q( MI N )

71

( t r to te) Sol id l ine shows s tan i lard character i .s t ics char t . In the

actual case, there is a variat ion depending uPon the

samples, and so, adopt the broken l ine and separete

standard va lues when making des ign.

When the structure of device is decided, the current f lowing

in MOS FET is determined by gate voltage V6g and voltage VDS

between source and dra in .

In the actua l IC, the gate vo l tage of output s tep IOS FET be-

comes nearly Vgg or GND level. The.refore, i f IVCSI = VCC is

considered, the fol lowing equation is real ized in r ion-

saturation zone3

. ros = ( 12 Vos (vcs - vr) -vos2l

I f , Vpg is made constant , IDS is propor t iona l to Vgg-V1.

satura tion' zorJle ,

I o S = f ( V C S . - Y y ) z

Thus, i t is proport ional ' to (VCC - VT)2

is the threshold voltage pfoper to I-{OS

v.a1ue of , about 0.7V in TC74HC ser ies.

In the

t

no t by _VDS . Here,

FET, and is set at

V1

a

Fig. 6-3 shows supply vol tage - output current character ist ics

of standard type output. This f igure indj-cates standard value.

Note that the var iat ion of output current at the t ime of low

supply voltage becomes large in comparison with that at the

t i m e o f 4 . 5 V

72

vgg-vsH (v)

5 4 3 2

tl

rlo

H

H

r.fo

H

Ta: 5t

3.r

vcc:2'ov

_2.5v =r v

l - 7;:r4.5

s,sv 'r

4.ov#I

v -1/7

I 45.OV (-

5.5V^/

/

6.OV

-10

-20

-30

-40

-50

-60

-10

6 - 3 .

- 0 L 2 3 4 5

vol, (v)

I g 1 C h a r a c t e r i e t i c s I g g C h a r a c t e r i e t i c s

Fig. 6-3 Standard Output Current Character ist ics

AC E lec t r i ca l Charac ter is t i cs

(1) Supply voltage dependence

Transient character ist ics of rc such as propagat io i i delay t ime

and maximum ope:ating frequency are determined by delay time

of inner gate or r ise t ime and fal l t ime of output buffer.

In terna l de lay is cons idered to be ch ie f ly due to in tepfa l e f fec t

o f on res is tance of MOS FET and load capac i ty , but as the

in terna l capac i ty does not remarkably depend upon supply

vo l tage, the dra in cur rent character is t ic o f MOS FET determines

the dependab i l i t y o f AC e lec t r i c cha rac te r i s t i c s on supp l y

vo l tage .

F ig . 6-4 shows the dependabi l i ty on supply vo l tage of propaga-

t ion de lay t ime i -n a representat ive gate IC.

Vg6:2.0V

73

\In JEDEC, the coef f ic ient o f dependabi l i ty on supply vo l tage

is dec ided as fo l lows as the s tandard. In the worst case,

adopt the broken l ine indicated in Fig . 6-4 which was made

on the basis of JEDEC standard.

Table 6-1 Calculat ion l lbthod of AC Standard Value

(excepting ft"tRX)

vcc Ta = 25"C Ta = -40 ' t ,85 "C

2 . 0

4 . 5

6 . 0

5 . 0 0 x

x0 . 8 5 X

5 . 0 0 Y

Y = 1 . 2 5 X

0 . 8 5 Y

Table 6-2 Calcu la t ion Method of fUeX Standard Value

vcc Ta = 25"C Ta = -40 n, 85 oC

2 . 0

4.s6 . 0

0 . 2 0 x

X

1 . 1 8 X

0 .20Y

Y = 0 . 8 0 X

1 . 1 8 Y

R

-l

d

o

4J< d z

-lCDtr

p < !

lrt \

I

\\

I

h.xa\ ts. _- - - -

I . t ,oint" ..roorro*ruur. cul

Fig.6-4 Dependabi l i ty on Supply Vol tage of Propagat ion Delay Time (Gate IC)

74

(2) Load capacitance dependence

rn TC74HC series, output current has been widely improved in

comparison with the conventional 40008/45008 series, and

""p""!.ty load can be driven at high speed.

Howeverr 4s output impedance is decided when supply voltage

is determined, r ise t ime and fal l t ime of output waveform,

or propagat ion de lay t ime wi l l increase in propor t ion to an

inc rease o f l oad capac i t ance .

F ig . 6-5 ind icates the load capac i tance dependence of output

r i se t ime and f a l 1 t ime a t supp l y vo l t age o f 4 .5V , wh i l e

F ig . 6-6 shows the load capac i tance dependence of propagat ion

de lay t ime .

Standard Type Buffer Type

Fig. 6-5 Load Capaci tance Dependence

of tTltt, TTIIL

(standard character ist ics)

3, zoFl

t-rP

d |T1

d t s4 J t o

Ut r q )

C0 .d.Fi Pii

U

q - uP F I

O q {0 5 0 1 0 0

Lood Capac i t y C f , ( pF )

EzoFl

F{p

s r €10d F

PU

. - l l

@ .'+.,-r Pl.

UP c 01 5 ' AF . : 0 5 0 1 0 0

i i Lood capac i t y cL (pF )U H

75

IDE.d

P

> oa l cO F I€ E !

Ag + to -..r !EP > l. t AQ PatAot{ft

Ioad. capactty rcT

(1,t)

Standard $pe Buffer Type

Fig. 6-6 Load Capacitance Dependence of tpLH' tpHL

(standard character ist ics) o

In TC74HC serLes, AC character is t ics o f 50pF dur ing load

capacitance is guaranteed. Therefore, ProPagatlon delay t ime

during load capacitance other than the above is obtained by

the f ol lowing eqr:at ion.

(Example) High level propagation delay t ime in the case of load

capac i tance of XpF.

tp l n ( x ) = d (X - 50 ) + t pLH (50 )

A: I { igh leve1 propagat ion de lay t ime increase ra te

per un i t load capac i tance (ns/pF)

oErlP

> ort FlO F Id E

AH + t

35. t Ao r 5a,Aok* 50 100

Load Celnclty C1, (pF)

76

Table 6-3 Load Capacitance

Characteris t ics

Dependence of AC Electr ical

( ns /pF )

Standard Output Buf fe r Outpu t

Tlpical va1rc(Ta = 25?e)

L im i t va lue( T a = 8 5 ' C )

Typd-cal vaLtre(Ta = 25 "C) -

L im i t va lue( T a = 8 5 ' C )

tttH, tTHL

0 . 3 3

o . r20 . 0 9

0 . 8 3

0 . 2 4

0 . 1 6

0 . 2 2

0 . 0 8

0 . 0 6

0 . 5 5

0 . 1 6

0 . 1 1

tpt fi, tPHL

o .L7

0 .96

0 .043

0 . 4 3

o . L 2

0 . 7 7

0 . 1 3

0 . 0 5

0 . 0 3 8

0 . 3 3

0 . 1 0

0 . 0 6 8

Table 6-3 ind icates increase ra te per un i t capac i ty o f AC

e lec t r i ca l cha rac te r i s t i c s hav ing l oad capac i t ance dependence .

In the case

ca l cu la t i on

6-4. Temperature Parameters o f Var ious

In TC74HC ser ies , 3D operat ion in

such as -40 to 85"C is guafanteed.

swi tch ing t ime and output cur rent

'of

by

heavy capac i tance load, i t is necessary to make

us ing the l imi t va lue in th is tab le .

Cha rac te r i s t i c s

a wide temperature range of

This chapter shows how the

are inf luenced by temperature.

(1) Temperature Character is t i -cs o f Output Current

F ig . 6-7 ind icates temperature dependence of output cur rent .

In th is f igure, so l id l ine shows the temperature dependence

in s tanda rd samp le . The re fo re , a t t he t ime o f des ign ing , use

the b roken l i ne i nd i ca ted as t he wo rs t case .

77

N

o

4J

N

F{Po

t_40

1 ? 0

1 0 0

80

VCC:45Vrour

AIOUT:_ :XLOOf orrn( Ta:Z5'C)

140

1 2 0

1 0 0

80

A.r-20i o ?0 40Ta ("c)

F i g . 6 - 7

1 0 0 -40 -20 0 ? 0 4 0ra (")

F i g . 6 - 8

1 0 0

(2) Tmeperature Character is t ics o f Propagat ion Delay T ime

Fig. 6-8 shows temperature dependence of propagat ion de lay

t ime. Sol id l ine in th is f igure ind icates s tandard temper-

ature dependence at Gate IC. , At the t ime of des ign ing,

therefore, use the broken l ine ind icated as the worst case.

7. PREcAUTIONS IN HANDLING

7 -L . E lec t r i c S ta t i c D i scha rge

CI"OS IC has very th in gate insu la t ion ox ide f i lm. When h igh

vol tage i -s appl ied to th is gate e lect rode ( input o f CMOS IC) ,

ox ide f i lm d i rect ly under the gate causes d ie lect r ic breakdor^rn

somet imes. In TC74HC ser iesr 6s shown in F ig . 7-L , res is tnace

and diode are added to al l input terminals in order to protect

CMOS gate f rom such h igh vo l tage. However , pro tect i -ve c i rcu i t

may not necessar i ly be ef fec t ive against acc identa l h igh

vo l t age , ca re mus t ' be f u l 1y t aken i n hand l i ng i t .

V6g45V

C1 :5OpF

ltnd: tPd-

tpd( Ta:P5"C)

78

vcc

ND

vcc -

I1t1

GND

Inpu t Ou tpu t

*- J

F ig . 7 -L I npu t P ro tec t i ve C i r cu i t , No te )

Ou tpu t Equ i va len t C i r cu i t

Futher , 8s parast ic d iode is formed

between each termi-na ls as ind icated

in F ig . 7-L , thermal breakage and

la tch up due to excess ive cur rent

may sometimes be caused when the

vol tage exceeding the ra t ings is

appl ied between each termina ls .

Therefore, care must fu11y be taken

at the t i -me.of assembl ing and

ad j us tmen t .

As input protect ive

res i s tance , po l y s i l i con

resistance of 20O to 400f1

i s u s e d .

test method I n F i g .

(1) E lect rosta t ic Discharge Test Method

Fig. 7-2 shows e lect rosta t ic d iscahrge

7-2, tes t j -s conducted wi th

C = 200pF , R = 00 . Tab le 7 -L

shows the resu l ts o f e lec t ro-

s ta t i c d i scha rge t es t ap -

pl ied to a r.pr"""rrtaEive ^?f-_o la

type of TC74HC ser ies. | |vtTT

In- the test of the above L tmethod standardized by EIAJ,

i t i s acknowledged that +200V

w i l l p rac t i ca l l y w i t hs tand anFig . 7 -2 Tes t C i reu i t

ord inary serv ice condi t ion. As shown by Table 7-L Toshibats

TC74HC ser ies has ample capac i tance.

V n n

Inputo rOu tpu t

GND

7g

Name

Input Output

Impress ion of* vo l tage

Impress ion of- vo l tage

Impression of* voltage

Impress ion of- vo l tagd

TC74HC OOP 300v -300v Above 1000V Above -1000V

TC74HC O4P 400v -350v Above 1000V Above -1000V

TC74HC 74P 300v -300v Above 1000V Above -1000V

TC 74HC1 38P 450V -350v Above 1000V Above -1000V

TC7 4HC24OP 350V -350v Above 1000V Above -1000V

TC7 4HC37 3P 350V -350V Above 1000V Above -1000V

C = 200pF, R = 00, Impress ion f requency three t imes

Table 7-L Test Resul t

7 -2 . P recau t i ons i n Hand l i ng

(1) Transpor ta t ion and Storage

As input and output terminals of unmounted CI'{OS IC are in the

sta te o f h igh impedance, they are apt to rece ive induct ion

f rom the surroundipg chargep body, space e lect r ic f ie ld , and

human body . Fo r t h i s r eason , i t " i s necessa ry i n t r anspo r t i ng

and s tor ing them to use d ie lect r ic mat , meta l case or a lumi-

num foi l box, so that each terminal of IC may become at same

p o t e n t i a l .

As TC74HC series is inserted in a maga zine given no-charging

t reatment a t the t ime of sh ipment , do not take i t out f rom

the maga zine unnecess arLLy. Especial ly, avoid to use plast ic

or v iny l conta iner which is apt to charge s ta t ic e lect r ic i ty .

80

(2) Assembl ing

I^ lhen ins ta l l ing CMOS IC on the pr in ted board, i t i s necessary

to protect the e lect r ic equipment , work ing s tand and operators

f rom s ta t i c e l ec t r i c i t y by .mak ing g round ing . I t i s adv i sab le

to ground the work ing s tand by spreading meta l p la te or a lumi-

num fo i l on the sur face. Grounding of operators should be

made through the resistance of about l Mft so as to prevent an

elect r i -c shock. I t j .s convenient to make grounding through

meta l l i c r i ng o r me ta l l i c wa tch band . A l so , i t i s adv l sab le

not to wear work ing c lo thes make of chemica l f iber . Fur ther ,

i t is necessary to per iod ica l ly check e lect r i -c equipment to

i nsu re absence o f e l ec t r i c l eakage .

When shaping the lead wi re dur ing the packaging of IC, 1 t is

adv i -sab le to use p incet or s imi lar j ig , so that s t ress may

no t be g i ven t o t he roo t .

l , lhen s tor i -ng or t ranspor t ing the complete ly assembled pr in ted

board, shor t c i rcu i t the termi .na ls o f pr in ted board or cover

the ent i re board wi th a luminum fo i l , so that input termina l

o f IC may be opened .

(3) Solder ing, washing

I,r lhen making so]deri-ng by using soldering lron and tank, carry

out the work a t the temperature o f 260"C or be low wi th in 10

seconds . I t i s con f i rmed tha t t he re l i ab i l i t y o f TC74HC

ser ies is never a f fec ted when subjected to a temperature

st ress to the s topper o f lead at 260"C for 10 seconds.

Use a so lder ing i ron hav ing no leak a t i ts end. I t is re-

commended to use A class iron having insulat ion resistance

exceeding 10 M0.

81

When using soldering tank, i t is necessary to make grounding

so as to prevent the potential of soldering tank from becoming

unstab le

Af ter so lder ing IC on the pr in ted board, c lean ing i .s made to

remove f lux , e tc . For th is c lean ing is used f lux removing

abluent or c lean ing method ut i l i z ing u l t rasonic wave. Care

must be fu l1y taken for the se lect i -on o f th is so lvent so a t

to prevent the effect given to the packagg and mark of CMOS IC.

In genera l , i t i s adv isab le to use Freon ser ies .

In the case of u l t ra 'son ic c lean ing, i t is necessary to prevent

the s t ress due to resonance f rom being imposed on IC or

p r i n ted boa rd . Fo r t h i s pu rpose , i t i s needed to cons ide r such

washing method that the main body becomes a shade against a

v ibrator , and a lso a c lean ing t ime of less than 30 seconds.

(4 ) Ad jus tmen t , Tes t

. l r lhen making adjustment and test af ter the completion of

pr in ted c i rcu i t board, i t i s necessary to check absence of

so lder ing br idge or crack on the pr in ted board before swi tch-

i -ng on supply power . As CMOS system requi res on ly smal l

supply cur rent , i t i s wel l to apply cur rent l imi ta t ion when

urak ing test by us ing marketed constant vo l tage pohTer source.

Inlhen mounting and dismounting printed circuit board on and

f rom the socket , never fa i l to cut o f f power supply before-

h a n d .

82

l r lhen surveying each part of printed board with probe during

the test , care must be fu l ly taken to prevent contact o f t ip

of probe with other si-gnal or poT^rer li-ne. when surveying

place is prev ious ly determined, i t is adv isab le to erect a

spec ia l t es t p i n .

When test is conducted under high temperature and low temper-

aturer i t is necessary to take grounding of constant temper-

ature oven, and the ins ide set must be on or in the inhuct ive

ma terial .

Th is i tem except ing one par t , is a lso appl icab le when CMOS IC

s ing le t rn i t is tes ted.

/

8. PREcAUTIoNS IN DESIGNING cIRCUITS

8-1 Input Processing

(1) Processing of unnecessary gate

Input of CMOS IC has so high impedance that logical leve1

becomes underf ined under open condi t ion. In th is case, i f

input is a t in ternedia te leve l ,

the t rans is tors o f both p-channel

and N-channel becorne continuity

s ta te , and unnecessary supply

current f lows.

Therefore, as shown in F ig . 8-1 ,

be sure to connect unnecessary

input l ine to VCC, GND or other

input and output whose log ica l

1evel is decided

83

Fig. 8-1 Treatment o f Input

rn the case of cMos, i f soldered part has bad contact , mul-

funct ion of system or increase of supply current wi l l be

caused. Therefore, care must be taken at the t ime of wir ing.

(2) Input process ing of pr in ted c i rcu i t board

F i g . 8 - 2 .

8-2 Design of Power Source

tr lhen input terminal of printed circuit

direct ly to CMOS input, CMOS input

is brought to e lect r ica l ly f loated

condi-t ion as in the case of IC

single unj-t when transported or

s tored as a s ing le un i . t o f pr in ted

board. I t is adv isab le , therefore,

to connect previously to VCC or GND

through res i -s tance in the pr in ted

c i r cu i t boa rd r 3s i nd i ca ted i n

board is connected

F:: lookf}

8-2 Input processing

pr inted circui t board

F i g .

; o f

trn general, cMos requires -srnal l

consumption current in com-

par i -son wi th o ther b ipo lar d ig i ta l rc , and therefore i t needs

only srna l l capac i ty power supply . However , f rom i ts operat iona l -

requirement, cMoS consumes poh/er in spike state, and therefore

it is necessary to keep high frequency impedance of 'pohrer

source at low leve l

r t is adv iasable to make wi r ing o f power source (v6g) l ine

and GND l ine thick and short, and to insertr eis high

f requency f l i te r , once 0.01 gF to 0 .1 t tF capac i tor between V6g

""a GND for each IC.

84

Also, i t is recommended to inser t a condenser o f about 10pF

to 100uF between power supply entrance and GND as low frequency

f i l te r . As rRean supply cur rent cons iderab ly d i f fers depending

upon operat ing f requency of system, ex is tence of condenser

load, r is i -ng and fa l l ing o f input s igna l

and supply vo l tage, a t tent j_on must be

spec ia l ly g iven in the case of s imple

poT^rer source by Zener diode, oE battery

dr iv ing. . t lhen there is overshoot ing

or urtdershooting during transient t ime

of supply pourer , use f i l te r e tc , so

that the maximuri rat ing rnay not be

exceeded .

F ig . 8-3 Example o f

increase in driving capacity

8-3 On Output Shor t -c i rcu i t

rn Tc74Hc ser ies , buf fer is added to the output , and both

f low-out ( IOH) and f low- in ( IOf , ) cur rent dr iv ing are poss ib le .

. For th is reason, excess ive cur rent f lows in C IvXCS output whenf r11rr leve l output l ine is shor ted wi th GND l ine or f r t r r f

l eve l : ou tpu t l i ne i s sho r ted w i t h Vgg 1 ine . pa r t i cu la r l y ,

when the supply voltage is high, arlowable loss of package

is exceeded by th is cur rent , and therefore care must be taken

n o t . t o c a u s e o u t p u t s h o r t c i r c u i t .

:I t is of course impossible to direct ly connect ordinary outputs

together, but in the case of rc which has 3 state output,

wired OR ls pernitted provided that more than two outputs

do not become enable s imultaneouslv.

85

Further, in order to improve driving capacity, i t is possible

to connect the gates in the sane package as shown in Fig. E"'3.

8-4 Ef fect o f Input o f S low Rise T ime and Fal l T ime

When the waveform of slow rise

ti .me or fal l t ime is im-

pressed to CMOS input , i t some-

t imes happens that output

tends to osc i l la t ion around VtU

( threshold vo l tage of c i rcu i t )

of input waveform in the case

of gate IC. Th is is because

CMOS gate becomes l inear ampl i -

f ie r equ iva lent ly in the v ic in-

i ty o f VtU, and minute power

source r ipp le and no ise compo-

nent are ampli f ied in the out-

put and appear .

For the purpose of prevent ing

the above , i t i s necessa ry t o

inser t h igh f requency f i l te r

condenser between VCC and GND

of osc i l l a t i ng IC , o r t o use

Schmi t t t r i gge r IC .

In the case of TC74HC ser ies ,

except ing HCU type, Schmi t t

t r igger IC, inpu. t r is ing and

fa l l ing t ime is regula ted as

shown in Table 8-1 in the

recommended operating condi--

C L O C K

C L O C K

F/Y I FA_Z

CIJOCK

i-rt l

(a) Normal operating waveform

Qt

C L O C K

nr

v11c2

n,

nt

n,

(c ) Mal funct ion waveform f romat the tire of VthCl <V16C2

Fig.8-4 Example o f Mal funct ion

Eions. P lease fo1 low th is condi t ion.

(b ) Ma l f unc t i onat the time

waveform fromof VthCl>Vs6C2

V11C1

V 15C2V 1 5 C 1

86

F i g . 8 - 4 s h o w s a n e x a m p l e o f m a l f u n c t i o n w h e n s h i f t c o u n t e r i s

c o n s t i t u t e d b y u s i n g t y p e D f l i p - f l o p o f a n o t h e r p a c k a g e .

In t h i s case , ma l f unc t i on i s cons ide red t o be

c a u s e d b y t h e d i f f e r e n c e o f c i r c u i t t h r e s h o l d l e v e l o f

r e s p e c t i v e D t y p e f l i p f 1 o p .

N o w , l e t c i r c u i t t h r e s h o l d l e v e l o f F / F - I b e V 5 6 C l , a n d t h a t

o f F / F - 2 b e V t t r C 2 . T h e n , d s s h o w n i n F i g . 8 - 4 , t i m e d i f f e r e n c e

, \ t i s f o r m e d w h i l e t h e r i s i n g w a v e f o r m o f c l o c k p u l s e c u t s

t h e r e s p e c t i v e c i r c u i t t h r e s h o l d v o l t a g e , a n d t h u s m a l f u n c t i o n

t a k e s p l a c e .

T h e f o 1 l o w i n g c : o n d i t i o n i s r e q u i r e d f o r i n s u r i n g n o r m a l

o p e r a t i o n :

h t < t p d ( C f - Q ) + t s e t - u p

I n t h i s c a s e , t h e r e i r

a p o s s i b i l i t y o f m a l f u n c t i o n e v e n

t h o u g h i n p u t s i g n a l i s w i t h i n t h e s t a n d a r d v a l u e o f T a b l e 8 - 1 .

T h e r e f o r e , c a r e m u s t b e s p e c i a l l v t a k e n f o r s e q u e n c e c i r c u i t

c l o c k i n p u t .

T a b l e 8 - 1 S t a n d a r d V a l u e o f I n p u t R i s i n g a n d F a l t i n g T i m e

I t em Symbol L im i t Uni t

I n p r r t R i s i n g

and Fa l l i ng T imetr, tf

Q r , 1 0 0 0 ( V C C = 2 . 0 V )

0 ' \ , 500 (VCC = 4 .5V)

0 t u 4 0 0 ( V C C = 6 . 0 V )

N S

87

8-5 Precautions for hl ir ing

(1) Output waveform d is tor t ion

As output impedance of TC74HC ser ies is cons iderab ly low in

compar ison wi th the convent iona l s tandard q l4OS IC, d is tor t ion

is somet imes caused in the output waveform depending upon L

component o f w i r ing, when the wi r ing connected to output end

is long or when capacitance is connected between signal l ine

and VCC or between s ignal l ine and GND. Thereforer 'when

designing the printed board, take care not to make signal

wi r ing length tbo 1ong. In the case of both s ide pr in ted

boa rd , i t i s i dea l t o l im i t s i gna l w i re l eng th t o 30cm o r

l ess . Espec ia l l y , i n t he c l ock s i gna l l i ne , d i s to r t i on o f

waveform causes mal funct ion

(2) Precaut ions for ar rangement

Output o f TC74HC ser ies has qu ick r is ing and fa l l ing t ime,

and makes fu l1 swing at VCC-GND, and so i t becomes a no ise

sou rce o f o the r s i gna l , . The re fo re , i t i s des i rous t o l oca te

i t sepa ra te l y f r om a pa r t wh i ch i s sens i t i ve t o a no j - se o f

ana log c i r cu i t . A l so , ca re mus t be t aken f o r t he reduc t i on

of load number and cur ta i lment o f w i r ing length.

(3) Terminat ion

F rom j - t s phys i ca l and e lec t r i ca l f ac to r s , TC74HC se r i es i s

ap t t o cause ove rshoo t i ng and unde rshoo t i ng , and t h i s l eads

to ma l f unc t i on o f c i r cu i t o r b reakdown o f pass i ve IC . These

t roubles can be prevented to some extent by terminat i -ng the

end o f s i gna l l i ne . F ig . 8 -5 i nd i ca tes examp les o f gene ra l

terminat ion

88

Tt

(a) Termi-nation by (b) Terminat ion by ' D iodeCR

Fig. 8-5 Examples o f Termj-nat ion

8 -6 I n te r f ace

(1) Input and output in ter face

When rhaking some processing with CMOS system, most systems

make exchange of s igna ls wi th .externa l c i rcu i t or mechanism.

These input and output signal l ines are natural ly made long

in many cases, and have d is t r ibuted inductance or reactance.

Therefore, i f d i rec t ly connected wi th CI 'OS, they wi l l g ive

r i se t o va r i ous t r oub les .

Conceivab le ser ious t roubles mav be the mal funct ion due to

i nduced no i se , and t he des t ruc t i on o f i npu t / ou tpu t e l emen t

due t o su rge . To cope w i t h t hese p rob lems , r educ t i on o f

s igna l l ine impedance (dr iv ing impedance) or inser t i -on o f

no ise e l iminat ing c i rcu i t on the rece iv ing s ide is appl ied

for the fornrEr , whi le surge protect ive measures are taken

fo r t he l a t t e r .

F ig . 8-6 i l lus t ra tes an example o f making no ise . surge pro-

tect ion on the input s ide ' .

89

(a) and (b) of this figure show an example of absorbing

noise by integrating lnput waveform by RC. (c) and (d)

indicate an example of protecting cl.os from input surge.

Fig. 8-7 gives an example of output interface. These are

only one example, but in any case, some protection should be

given to an interface involving long signal l ine.

Fig. B-7 Output Protect ion/Dr iv ing Ci rcu i t

T7n

( a ) u o i s e K i 1 1 e r I

vcc

T( u ) N o i e e Ki l -1er 2

, \

vco

Gtt

( c ) S u r g e P r o t e c t i o n 1 S u r g e P r o i e c t i o n Z

Fig. 8-6 C MOS Input Protect ive Circui t

J_

4i(u) output Dr iver

( a ) S u r g e P r o t e c t i o n f

\ Ei+fl,i

( " ) o u t p u t D r i v e r P ( a ) S u r g e P r o t e c t i o n Z

90

( 2 ) I n te r f ace o f C MOS IC

In the case of mutua l in ter face between CIOS IC, input im-

pedance of CMOS has so large value that l imitat ion of fan out

may not be so large. However, there is actual ly need to

cons ider fa l l o f propagat ion t ime due to adding ef fec t o f load

capacity and an increase of power consumption.

As input capac i ty o f CMOS is about 5 pF per input , i f 10

fan outs are taken for example, load capacity of 50pF is given

by i t , and fur ther , l ine capac i ty on the pr in ted board must

a lso be taken i -n to account . Th is shows that the process ing

speed of system is cont ro l led not on ly by c i rcu i t const i tu t ing

me thod bu t a l so bv f an ou t .

When const i tu t ing a system wi th CI"OS IC, i t is recommended

to examine fan out by tak ing these po in ts in to cos iderat ion.

(3) In ter face between, d i f ferent CMOS fami l ies

The prob lem to be cons idered between d i f ferent CI ,OS fami l ies

i -s d i f ference of supply vo l tages between fami l ies . t r lhen

di f ferent C MOS fami l ies are used wi th the same power source,

i t is al l r ight to pay attention to Ehe hazard due to the

p ropaga t i on de lay t ime d i . f f e rence , bu t i n t he case o f d i f -

ferent power source, the vo l tage leve l conver t ing c i rcu i t is

needed

Fig. 8-8 shows an in ter face method f rom the s tandard C MOS

oprat ing a t 6V^, 15V to 74HC. The npst popular method is to

use C MOS (4O4gB/40508) which- Ias leve l sh i f t funct ion as

shown in th is f igure.

91

40498140508 has diode of

constructed that current

(VCC) of 5V system even

GND side diode only, and is so

does not f low in the power source

though vo l tage of 15V is impressed.

On the otherhand, an in ter face f rom 74HC to s tandard C MOS

can be rea l i zed by us ing TC5020BP o f l eve l sh i f t use IC , as

i n d i c a t e d i n F i g . 8 - 9 ( a ) . F g r t h e r , i t i s a l s o p o s s i b l e t o

use d i sc re te t r ans i s to r as shown i n F ig . 8 -9 (b ) . The c i r cu i t

employ ing d iscrete t rans is tor can of course be used for power

i nve rs i on .

(4) In ter face wi th TTL

When dr iv ing TI I - w i th TC74HC ser ies , input and output vo l tage

leve1 can be connected in that s ta te . w i thout t roub le . Fan out

is dec ided by output cur rent o f CMOS IC and input cur rent o f

TTL. I ts example is shown in F ig . 8-10. .

61F"15V

li+!L t

LFig. 8-€ Standard C D'0S

It_Stand ard C l lOS

L _ _ _ _ _ _ JL e v e l t h i f t e r

4049P,,/50B'

92

+ 74HC In ter face

5V

,/ oHC

(b) , Example o f us ing t rans is tor

F ig . 8-9 74HC. + Standard C MOS

+ TTL

93

6V-15V

TC5O ?OBPS t a n d a r d C M O S

using leve l sh i f ter IC.

Stand.ard C I1OS

Level convers ionby t rans i -s tor

Fan Out Number

In ter face

-lLl

14HC

(a) Example of

rl- - --.{LJ

6 V - L 5 V

vgc:5v

Standard TyPe Buffer Type

TTL

S TTL

LS TTL

ALS TTT,

2

2

10

20

3

3

1 5

30

Fig. 8-10 TC74HC

In th is way, TC74HC ser ies is capable o f d i rect ly dr iv ing

var ious TTL dev ices.

On the other hand, when driving TC74HC series from TTL, i t is

necessary to convert output voltage level of TTL to input

level of 74HC. Normally, in this case TCT4HCT series which

has same input level with LS TTL are used. Input current of

TCT4HCT series is very sma11 l ike that of TC74HC series, and

therefore no burden is imposed on the driving side 74L5, and

the speed a lso does not fa11 so much. Therefore i t can be

said to be an ef fec t ive method. Another npthod is to use

pul1 up res is tance as shown in F ig . 8-11.

R p : P u l f u p R e s i s t a n c e

( z_loK())

F i g . 8 - 1 1

(5) Interface with CPU

TTL + TC74HC Interface

At present , as the per iphera l suppor t ing log ic o f micropro-

cessor of rnany NloS and cMoSr T4LS series is used universal ly.

As TC74H} series has the same speed with 74L5, i t can natural ly

be used as microporcessor per iphera l log ic .

94

As for an interface between C MOS CPU and 74HC seri-es, there

is no prob lem because both are CMOS. At present , however ,

prio-r i ty of NI.OS CPU ls higher, and interface of NIOS to CMOS

must be taken into consideration.

Output o f most NMOS CPU def l -ec ts up to near VCC, but as shown

in F ig . 8-12, 8s outputs q f both dr iv ing MOS and load MOS

are.const i tu ted wi th enhancement typer ro def lec t ion takes

place unt i l VCC. For th is reason, in order to cer ta in ly

carry out the signal transfer from NMOS CPU to 74HC, i t is

easy to use 74HCT series which has an input of TTT. l-evel .

When connect ing 74HC ser ies , pu l l up res is tance is used as

i n d i c a t e d i n F i g . 8 - 1 2 .

Next, driving of NMOS CPU

wi thou t d i f f i cu l t y . Th i s

is of high impedance l ike

taken in to cons iderat ion.

from 74HC series can be connected

is because, normal ly input o f NMOS

C MOS, and DC fan out need not be

R p : P o 1 ] u p R e s i s t a n c e

d- -

._l

Fig. 8-L2 NMOS CPU Interface

95

8-7 Latch-up

Ldtch up is a phenomenon pecul iar to CMOS, and is a lso ca l led

scR, (s i l i con cont ro l led Rect i f ie r ) phenomenon. Dur ing the

no rma l ope ra t i on t ime , i f excess i ve vo l t age and cu r ren t

caused by b ig no ise or acc identa l surge are appl ied on the

input and output termina l r or supply source ampl i tude is

sud.denly f luc tuated, abnorrna l cur rent f lows between Vcc and

GM, and th is abnormal cur rent cont inues to f low even. though

the 'd is turbance s ignal is cut o f f , and f ina l ly puncture is

caused. Latch-up is a name given to such phenomenon.

once the la tch-up takes p lace, the former condi t ion is not

restored un less the power supply is cut o f f or vo l tage is

lowered, and an overcurrent continues to f low be\ween vcc and

GND. r t t h i s s ta tus i s l e f t a1one , des t ruc t i on o f e l emen t

such as me l t i ng o f w i r l ng w i l l t ake p lace .

I

( 1 ) Cause o f l a t ch -up

F ig . 8 -13 shows - . r , .O r r r va len t c i r cu i t due t o pa ras i t i c

el.ement. NPN transistor Qz is formed in p-well of NMos

side whi le PNP t rans is tor Qr is formed in N-subst ra te o f

PMOS s ide , and pa ras i t i c r es i s tance ex i s t s be tween te rm ina l s .

As is c lear f rom the current path through the medium of

paras i t ic e lement ind icates in th is f igure, these paras i t ic

e lements const i tu te Thyr is tor .

96

OUT

Fig. 8-13 In terna l Equiva lent Ci rcu i t o f CMOS IC

For example, i f current f lows into the N-substrate frorn ex-

terna l causes, vo l tage drop takes p lace in res i .s tance Rs of

the N-substrate, and this causes to turn on parasist ic

transistor Ql, and current f lows towards GND from Vcc through

the medium of res is tance Rw of P-Wel l . When current f lows

in Rw, vo l tage drop takes p lace at both ends of Rw, Q2 turns

oD, and fur ther , supply cur rent f lows through Rs. As a re-

su1 t , t he vo l t age d rop a t bo th ends o f Rs f u r t he rs i nc rease ,

Qf and QZ are le f t in the turn-on s ta te , and the supply

current fur ther increases.

In th is way, i f the vo l tage drop takes p lace in res is tance

Rw of P- lde l l and in res is tance Rs of N-subst ra te , la tch-up

occu rs , and t he re fo re , t he f o l l ow ing causes a re cons ide red .

P o l y S r l i c o nr e s i s t a n c e

N - S u b B t r a t e

L _ _P-[te ]-1

I

-+ -

b00

97

To make input voltage higher than V66 + Vp

(QS of Fig. 8-13 turns on)

To rnake input voltage lower than GND - Vf

(QS of Fig. 8-13 turns on)

To make output- voltage higher than Vgg + Vp

(QS o f F ig . 8 -13 ru rns on)

To make output voltage lower than GND - Vp)

To raise supply voltage VCC above the rated value and to

cause breakdoum, (To direct ly f low current in Rw or Rs)

Here, VF is the forward vo l tage between base and emi t ter o f

pa ras i t i c b i po la r t r ans i s to r Q3 - Q4 .

(2) Latch. up s t rength measurement

F ig . '8 -14

i l lus t ra tes measurement er<ample o f la tch up s t rength.

As ind icated in F ig . 8-14, la tch-up is induced by f lowing

current in to input termina l (O in jec t ion) or f lowing current

out o f output termina l . (O In ject ion) , and the cur rent va lue

at that t ime is ueasured. Table 8-2 shows the, resu l ts o f

Latch-up Strength Test of representative types of TC74HC

ser ies. As ind icated here, TC74HC ser ies have ample marg in

such as input of above + 70mA and output of above + 300mA

against the maximum rating of * 20mA.

@

@

o

@

o

98

I n n

(a) Measur ing c i rcui tstrength of Input

of (E In ject ionTerminal

(b) Measur ing c i rcui tstrength of Input

g

(d) Measur ingst rength

o f O In j ec t i onTerminal

c i rcu i t o f e In jec t ionof Output Terminal

( c )

rcc

Measur ing c i rcu i t o f @ In ject ionstrength of Output Termirral

Input condi t ion

Input condi t ion

Fig . 8-14 Latch-up

Current

make measured, terminal "Htt level.

make measu red t e rm ina l " L t ' l eve l .

St rength Measur ing Ci rcu i t by

Feeding System

to

to

-{>

r c c

vcc

IN OUT

GND

99

Table 8-2Unit : mA

Type C lass Input @ Input Q Output @ Output Q

74HCO2

u04

74

138

375

NOR.GATE

INVERTER

D-P/r

LINE DECODER

D-Latch

Above 70

Above 70

Above 70

Above 70

Above 70

Above 70

Above 70

Above 70

Above 70

Above 70

A'bove 300

Above 300

Above 300

Above 300

Above 300

Above 300

Above 300

Above 300

Above 300

Above 300

(Note 1) As for this input exceedj-ng !On'A

t300mAr Do measurement is made as

breakdown of e lement.

(3) Countermeasures

As ample rnargin 'is provided for

there is no problem in using the

However, for the interface part

rece iv ing excess ive surge. , i t i s'

pro tect ive c i rcu i t as ind icated

and the output exceeding

there is a poss i .b i l i ty o f

la tch-up as exp la ined in (2) ,

un i t w i th in the s tandards.

having the possibi l i ty of

recommended to add the

i n F i g . 8 - 1 5 .

F ig . 8-15 Example o f Latch-up Prevent ive Method

r00