22 www.rfdesign.com April 2006
CMOS RF transceiver chip tackles multiband 3.5G radio system Board space and cost are among the top concerns for manufacturers of next-generation multimedia, thin-profile mobile phones. Plus, with the advent of HSDPA networks, wireless carriers are anxious to capitalize on increased data throughput in these devices. Thus, driving the need for higher integration, robust architectures, and receive diversity in RF transceiver design. In this article, the author presents an innovative single-chip CMOS RF transceiver that incorporates a complete multiband HSDPA/WCDMA and quad-band GSM/EDGE radio subsystem with receive diversity for multimode wireless applications.
By Kiran Konanur
Spanning multiple standards, frequency bands and multimedia applications, 3.5G mobile phones are becoming increasingly complex. This trend, coupled with a demand for low-cost, thin-profile handset designs, is driving the need for smaller RF subsystems. And now, with the projected growth of high-speed downlink packet access (HSDPA)-enabled networks, the requirement for higher data through-put in these subsystems is increasing as the realization of multimedia cellular applications becomes more evident.
As the demand for higher integration increases, RF integrated circuit (RFIC) designers must stretch the limits of available process technologies to implement transceiver architectures that support wide-band multistandard mobile operation. Given the additional demand for smaller and cheaper solutions, it is understandable that many 3.5G RFIC
designers are migrating to nanometer CMOS process technologies. The near-term goal in CMOS integration is to create a monolithic
RF transceiver that supports quad-band GSM/EDGE and multiband WCDMA operation with enhanced HSDPA performance. As RF CMOS technologies mature at deep submicron levels (90 nm and lower) it is a reasonable expectation that innovative IC designers will realize the complete integration of RF transceiver and baseband processor functionalities in a single chip. This RF-baseband integration effort is already gaining momentum for GSM/GPRS systems.
CMOS advantageIn the not-too-distant past, BiCMOS process technologies, such as
silicon germanium (SiGe) and silicon-on-insulator (SOI), were more suitable for analog and RFIC design than CMOS. However, as CMOS processes continue to mature in their support of analog and RF design, they are fast becoming the technology of choice in RFIC development. This transition is driven primarily by the fact that CMOS processes are less expensive and more conducive to large-scale integration than BiCMOS.
IC designers making this transition have tended to simply transfer their analog-based bipolar-type circuit designs from BiCMOS to CMOS. The negative result of such an approach to RF CMOS design is larger die size and higher current consumption. Thus, the only benefit gained in this move to CMOS is reduced cost due to a cheaper wafer process.
A digital approach to RF design is needed to reap the full benefits of CMOS. By implementing digital-based transceiver architectures, RFIC designers take full advantage of the switching characteristics of MOS transistors in CMOS, thereby significantly decreasing size and current consumption in addition to cost. Only when such an approach to RF CMOS design is taken can Moores law be fully leveraged.
To further illustrate the digital CMOS advantage, an analog filter circuit is more than twice the size and consumes more than twice the current than its digital equivalent at the same CMOS process node. When these filter circuits are implemented at subsequent process nodes, the size difference grows exponentially, thus demonstrating the scalable advantage of digital circuitry in CMOS.
Analog RF circuits, in general, require higher supply voltage levels than digital RF circuits to maintain similar performance levels. Supply voltages below 1.4 V (at 90 nm CMOS and smaller) are not suitable for analog RF circuits because very high current levels are needed to meet dynamic range and matching requirements. Conversely, for digital RF circuits, current consumption decreases at smaller process nodes.
As line widths continue to shrink, nanometer CMOS technology Figure 1. Example of a digital 65 nm CMOS RF transceiver chip.
Digital IQ DirectUp-Conversion
Digital Functions: Filtering DC Offset Correction DigRF Interface Control Interface
Digital Functions: Filtering DigRF Interface Control Interface
24 www.rfdesign.com April 2006
is also enabling RFIC designers to achieve ever-higher levels of integration. For example, at 130 nm line widths, it is possible to design and fully integrate digital loop filters for PLLs, which not long ago were considered a standard external bill of materials requirement for RF transceivers.
The emergence of the DigRF digital baseband interface standard has further facilitated the move toward a more digital-oriented CMOS transceiver design. The current release of the DigRF standard (version 1.12) supports the full integration of a 2.5G analog baseband processor. The next release of the DigRF standard will enable 3G analog baseband integration into the transceiver.
The above-mentioned size, current and integration differentiators demonstrate that digital-centric RF CMOS transceiver designs have a decisive long-term advantage over analog-centric designs. They will continue to decrease in cost and feature increased programmability.
It is conceivable that transceiver designs in CMOS at 65 nm line widths could become as much as 90% digital. The potential of this trend is illustrated in Figure 1. At the 65 nm CMOS process node, traditional analog circuits such as baseband filtering, transmit upconverters and PLLs will transition from the analog domain to the digital domain.
Receive architecture considerationsAs mobile phones have incorporated support for more frequency
bands and wideband modulation standards, receiver architectures have followed a progression from high intermediate frequency (IF) designs to zero-IF designs, otherwise known as direct downconversion.
Initially, high-IF super-heterodyne (super-het) receivers were used quite extensively for low-band GSM handsets. Although super-het architectures produced robust GSM receivers, they were limited in their ability to support a broad range of frequencies and required large, expensive external IF filters.
When RFIC designers started implementing quad-band (GSM850, EGSM900, DCS1800 and PCS1900) GSM and EDGE functionality into single-chip transceivers, they gravitated toward either direct down-conversion or low-IF architectures, both of which eliminated the need for external IF filtering. However, in support of wideband modulation standards, such as WCDMA, low-IF architectures have fallen short, whereas direct downconversion architectures have proven ideal.
Direct downconversion receivers also feature better spurious response than low IF designs. This advantage is due to the fact that low-IF receivers have to contend with image tones, and direct downcon-verters, in general, display higher tolerance to spurs generated by PLLs.
When integrating a direct downconversion mixer within a propri-etary digital-based receiver design, automatic calibration algorithms can be designed into the receiver itself. Calibration parameters can be programmed into the receiver during chip design validation, thereby eliminating the need for unit calibration on the handset manufacturing line.
The design of direct downconversion receivers does present its challenges. Due to their susceptibility to dc offsets at the mixer output (at baseband levels) in the presence of blockers, RFIC designers have found the application of direct downconversion architectures to narrow-band modulation schemes an arduous task. To further complicate the dc offset issue, 1/f flicker noise is introduced into the receiver when direct downconversion architectures are implemented in CMOS.
Innovative CMOS RFIC design techniques, which are the secret sauce of successful direct downconversion design, are required to resolve these dc offset issues. When these dc offset challenges are overcome, the benefits of direct downconversion receivers make them the clear architecture of choice for multimode transceiver design.
Optimizing HSDPA throughputFirst-generation HSDPA-enabled networks are targeting Category
6 throughput performance, which has a 3.6 Mbps theoretical down-link data rate. The effective HSDPA data rates are dependent on the processing capabilities of the baseband processor, as well as the
ability of the transceiver to receive and downconvert a high-quality RF signal throughout the cell.
In attempts to maximize effec-tive HSDPA throughput and elimi-nate fading conditions across the entire cell, handset designers are beginning to implement receive diversity, which uses dual anten-nas and receive chains. Introduc-ing receive diversity into Category 6 HSDPA systems greatly im-
proves effective data rates, pushing them to maximum capacity close to the cell center. A radio subsystem that implements receive diversity using a next-generation advanced receiver can more than double the effective downlink data rate to the mobile device throughout the cell as shown in Figure 2.
The future implementation of a WCDMA digital baseband inter-face in RF transceiverspending the ratification of the 3G DigRF standardwill enable the application of innovative digital filtering techniques in the receive path. The resulting digita