USB3300 Hi-Speed USB Host Device or OTG PHY …Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface Datasheet SMSC USB3300 3 Revision 1.08 (11-07-07) DATASHEET 0.1 Reference

SMSC USB3300 DATASHE

PRODUCT FEATURES
USB3300
Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0Interface compliant with the ULPI Specification revision 1.1 in 8-bit modeIndustry standard UTMI+ Low Pin Interface (ULPI) Converts 54 UTMI+ signals into a standard 12 pin Link controller interface54.7mA Unconfigured Current (typical) - ideal for bus powered applications83uA suspend current (typical) - ideal for battery powered applications Latch-Up performance exceeds 150 mA per EIA/JESD 78, Class IIESD protection levels of ±8kV HBM without external protection devicesIntegrated protection to withstand IEC61000-4-2 ESD tests (±8kV contact and ±15kV air) per 3rd party test facilitySupports FS pre-amble for FS hubs with a LS device attached (UTMI+ Level 3)Supports HS SOF and LS keep-alive pulseIncludes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go Supplement Revision 1.0a specificationSupports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)Allows host to turn VBUS off to conserve battery power in OTG applicationsSupports OTG monitoring of VBUS levels with internal comparators. Includes support for an external VBUS or fault monitor.

Low Latency Hi-Speed Receiver (43 Hi-Speed clocks Max) allows use of legacy UTMI Links with a ULPI wrapperIntegrated Pull-up resistor on STP for interface protection allows a reliable Link/PHY start-up with slow Links (software configured for low power)Internal 1.8 volt regulators allow operation from a single 3.3 volt supplyInternal short circuit protection of ID, DP and DM lines to VBUS or groundIntegrated 24MHz Crystal Oscillator supports either crystal operation or 24MHz external clock inputInternal PLL for 480MHz Hi-Speed USB operationIndustrial Operating Temperature -40°C to +85°C32 pin, QFN lead-free RoHS Compliant package (5 x 5 x 0.90 mm height)

Applications

The USB3300 is the ideal companion to any ASIC, SoCor FPGA solution designed with a ULPI Hi-Speed USBhost, peripheral or OTG core.

The USB3300 is well suited for:Cell PhonesPDAsMP3 PlayersScannersExternal Hard DrivesDigital Still and Video CamerasPortable Media PlayersPrinters

ET Revision 1.08 (11-07-07)

ORDER NUMBERS:

USB3300-EZK for 32 pin, QFN Lead-Free RoHS Compliant Package

USB3300-EZK-TR for 32 pin, QFN Lead-Free RoHS Compliant Package (tape and reel)

Reel Size is 4000 pieces.


Datasheet

Revision 1.08 (11-07-07) 2 SMSC USB3300DATASHEET

80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123

Copyright © 2007 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient forconstruction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSCreserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specificationsbefore placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patentrights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently datedversion of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errorsknown as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are notdesigned, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe propertydamage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies ofthis document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registeredtrademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSEOF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIALDAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELDTO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.


Datasheet

0.1 Reference DocumentsUniversal Serial Bus Specification, Revision 2.0, April 27, 2000

On-The-Go Supplement to the USB 2.0 Specification, Revision 1.0a, June 24, 2003

USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.02, May 27, 2000

UTMI+ Specification, Revision 1.0, February 2, 2004

UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1

SMSC USB3300 3 Revision 1.08 (11-07-07)DATASHEET


Datasheet


Table of Contents0.1 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Chapter 2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chapter 3 Pin Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.1 USB3300 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103.2 Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Chapter 4 Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chapter 5 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Chapter 6 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196.1 ULPI Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206.1.2 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216.1.3 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226.1.4 ULPI Register Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226.1.5 ULPI Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1.6 ULPI RXD CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.1.7 USB3300 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.1.8 USB3300 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.1.9 Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.1.10 Full Speed/Low Speed Serial Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376.1.11 Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6.2 Hi-Speed USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.2.1 High Speed and Full Speed Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.2.2 Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386.2.3 Bias Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.3 Crystal Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406.4 Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.4.1 Internal Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.4.2 Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.5 USB On-The-Go (OTG) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416.5.1 ID Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426.5.2 VBUS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436.5.3 Driving External Vbus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446.5.4 External Vbus Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Chapter 7 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467.1 Application Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477.2 Multi-port Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507.3 Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507.4 ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

7.4.1 Human Body Model (HBM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517.4.2 IEC61000-4-2 Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52


Datasheet


List of FiguresFigure 1.1 Basic ULPI USB Device Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 1.2 ULPI Interface Features as Related to UTMI+. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 2.1 USB3300 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 3.1 USB3300 Pin Diagram - Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 6.1 Simplified USB3300 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 6.2 ULPI Digital Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Figure 6.3 ULPI Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Figure 6.4 ULPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 6.5 ULPI Register Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Figure 6.6 ULPI Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 6.7 ULPI Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 6.8 Entering Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 6.9 Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Figure 6.10 USB3300 On-the-Go Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Figure 7.1 USB3300 Application Diagram (Peripheral). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Figure 7.2 USB3300 Application Diagram (Host or OTG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection) . . . . . . . . . . . . . . 49Figure 7.4 Expanding Downstream Ports for USB3300 Host Applications . . . . . . . . . . . . . . . . . . . . . . . 50Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free) . . . . . . . . . 52Figure 8.1 QFN, 5x5 Taping Dimensions and Part Orientation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53Figure 8.2 Reel Dimensions for 12mm Carrier Tape. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Figure 8.3 Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55


Datasheet


List of TablesTable 3.1 USB3300 Pin Definitions 32-Pin QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Table 4.1 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Table 5.1 Electrical Characteristics: Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 5.2 Electrical Characteristics: CLKOUT Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 5.3 DC Electrical Characteristics: Logic Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 5.6 OTG Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 5.7 Regulator Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 6.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 6.2 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Table 6.3 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 6.4 ULPI TXD CMD Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 6.5 ULPI RX CMD Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Table 6.6 Interface Signal Mapping During Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Table 6.7 Pin Definitions in 3 pin Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38Table 6.8 DP/DM termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Table 6.9 IdGnd vs. USB Cable Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 6.10 External Vbus Indicator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 7.1 Component Values in Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 7.2 Capacitance Values at VBUS of USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 8.1 32 Terminal QFN Package Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52


Datasheet

Chapter 1 General Description

The USB3300 is an industrial temperature Hi-Speed USB Physical Layer Transceiver (PHY). TheUSB3300 uses a low pin count interface (ULPI) to connect to a ULPI compliant Link layer. The ULPIinterface reduces the UTMI+ interface from 54 pins to 12 pins using a method of in-band signaling andstatus byte transfers between the Link and PHY.

This PHY was designed from the start with the ULPI interface. No UTMI to ULPI wrappers are usedin this design which provides a seamless ULPI to Link interface. The result is a PHY with a low latencytransmit and receive time. SMSC’s low latency high speed and full speed receiver provide the optionof re-using existing UTMI Links with a simple wrapper to convert UTMI to ULPI.

The ULPI interface allows the USB3300 PHY to operate as a device, host, or an On-The-Go (OTG)device. Designs using the USB3300 PHY as a device, can add host and OTG capability at a later datewith no additional pins.

The ULPI interface, combined with SMSC’s proprietary technology, makes the USB3300 the idealmethod of adding Hi-Speed USB to new designs. The USB3300 features an industry leading smallfootprint package (5mm by 5mm) with sub 1mm height. In addition the USB3300 integrates all DP andDM termination resistances and requires a minimal number of external components.

The ULPI interface consists of 12 interface pins; 8 bi-directional data pins, 3 control pins, and a 60MHz clock. By using the 12 pin ULPI interface the USB3300 is able to provide support for the full rangeof UTMI+ Level 3 through Level 0, as shown in Figure 1.2. This allows USB3300 to work as a HS andFS peripheral and as a HS, FS, and LS Host.

The USB3300 can also, as an option, fully support the On-the-Go (OTG) protocol defined in the On-The-Go Supplement to the USB 2.0 Specification. On-the-Go allows the USB3300 to function like ahost, or peripheral configured dynamically by software. For example, a cell phone may connect to acomputer as a peripheral to exchange address information or connect to a printer as a host to printpictures. Finally the OTG enabled device can connect to another OTG enabled device to exchangeinformation. All this is supported using a single low profile Mini-AB USB connector.

Designs not needing OTG can ignore the OTG feature set.

In addition to the advantages of the leading edge ULPI interface, the use of SMSC’s advanced analogtechnology enables the USB3300 to consume a minimum amount of power which results in maximizedbattery life for portable applications.

Figure 1.1 Basic ULPI USB Device Block Diagram

USB3300

Hi-Speed Analogw/ OTG

ULPIDigitalLogic

USB Connector(Standard or Mini)

ULPI LINK DM

VBUS

DP

IDSTP

CLK

DIR

NXTDATA[7:0]

32 Pin QFN



Datasheet

Figure 1.2 ULPI Interface Features as Related to UTMI+

UTMI+ Level 0Hi-Speed Peripherals Only

ADD

ED

FEA

TUR

ES

USB3300ULPI

Hi-Speed Peripheral, host controllers, On-the-Go devices with 12 pin interface(HS, FS, LS, preamble packet)

UTMI+ Level 3Hi-Speed Peripheral, host controllers, On-

the-Go devices(HS, FS, LS, preamble packet)

UTMI+ Level 2Hi-Speed Peripheral, host controllers, On-

the-Go devices(HS, FS, and LS but no preamble packet)

UTMI+ Level 1Hi-Speed Peripheral, host controllers,

and On-the-Go devices(HS and FS Only)

USB3500USB3450

USB3280USB3250



Datasheet


Chapter 2 Functional Overview

The USB3300 is a highly integrated USB PHY. It contains a complete Hi-Speed USB 2.0 PHY with theULPI industry standard interface to support fast time to market for a USB product. The USB3300 iscomposed of the functional blocks shown in Figure 2.1 below. Details of these individual blocks aredescribed in Chapter 6, "Architecture Overview," on page 19.

Figure 2.1 USB3300 Block Diagram

ULPI Digital

OTG Module

DATA[7:0]

24 MHz XTAL

Internal Regulator &

POR

5VPower

Supply

Bias Gen.

CLKOUT

NXT

DIR

STP

VDD3.3 XTAL & PLL

XI CPEN

VBUS

ID

VDD3.3

DPDM

USB3300

VD

D1.

8

VDD

A1.

8 mX

O

RBIAS

EXTVBUSFAULT

Mini-ABUSB

Connector

HS XCVR

FS/LS XCVR

Resistors

Rpu

_dp

Rpd

_dm

Rpd

_dp

Rpu

_dm

EN


Datasheet

Chapter 3 Pin Layout

The USB3300 is offered in a 32 pin QFN package (5 x 5 x 0.9mm). The pin definitions and locationsare documented below.

3.1 USB3300 Pin Diagram

The exposed flag of the QFN package must be connected to ground with a via array to the groundplane. This is the main ground connection for the USB3300.

3.2 Pin Function

Figure 3.1 USB3300 Pin Diagram - Top View

Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package

PIN NAMEDIRECTION,

TYPE ACTIVELEVEL DESCRIPTION

1 GND Ground N/A Ground

2 GND Ground N/A Ground

3 CPEN Output,CMOS

High External 5 volt supply enable. This pin is used to enable the external Vbus power supply. The CPEN pin is low on POR.

GND

GND

CPEN

VBUS

ID

VDD3.3

DM

DP

RE

SET

EXT

VBU

S

NX

T

DIR

STP

CLK

OU

T

VD

D3.

3

VD

D1.

8

DATA0

DATA7

DATA5

DATA6

DATA2

DATA3

DATA4

DATA1

RB

IAS

VD

D3.

3

XO

VD

D1.

8

VD

D3.

3

VD

DA1

.8

XI

RE

G_E

N

USB3300Hi-Speed USB2

ULPI PHY32 Pin QFN

1

2

3

4

5

6

7

8

USB3300Hi-Speed USB

ULPI PHY32 Pin QFN

GND FLAG

9 10 11 12 13 14 15 16

24

23

22

21

20

19

18

17

32 31 30 29 28 27 26 25



Datasheet

4 VBUS I/O,Analog

N/A VBUS pin of the USB cable. The USB3300 uses this pin for the Vbus comparator inputs and for Vbus pulsing during session request protocol.

5 ID Input,Analog

N/A ID pin of the USB cable. For non-OTG applications this pin can be floated. For an A-Device ID = 0. For a B-Device ID = 1.

6 VDD3.3 Power N/A 3.3V Supply. A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB.

7 DP I/O,Analog

N/A D+ pin of the USB cable.

8 DM I/O,Analog

N/A D- pin of the USB cable.

9 RESET Input, CMOS High Optional active high transceiver reset. This is the same as a write to the ULPI Reset, address 04h, bit 5. This does not reset the ULPI register set. This pin includes an integrated pull-down resistor to ground. If not used, this pin can be floated or connected to ground (recommended).

See Section 6.1.11, "Reset Pin" for details.

10 EXTVBUS Input, CMOS High External Vbus Detect. Connect to fault output of an external USB power switch or an external Vbus Valid comparator. See Section 6.5.4, "External Vbus Indicator," on page 44 for details. This pin has a pull down resistor to prevent it from floating when the ULPI bit UseExternalVbusIndicator is set to 0.

11 NXT Output,CMOS

High The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle.

12 DIR Output,CMOS

N/A Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up.

13 STP Input,CMOS

High The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle. The STP pin also includes the interface protection detailed in Section 6.1.9.3, "Interface Protection," on page 36.

14 CLKOUT Output,CMOS

N/A 60MHz reference clock output. All ULPI signals are driven synchronous to the rising edge of this clock.

15 VDD1.8 Power N/A 1.8V for digital circuitry on chip. Supplied by On-Chip Regulator when REG_EN is active. Place a 0.1uF capacitor near this pin and connect the capacitor from this pin to ground. Connect pin 15 to pin 26.

Table 3.1 USB3300 Pin Definitions 32-Pin QFN Package (continued)

PIN NAMEDIRECTION,




Datasheet

16 VDD3.3 Power N/A A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB.

17 DATA[7] I/O,CMOS,Pull-low

N/A 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of CLKOUT. DATA[7] is the MSB and DATA[0] is the LSB.


N/A


N/A


N/A


N/A


N/A


N/A


N/A

25 VDD3.3 Power N/A A 0.1uF bypass capacitor should be connected between this pin and the ground plane on the PCB.

26 VDD1.8 Power N/A 1.8V for digital circuitry on chip. Supplied by On-Chip Regulator when REG_EN is active. When using the internal regulators, place a 4.7uF low-ESR capacitor near this pin and connect the capacitor from this pin to ground. Connect pin 26 to pin 15. Do not connect VDD1.8 to VDDA1.8 when using internal regulators. When the regulators are disabled, pin 29 may be connected to pins 26 and 15.

27 XO Output,Analog

N/A Crystal pin. If using an external clock on XI this pin should be floated.

28 XI Input,Analog

N/A Crystal pin. A 24MHz crystal is supported. The crystal is placed across XI and XO. An external 24MHz clock source may be driven into XI in place of a crystal.

29 VDDA1.8 Power N/A 1.8V for analog circuitry on chip. Supplied by On-Chip Regulator when REG_EN is active. Place a 0.1uF capacitor near this pin and connect the capacitor from this pin to ground. When using the internal regulators, place a 4.7uF low-ESR capacitor near this pin in parallel with the 0.1uF capacitor. Do not connect VDD1.8A to VDD1.8 when using internal regulators. When the regulators are disabled, pin 29 may be connected to pins 26 and 15.


PIN NAMEDIRECTION,




Datasheet

30 VDD3.3 Power N/A Analog 3.3 volt supply. A 0.1uF low ESR bypass capacitor connected to the ground plane of the PCB is recommended.

31 REG_EN I/O,CMOS,Pull-low

N/A On-Chip 1.8V regulator enable. Connect to ground to disable both of the on chip (VDDA1.8 and VDD1.8) regulators. When regulators are disabled:

External 1.8V must be supplied to VDDA1.8 and VDD1.8 pins. When the regulators are disabled, VDDA1.8 may be connected to VDD1.8 and a bypass capacitor (0.1uF recommended) should be connected to each pin.The voltage at VDD3.3 must be at least 2.64V (0.8 * 3.3V) before voltage is applied to VDDA1.8 and VDD1.8.

32 RBIAS Analog,CMOS

N/A External 12KΩ +/- 1% bias resistor to ground.

GND FLAG Ground N/A Ground. The flag must be connected to the ground plane with a via array under the exposed flag. This is the main ground for the IC.


PIN NAMEDIRECTION,




Datasheet


Chapter 4 Operational Description

Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanentdamage to the device. Exposure to absolute maximum rating conditions for extended periodsmay affect device reliability.

Table 4.1 Maximum Guaranteed Ratings

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Maximum VBUS, ID, EXTVBUS, DP, and DM voltage to GND

VMAX_5V -0.5 +5.5 V

Maximum VDD1.8 and VDDA1.8 voltage to Ground

VMAX_1.8V -0.5 2.5 V

Maximum 3.3V supply voltage to Ground

VMAX_3.3V -0.5 4.0 V

Maximum I/O voltage to Ground

VMAX_IN -0.5 4.0 V

Operating Temperature TMAX_OP -40 85 °C

Storage Temperature TMAX_STG -55 150 °C

ESD PERFORMANCE

All Pins VHBM Human Body Model ±8 kV

LATCH-UP PERFORMANCE

All Pins ILTCH_UP EIA/JESD 78, Class II 150 mA

Table 4.2 Recommended Operating Conditions


VDD3.3 to GND VDD3.3 3.0 3.3 3.6 V

Input Voltage on Digital Pins

VI 0.0 VDD3.3 V

Voltage on Analog I/O Pins (DP, DM, ID)

VI(I/O) 0.0 VDD3.3 V

VBUS to GND VVBUS 0.0 5.25

Ambient Temperature TA -40 85 C


Datasheet

Chapter 5 Electrical Characteristics

Notes:

VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40C to +85C; unless otherwise specified.

SessEnd and VbusVld comparators disabled. Interface protection disabled.

Maximum current numbers are worst case over supply voltage, temperature and process.

Note: The USB330 uses the AutoResume feature, Section 6.3, for host start-up of less than 1ms

Table 5.1 Electrical Characteristics: Supply Pins

PARAMETER SYMBOL CONDITIONS TYP MAX UNITS

Unconfigured Current IAVG(UCFG) Device Unconfigured Same as Idle mA

FS Idle 3.3V Current IAVG(FS33) FS idle not data transfer 18.8 21.9 mA

FS Idle 1.8V Current IAVG(FS18) FS idle not data transfer 36.4 43.2 mA

FS Transmit 3.3V Current IAVG(FSTX33) FS current during data transmit

36.0 41.6 mA

FS Transmit 1.8V Current IAVG(FSTX18) FS current during data transmit

36.8 43.2 mA

FS Receive 3.3V Current IAVG(FSRX33) FS current during data receive

22.5 27.0 mA

FS Receive 1.8V Current IAVG(FSRX18) FS current during data receive

36.7 43.4 mA

HS Idle 3.3V Current IAVG(HS33) HS idle not data transfer 22.1 25.4 mA

HS Idle 1.8V Current IAVG(HS18) HS idle not data transfer 38.7 45.6 mA

HS Transmit 3.3V Current IAVG(HSTX33) HS current during data transmit

25.4 29.0 mA

HS Transmit 1.8V Current IAVG(HSTX18) HS current during data transmit

39.1 46.2 mA

HS Receive 3.3V Current IAVG(HSRX33) HS current during data receive

23.0 26.6 mA

HS Receive 1.8V Current IAVG(HSRX18) HS current during data receive

39.6 46.8 mA

Low Power Mode 3.3V Current IDD(LPM33) VBUS 15kΩ pull-down and 1.5kΩ pull-up resistor currents not included.

59.4 uA

Low Power Mode 1.8V Current IDD(LPM18) VBUS 15kΩ pull-down and 1.5kΩ pull-up resistor currents not included.

25.5 uA

Table 5.2 Electrical Characteristics: CLKOUT Start-Up


Suspend Recovery Time TSTART 2.25 3.5 ms



Datasheet

Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40C to +85C; unless otherwise specified.

Table 5.3 DC Electrical Characteristics: Logic Pins


Low-Level Input Voltage VIL VSS 0.8 V

High-Level Input Voltage VIH 2.0 VDD3.3 V

Low-Level Output Voltage VOL IOL = 8mA 0.4 V

High-Level Output Voltage VOH IOH = -8mA VDD3.3 - 0.4

V

Input Leakage Current ILI ±10 uA

Pin Capacitance Cpin 4 pF

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM)


FS FUNCTIONALITY

Input levels

Differential Receiver Input Sensitivity

VDIFS | V(DP) - V(DM) | 0.2 V

Differential ReceiverCommon-Mode Voltage

VCMFS 0.8 2.5 V

Single-Ended Receiver Low Level Input Voltage

VILSE 0.8 V

Single-Ended Receiver High Level Input Voltage

VIHSE 2.0 V

Single-Ended Receiver Hysteresis

VHYSSE 0.050 0.150 V

Output Levels

Low Level Output Voltage VFSOL Pull-up resistor on DP;RL = 1.5kΩ to VDD3.3

0.3 V

High Level Output Voltage VFSOH Pull-down resistor on DP, DM;RL = 15kΩ to GND

2.8 3.6 V

Termination

Driver Output Impedance forHS and FS

ZHSDRV Steady state drive 40.5 45 49.5 Ù

Input Impedance ZINP TX, RPU disabled 1.0 MΩ

Pull-up Resistor Impedance ZPU Bus Idle 0.900 1.24 1.575 kΩ

Pull-up Resistor Impedance ZPURX Device Receiving 1.425 2.26 3.09 kΩ

Pull-dn Resistor Impedance ZPD 14.25 15.0 15.75 kΩ



Datasheet


HS FUNCTIONALITY

Input levels

HS Differential Input Sensitivity

VDIHS | V(DP) - V(DM) | 100 mV

HS Data Signaling CommonMode Voltage Range

VCMHS -50 500 mV

HS Squelch Detection Threshold (Differential) VHSSQ

Squelch Threshold 100 mV

Un-squelch Threshold 150 mV

Output Levels

Hi-Speed Low LevelOutput Voltage (DP/DMreferenced to GND)

VHSOL 45Ω load -10 10 mV

Hi-Speed High LevelOutput Voltage (DP/DMreferenced to GND)

VHSOH 45Ω load 360 440 mV

Hi-Speed IDLE LevelOutput Voltage (DP/DMreferenced to GND)

VOLHS 45Ω load -10 10 mV

Chirp-J Output Voltage (Differential)

VCHIRPJ HS termination resistor disabled, pull-up resistor connected. 45Ω load.

700 1100 mV

Chirp-K Output Voltage(Differential)

VCHIRPK HS termination resistor disabled, pull-up resistor connected. 45Ω load.

-900 -500 mV

Leakage Current

OFF-State Leakage Current ILZ ±10 uA

Port Capacitance

Transceiver Input Capacitance

CIN Pin to GND 5 10 pF

Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM)


FS Output Driver Timing

Rise Time TFSR CL = 50pF; 10 to 90% of|VOH - VOL|

4 20 ns

Fall Time TFFF CL = 50pF; 10 to 90% of|VOH - VOL|

4 20 ns

Output Signal Crossover Voltage

VCRS Excluding the first transition from IDLE state

1.3 2.0 V

Table 5.4 DC Electrical Characteristics: Analog I/O Pins (DP/DM) (continued)




Datasheet


Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40C to +85C; unless otherwise specified

Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -040C to +85C; unless otherwise specified

Differential Rise/Fall Time Matching

FRFM Excluding the first transition from IDLE state

90 111.1 %

HS Output Driver Timing

Differential Rise Time THSR 500 ps

Differential Fall Time THSF 500 ps

Driver Waveform Requirements

Eye pattern of Template 1 in USB 2.0 specification

Hi-Speed Mode Timing

Receiver Waveform Requirements


Data Source Jitter and Receiver Jitter Tolerance


Table 5.6 OTG Electrical Characteristics


SessEnd trip point VSessEnd 0.2 0.5 0.8 V

SessVld trip point VSessVld 0.8 1.4 2.0 V

VBUSVld trip point VVbusVld 4.4 4.58 4.75 V

Vbus Pull-Up RVbusPu Vbus to VDD3.3 (ChargeVbus = 1)

281 340 Ù

Vbus Pull-down RVbusPd Vbus to GND (DisChargeVbus = 1)

656 850 Ù

Vbus Impedance RVbus Vbus to GND 40 75 100 kΩ

ID pull-up resistance RIdPullUp IdPullup = 1 80 100 120 kΩ

ID pull-up resistance RId IdPullup = 0 1 MΩ

STP pull-up resistance RSTP InterfaceProtectDisable = 0 240 330 600 kΩ

Table 5.7 Regulator Output Voltages


VDDA1.8 VDDA1.8 Normal Operation (SuspendM = 1)

1.6 1.8 2.0 V

VDDA1.8 VDDA1.8 Low Power Mode(SuspendM = 0)

0 V

VDD1.8 VDD1.8 1.6 1.8 2.0 V

Table 5.5 Dynamic Characteristics: Analog I/O Pins (DP/DM) (continued)




Datasheet

Chapter 6 Architecture Overview

The USB3300 architecture can be broken down into the following blocks shown in Figure 6.1,"Simplified USB3300 Architecture" below.

6.1 ULPI DigitalThe USB3300 uses the industry standard ULPI digital interface to facilitate communication betweenthe PHY and Link (device controller). The ULPI interface is designed to reduce the number of pinsrequired to connect a discrete USB PHY to an ASIC or digital controller. For example, a full UTMI+Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals.

The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI)Specification” document (www.ulpi.org). The following sections highlight the key operating modesof the USB3300 digital interface.

Figure 6.1 Simplified USB3300 Architecture

ULPI Digital

OTGModule

DATA[7:0]

InternalRegulator &

POR

BiasGen.

CLKOUT

NXT

DIR

STP

VDD3.3 XTAL &PLL

XI

CPE

N

VBUS

ID

VDD3.3

DPDM

USB3300

VD

D1.

8

VDD

A1.

8

XO

RBIAS

EXTV

BU

S

HS XCVR

FS/LSXCVR

ResistorsR

pu_d

p

Rpd

_dm

Rpd

_dp

Rpu

_dm



Datasheet

6.1.1 Overview

Figure 6.2 illustrates the block diagram of the ULPI digital functions. It should be noted that this PHYdoes not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.

The advantage of a “wrapper less” architecture is that the PHY has a lower USB latency than a designwhich must first register signals into the PHY’s wrapper before the transfer to the PHY core. A lowlatency PHY allows a Link to use a wrapper around a UTMI Link and still make the required USB turn-around timing given in the USB 2.0 specification.

RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 high speed clocks. USB3300uses a low latency high speed receiver path to lower the RxEndDelay to 43 high speed clocks. Thislow latency design gives the Link more cycles to make decisions and reduces the Link complexity. Thisis the result of the “wrapper less” architecture of the USB3300. This low RxEndDelay should allowlegacy UTMI Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface.

Figure 6.2 ULPI Digital Block Diagram

Data[7:0]

Interrupt Control

High Speed TXFull Speed TXLow Speed TX

High Speed DataRecovery

Full / Low Speed Data Recovery

ULPI Protocol Block

6pinSerial Mode

XcvrSelect[1:0]TermSelectOpMode[1:0]Reset

SuspendM

3pinSerial ModeClockSuspendMAutoResume

Indicator ComplementIndicator Pass Thru

Interface Protect Disable

IdPullUpDpPulldownDmPulldownDischrgVbusChrgVbusDrvVbusDrvVbusExternalUseExternal Vbus Indicator

InterruptEnable Rise[4:0]InterruptEnableFall[4:0]

InterruptStatus[4:0]InterruptLatch[4:0]

Linestates[1:0]

VbusValidSessionValidSessionEnd

HS Tx Data

FS/LS Tx Data

HS RX Data

FS/LS Data

NOTE:The USB3300 uses a wrapperless ULPI interface.

DIR

NXT

STP

Tx Data

Rx Data

POR

ULPI Register Array

HostDisconnect

IdGnd

To OTG Module

Transceiver ControlModule

To USB Transceiver

From OTG Module

To USB Transceiver

RXD CMD

From USB Transceiver



Datasheet

In Figure 6.2, "ULPI Digital Block Diagram", a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link addresses the PHY. The Link must use the DIR output to determinedirection of the ULPI data bus. The USB3300 is the “bus arbitrator”. The ULPI Protocol Block will routedata/commands to the transmitter or the ULPI register array.

6.1.2 ULPI Interface Signals

UTMI+ Low Pin Interface (ULPI) uses 12-pins to connect a full OTG Host / Device PHY to an SOC.A reduction of external pins on the PHY is accomplished by realizing that many of the relatively staticconfiguration pins (xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown DmPulldown to list afew,) can be implemented by having a internal static register array.

An 8-bit bi-directional data bus clocked at 60Mhz allows the Link to access this internal register arrayand transfer USB packets to and from the PHY. The remaining 3 pins function to control the data flowand arbitrate the data bus.

Direction of the 8-bit data bus is control by the DIR output from the PHY. Another output NXT is usedto control data flow into and out of the device. Finally, STP, which is in input to the PHY, terminatestransfers and is used to start up and resume from a suspend state.

The 12 signals are described below in Table 6.1, "ULPI Interface Signals".

USB3300 implements a Single Data Rate (SDR) ULPI interface with all data transfers happening onthe rising edge of the CLKOUT. CLKOUT is supplied by the PHY.

The ULPI interface supports the two basic modes of operation, Synchronous Mode and Low PowerMode. Synchronous Mode with the signals all changing relative to the 60MHz clockout. Low PowerMode where the clock is off in a suspended state and the lower two bits of the data bus contain thelinestate[1:0] signals. ULPI adds to Low Power Mode, an interrupt output which permits the Link toreceive an asynchronous interrupt when the OTG comparators, or ID pin change state.

In Synchronous Mode operation, data is transferred on the rising edge of CLKOUT. Direction of thedata bus is determined by the state of DIR. When DIR is high, the PHY is driving DATA[7:0]. WhenDIR is low, the Link is driving DATA[7:0].

Table 6.1 ULPI Interface Signals

SIGNAL DIRECTION DESCRIPTION

CLKOUT OUT 60MHz reference clock output. All ULPI signals are driven synchronous to the rising edge of this clock.

DATA[7:0] I/O 8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI defines interface timing for a single-edge data transfers with respect to rising edge of CLKOUT.

DIR OUT Controls the direction of the data bus. When the PHY has data to transfer to the Link, it drives DIR high to take ownership of the bus. When the PHY has no data to transfer it drives DIR low and monitors the bus for commands from the Link. The PHY will pull DIR high whenever the interface cannot accept data from the Link, such as during PLL start-up.

STP IN The Link asserts STP for one clock cycle to stop the data stream currently on the bus. If the Link is sending data to the PHY, STP indicates the last byte of data was on the bus in the previous cycle.

NXT OUT The PHY asserts NXT to throttle the data. When the Link is sending data to the PHY, NXT indicates when the current byte has been accepted by the PHY. The Link places the next byte on the data bus in the following clock cycle.



Datasheet

Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the databus for one clock cycle. During the “turn–around“cycle, the state of DATA[7:0] is unknown and the PHYwill not read the data bus.

Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USBtransmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on thedatabus by the Link layer.

6.1.3 ULPI Interface Timing

The control and data timing relationships are given in Figure 6.3, "ULPI Timing Diagram" and Table 6.2,"ULPI Interface Timing". The USB300 PHY provides CLKOUT and all timing is relative to the risingclock edge. The timing relationships detailed below apply to Synchronous Mode only.

Note: VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40C to 85C; unless otherwise specified.

6.1.4 ULPI Register Array

The USB3300 PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification.The complete USB3300 ULPI register set is shown in Table 6.3, "ULPI Register Map". All registers are8 bits. This table also includes the default states of the register upon POR. The RESET bit in the

Figure 6.3 ULPI Timing Diagram

Table 6.2 ULPI Interface Timing

PARAMETER SYMBOL MIN MAX UNITS

Setup time (control in, 8-bit data in) TSC,TSD 5.0 ns

Hold time (control in, 8-bit data in) THC, THD 0 ns

Output delay (control out, 8-bit data out) TDC, TDD 2.0 5.0 ns

Clock Out -CLKOUT

Control In -STP

Data In -DATA[7:0]

Control Out -DIR, NXT

Data Out -DATA[7:0]

TSC

TSD

THC

THD

TDC TDC

TDD



Datasheet

Function Control Register does not reset the bits of the ULPI register array. The Link should not reador write to any registers not listed in this table.

6.1.4.1 Vendor ID Low: Address = 00h (read only)

6.1.4.2 Vendor ID High: Address = 01h (read only)

Table 6.3 ULPI Register Map

REGISTER NAMEDEFAULT

STATE

ADDRESS (6BIT)

READ WRITE SET CLEAR

Vendor ID Low 24h 00h - - -

Vendor ID High 04h 01h - - -

Product ID Low 04h 02h - - -

Product ID High 00h 03h - - -

Function Control 41h 04-06h 04h 05h 06h

Interface Control 00h 07-09h 07h 08h 09h

OTG Control 06h 0A-0Ch 0Ah 0Bh 0Ch

USB Interrupt Enable Rising 1Fh 0D-0Fh 0Dh 0Eh 0Fh

USB Interrupt Enable Falling 1Fh 10-12h 10h 11h 12h

USB Interrupt Status 00h 13h - - -

USB Interrupt Latch 00h 14h - - -

Debug 00h 15h - - -

Scratch Register 00h 16-18h 16h 17h 18h

FIELD NAME BIT DEFAULT DESCRIPTION

Vendor ID Low 7:0 24h SMSC Vendor ID


Vendor ID High 7:0 04h SMSC Vendor ID



Datasheet

6.1.4.3 Product ID Low: Address = 02h (read only)

6.1.4.4 Vendor ID Low: Address = 03h (read only)

6.1.4.5 Function Control: Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)


Product ID Low 7:0 04h SMSC Product ID revision A0


Product ID High 7:0 00h SMSC Product ID revision A0


XcvrSelect[1:0] 1:0 01b Selects the required transceiver speed.00b: Enables HS transceiver01b: Enables FS transceiver10b: Enables LS transceiver11b: Enables FS transceiver for LS packets (FS preamble automatically pre-pended)

TermSelect 2 0b Controls the DP and DM termination depending on XcvrSelect, OpMode, DpPulldown, and DmPulldown. The Dp and DM termination is detailed in Table 6.8, "DP/DM termination vs. Signaling Mode".

OpMode 4:3 00b Selects the required bit encoding style during transmit.00b: Normal Operation01b: Non-Driving10b: Disable bit-stuff and NRZI encoding11b: Reserved

Reset 5 0b Active high transceiver reset. This reset does not reset the ULPI interface or register set. Automatically clears after reset is complete.

SuspendM 6 1b Active low PHY suspend. When cleared the PHY will enter Low Power Mode as detailed in Section 6.1.9, "Low Power Mode". Automatically set when exiting Low Power Mode.

Reserved 7 0b Driven low.



Datasheet

6.1.4.6 Interface Control: Address = 07-09h (read), 07h (write), 08h (set), 09h (clear)

6.1.4.7 OTG Control: Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear)


6-pin FsLsSerialMode 0 0b Changes the ULPI interface to a 6-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode.

3-pin FsLsSerialMode 1 0b Changes the ULPI interface to a 3-pin Serial Mode. The PHY will automatically clear this bit when exiting serial mode.

Reserved 2 0b Driven low.

ClockSuspendM 3 0b Enables Link to turn on 60MHz CLKOUT in serial mode.0b: Disable clock in serial mode.1b: Enable clock in serial mode.

AutoResume 4 0b Only applicable in Host mode. Enables the PHY to automatically transmit resume signaling. This function is detailed in Section 6.1.7.4, "Host Resume K".

IndicatorComplement 5 0b Inverts the EXTVBUS signal. This function is detailed in Section 6.5.4, "External Vbus Indicator".

IndicatorPassThru 6 0b Disables anding the internal VBUS comparator with the EXTVBUS input when asserted. This function is detailed in Section 6.5.4.

InterfaceProtectDisable 7 0b Used to disable the integrated STP pull-up resistor used for interface protection. This function is detailed in Section 6.1.9.3, "Interface Protection".


IdPullup 0 0b Connects a pull-up resistor from the ID pin to VDD3.30b: Disables the pull-up resistor1b: Enables the pull-up resistor

DpPulldown 1 1b Enables the 15k Ohm pull-down resistor on DP.0b: Pull-down resistor not connected to DP1b: Pull-down resistor connected to DP

DmPulldown 2 1b Enables the 15k Ohm pull-down resistor on DM.0b: Pull-down resistor not connected to DM1b: Pull-down resistor connected to DM

DischrgVbus 3 0b This bit is only used during SRP. Connects a resistor from VBUS to ground to discharge VBUS. 0b: disconnect resistor from VBUS to ground1b: connect resistor from VBUS to ground

ChrgVbus 4 0b This bit is only used during SRP. Connects a resistor from VBUS to VDD3.3 to charge VBUS above the SessValid threshold.0b: disconnect resistor from VBUS to VDD3.31b: connect resistor from VBUS to VDD3.3



Datasheet

6.1.4.8 USB Interrupt Enable Rising: Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear)

6.1.4.9 USB Interrupt Enable Falling: Address = 10-12h (read), 10h (write), 11h (set), 12h (clear)

DrvVbus 5 0b Used to enable external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbusExternal.0b: do not drive VBUS1b: drive VBUS

DrvVbusExternal 6 0b Used to enable external 5 volt supply to drive 5 volts on VBUS. This signal is or’ed with DrvVbus.0b: do not drive VBUS1b: drive VBUS

UseExternalVbusIndicator

7 0b Tells the PHY to use an external VBUS over-current or voltage indicator. This function is detailed in Section 6.5.4, "External Vbus Indicator".0b: Use the internal VbusValid comparator1b: Use the EXTVBUS input as for VbusValid signal.


HostDisconnect Rise 0 1b Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode.

VbusValid Rise 1 1b Generate an interrupt event notification when Vbusvalid changes from low to high.

SessValid Rise 2 1b Generate an interrupt event notification when SessValid changes from low to high.

SessEnd Rise 3 1b Generate an interrupt event notification when SessEnd changes from low to high.

IdGnd Rise 4 1b Generate an interrupt event notification when IdGnd changes from low to high.

Reserved 7:5 0h Driven low.


HostDisconnect Fall 0 1b Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode.

VbusValid Fall 1 1b Generate an interrupt event notification when Vbusvalid changes from high to low.

SessValid Fall 2 1b Generate an interrupt event notification when SessValid changes from high to low.




Datasheet

6.1.4.10 USB Interrupt Status Register: Address = 13h (read only with auto clear)

6.1.4.11 USB Interrupt Status: Address = 14h (read only with auto clear)

SessEnd Fall 3 1b Generate an interrupt event notification when SessEnd changes from high to low.

IdGnd Fall 4 1b Generate an interrupt event notification when IdGnd changes from high to low.



HostDisconnect 0 0b Current value of the UTMI+ Hostdisconnect output. Applicable only in host mode.

VbusValid 1 0b Current value of the UTMI+ Vbusvalid output.

SessValid 2 0b Current value of the UTMI+ SessValid output.

SessEnd 3 0b Current value of the UTMI+ SessEnd output.

IdGnd 4 0b Current value of the UTMI+ IdGnd output.



HostDisconnect Latch 0 0b Set to 1b by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode.

VbusValid Latch 1 0b Set to 1b by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read.

SessValid Latch 2 0b Set to 1b by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read.

SessEnd Latch 3 0b Set to 1b by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read.

IdGnd Latch 4 0b Set to 1b by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read.





Datasheet

6.1.4.12 Debug Register: Address = 15h (read only)

6.1.4.13 Scratch Register: Address = 16-18h (read), 16h (write), 17h (set), 18h (clear)

6.1.4.14 Carkit Register Access

The Carkit registers are reserved for SMSC testing and should not be written to or read by the Link.

6.1.4.15 Extended Register Access

The extended registers are reserved for SMSC testing and should not be written to or read by the Link.

6.1.4.16 Vendor Register Access

The vendor specific registers are reserved for SMSC testing and should not be written to or read bythe Link. The vendor specific registers include the range from 30h to 3Fh.

6.1.5 ULPI Register Access

A command from the Link begins a ULPI transfer from the Link to the USB3300. Anytime the Linkwants to write or read a ULPI register, the Link will need to wait until DIR is low, and then send aTransmit Command Byte (TXD CMD) to the PHY. The TXD CMD byte informs the PHY of the type ofdata being sent. The TXD CMD is followed by the a data transfer to or from the PHY. Table 6.4, "ULPITXD CMD Byte Encoding" gives the TXD command byte (TXD CMD) encoding for the USB3300. Theupper two bits of the TX CMD instruct the PHY as to what type of packet the Link is transmitting.


Linestate0 0 0b Contains the current value of Linestate[0].

Linestate1 1 0b Contains the current value of Linestate[1].

Reserved 7:2 000000b Driven low.


Scratch 7:0 00h Empty register byte for testing purposes. Software can read, write, set, and clear this register and the PHY functionality will not be affected.

Table 6.4 ULPI TXD CMD Byte Encoding

COMMAND NAMECMD

BITS[7:6] CMD BITS[5:0] COMMAND DESCRIPTION

Idle 00b 000000b ULPI Idle

Transmit 01b 000000b USB Transmit Packet with No Packet Identifier (NOPID)

00XXXXb USB Transmit Packet Identifier (PID) where DATA[3:0] is equal to the 4-bit PID. P3P2P1P0 where P3 is the MSB.



Datasheet

6.1.5.1 ULPI Register Write

A ULPI register write operation is given in Figure 6.4. The TXD command with a register writeDATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of theTXD CMD byte.

To write to a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the databus.At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the registerdata. At T4 the PHY will accept the register data and the Link will drive an Idle on the bus and driveSTP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the registerand drive NXT low. The Link will pull STP low.

NXT is used to control when the Link drives the register data on the bus. DIR is low throughout thistransaction since the PHY is receiving data from the Link. STP is used to end the transaction and datais registered after the de-assertion of STP. After the write operation completes, the Link must drive aULPI Idle (00h) on the data bus or the USB3300 may decode the bus value as a ULPI command.

Register Write 10b XXXXXXb Immediate Register Write Command whereDATA[5:0] = 6-bit register address

Register Read 11b XXXXXXb Immediate Register Read Command whereDATA[5:0] = 6-bit register address

Figure 6.4 ULPI Register Write

Table 6.4 ULPI TXD CMD Byte Encoding (continued)

COMMAND NAMECMD

BITS[7:6] CMD BITS[5:0] COMMAND DESCRIPTION

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD (reg write) Idle Reg Data[n] Idle

ULPI Register Reg Data [n-1] Reg Data [n]

T0 T1 T2 T3 T5T4 T6



Datasheet

6.1.5.2 ULPI Register Read

A ULPI register read operation is given in Figure 6.5. The Link drives a TXD CMD byte with DATA[7:6]= 11h for a register read. DATA[5:0] of the ULPI TXD command bye contain the register address.

At T0, the Link will place the TXD CMD on the databus. At T2, the PHY will bring NXT high, signalingthat the Link it is ready to accept the data transfer. At T3, the PHY reads the TXD CMD, determinesit is a register read, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. AtT4, the bus ownership has transferred back to the PHY and the PHY drives the requested registeronto the databus. At T5, the Link will read the databus and the PHY will drop DIR low returning controlof the bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6.

6.1.6 ULPI RXD CMD

The Link needs several more important states of information which were provided by the linestate[1:0],rxactive, rxvalid and rxerror. When an implementing the OTG functions the Vbus and ID pin statesmust also be transferred into the Link.

ULPI defines a Receive Command Byte (RXD CMD) that contains this information. The Encoding ofthe RXD CMD byte is given in the Table 6.5, "ULPI RX CMD Encoding".

Transfer of the RXD CMD byte occurs when in Synchronous Mode when the PHY has control of thebus. Transfers of the RXD CMD occur after: a transmit cmd has issued STP, a linestate change whennot transmitting, a USB receive, or an interrupt event occurs.

In Figure 6.2, "ULPI Digital Block Diagram", the ULPI Protocol Block determines when to send an RXDCMD. When a linestate change occurs the RXD CMD is sent immediately if the DIR output is low.

When a USB Receive is occurring RXD CMDs are sent when ever NXT = 0 and DIR = 1. When aUSB Transmit occurs the RXD CMDs are returned to the Link after the STP is asserted ending theLink to USB3300 transfer of the bytes to be sent on the transmit.

To summarize a RXD CMD transfer occurs:

when DIR is low and a linestate change occurs.

when Vbus and/or ID comparators change state.

Figure 6.5 ULPI Register Read

DIR

CLK

DATA[7:0]

STP

NXT

Txd Cmd Reg Read Idle

T0

Reg DataTurn around Turn around

T1 T2 T3 T4 T5 T6

Idle



Datasheet

during a USB receive when NXT is low.

after STP is asserted during a USB transmit cmd.

Notes:

1. An ‘X’ is a do not care and can be either a logic 0 or 1.

2. The value of VbusValid is defined in Table 6.10, "External Vbus Indicator Logic".

6.1.7 USB3300 Transmitter

The USB3300 ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6.2, "ULPIDigital Block Diagram" shows the high speed, full speed, and low speed transmitter block controlledby ULPI Protocol Block. Encoding of the USB packet follows the bit-stuffing and NRZI outlined in theUSB 2.0 specification. Many of these functions are re-used between the high speed and full/low speedtransmitters. When using the USB3300, Table 6.8, "DP/DM termination vs. Signaling Mode" shouldalways be used as a guideline on how to configure for various modes of operation. The transmitterdecodes the inputs of Xcvrselect, Termselect, opmodes, DpPulldown and DmPulldown to determinewhat operation is expected. Users must strictly adhere to the modes of operation given in Table 6.8.

Several important functions for a device and host are designed in the transmitter blocks.

Table 6.5 ULPI RX CMD Encoding

DATA[7:0] NAME DESCRIPTION AND VALUE

[1:0] Linestate UTMI Linestate SignalsDATA[1] = Linestate[1]DATA[0] = Linestate[0]

[3:2] Encoded Vbus State

ENCODED VBUS VOLTAGE STATES

VALUE VBUS VOLTAGE SESSEND SESSVLD VBUSVLD2

00 VVBUS < VSESS_END 1 0 0

01 VSESS_END < VVBUS < VSESS_VLD

0 0 0

10 VSESS_VLD < VVBUS < VVBUS_VLD

X 1 0

11 VVBUS_VLD < VVBUS X X 1

[5:4] Rx Event Encoding

ENCODED UTMI EVENT SIGNALS

VALUE RXACTIVE RXERROR HOSTDISCONNECT

00 0 0 0

01 1 0 0

11 1 1 0

10 X X 1

[6] State of ID pin

Set to the logic state of the ID pin. A logic low indicates an A device. A logic high indicates a B device.

[7] Reserved Always



Datasheet

The USB3300 transmitter will transmit a 32-bit long high speed synch before every high speed packet.In full and low speed modes a 8-bit synch is transmitted.

When the device or host needs to chirp for high speed port negotiation, the Opmode Bits=10 will turnoff the bit-stuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB3300 Opmoderegister bits should be changed only after the RXCMD linestate encoding indicates that the transmitterhas completed transmitting. Should the opmode be switched to normal bit-stuffing and NRZI encodingbefore the transmit pipeline is empty, the remaining data in the pipeline may be transmitted in an bit-stuff encoding format.

Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp.

6.1.7.1 High Speed Long EOP

When operating as a Hi-Speed host, the USB3300 will automatically generate a 40 bit long End ofPacket (EOP) after a SOF PID (A5h). The USB3300 determines when to send the 40-bit long EOP bydecoding the ULPI TXD CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when theDpPulldown and DmPulldown bits are asserted. The Hi-Speed 40-bit long EOP is used to detect adisconnect in high speed mode.

In device mode, the USB3300 will not send a long EOP after a SOF PID.

6.1.7.2 Low Speed Keep-Alive

Low speed keep alive is supported by the USB3300. When in Low speed (10b), the USB3300 will sendout two Low speed bit times of SE0 when a SOF PID is received.

6.1.7.3 UTMI+ Level 3

Pre-amble is supported for UTMI+ Level 3 compatibility. When Xcvrselect is set to (11b) in host mode,(dpPulldown and dmPulldown both asserted) the USB3300 will pre-pend a full speed pre-amble beforethe low speed packet. Full speed rise and fall times are used in this mode. The pre-amble consists ofthe following: Full speed sync, the encoded pre-PID (C3h) and then full speed idle (DP=1 and DM =0). A low speed packet follows with a sync, data and a LS EOP.

6.1.7.4 Host Resume K

Resume K generation is supported by the USB3300. When the USB3300 exits the suspended lowpower state, the USB3300, when operating as a host, will transmit a K on DP/DM. The transmitterswill end the K with SE0 for two Low Speed bit times. If the USB3300 was operating in high speedmode before the suspend, the host must change to high speed mode before the SE0 ends. SE0 istwo low speed bit times which is about 1.2 us.

The ULPI specification has an explicit discussion of the resume sequence and the order of operationsrequired.

In device mode, the resume K will not append a SE0 but release the DP/ DM lines to allow the pullup to return the bus to the correct idle state, depending upon the operational mode of the USB3300.Refer to Table 6.8, "DP/DM termination vs. Signaling Mode".

6.1.7.5 No SYNC and EOP Generation (Opmode 11) (optional)

UTMI+ defines an opmode 11 where no sync and EOP generation occurs in Hi-Speed operation. Thisis an option to the ULPI specification and not implemented in the USB3300.

6.1.7.6 Typical USB Transmit with ULPI

Figure 6.6, "ULPI Transmit" shows a typical USB transmit sequence. A transmit sequence starts by theLink sending a TXD CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMDwith the PID is followed by transmit data. Form the time the data is clocked into the transmitter it willappear at DP and DM 11 high speed bit times later. This time is the HS_TX_START_DELAY.



Datasheet

During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB3300pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link willhold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP whileNXT is asserted. (Note that the Link cannot assert STP with NXT de-asserted since the USB3300 isexpecting to fetch another byte from the Link in this state).

Once, the USB3300 completes transmitting, the DP/DM lines return to idle and an RXD CMD isreturned to the Link so the inter-packet timers may be updated by linestate.

In the case of Full Speed or Low Speed, once STP is asserted each FS/LS bit transition will generatea RXD CMD since the bit times are relatively slow.

6.1.8 USB3300 Receiver

The USB3300 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes thereceiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol,a received packet has the priority and will immediately follow register reads and RXD CMD transfers.Figure 6.7, "ULPI Receive" shows a basic USB packet received by the USB3300 over the ULPIinterface.

Figure 6.6 ULPI Transmit

DATA[7:0]

DP/DM

DIR

CLK

STP

NXT

TXD CMD (USB tx) Idle D0 D2 D3 IDLE

SE0 !SQUELCH SE0

Turn Around

Turn Around

RXD CMDD1



Datasheet

In Figure 6.7, "ULPI Receive" the PHY asserts DIR to take control of the data bus from the Link. Theassertion of DIR and NXT in the same cycle contains additional information that Rxactive has beenasserted. When NXT is de-asserted and DIR is asserted, the RXD CMD data is transferred to the Link.After the last byte of the USB receive packet is transferred to the PHY, the linestate will return to idle.

The ULPI full speed receiver operates according to the UTMI/ULPI specification. In the full speed case,the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is lowwith DIR high, the RXD CMD is driven on the data bus.

In full speed, the USB3300 will not issue a Rxactive de-assertion in the RXD CMD until the DP/DMlinestate transition to idle. This prevents the Link from violating the two full speed bit times minimumturn around time.

6.1.8.1 Disconnect Detection

A High Speed host must detect a disconnect by sampling the transmitter outputs during the long EOPtransmitted during a SOF packet. The USB3300 only looks for a high speed disconnect during the longEOP where the period is long enough for the disconnect reflection to return to the host PHY. When ahigh speed disconnect occurs the USB3300 will return a RXD CMD and set the host disconnect bit inthe ULPI interrupt status register (address 13h).

When in FS or LS modes, the Link is expected to handle all disconnect detection.

6.1.9 Low Power Mode

Low Power Mode is a power down state to save current when the USB session is suspended. TheLink controls when the PHY is placed into or out of Low Power Mode. In Low Power Mode all of thecircuits are powered down except the interface pins, full speed receiver, VBUS comparators, and IDcomparator.

6.1.9.1 Entering Low Power/Suspend Mode

To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function ControlRegister. Once this write is complete, the PHY will assert DIR high and after five rising edges ofCLKOUT, drive the clock low. Once the clock is stopped, the PHY will enter a low power state toconserve current.

Figure 6.7 ULPI Receive

DIR

CLK

DATA[7:0]

STP

NXT

Rxd Cmd Idle Turn

around PID D1 Rxd Cmd D2 Turn

around



Datasheet

While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate andthe Vbus voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6.6, "Interface SignalMapping During Low Power Mode". Linestate[1:0] is the combinational output of the full speedreceivers. The “int” or interrupt signal indicates an unmasked interrupt has occurred. When anunmasked interrupt or linestate change has occurred, the Link is notified and can determine if it shouldwake-up the PHY.

An unmasked interrupt can be caused by the following comparators changing state, VbusVld, SessVld,SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and either theirrising or falling edge interrupt is enabled, DATA[3] will assert. During Low Power Mode, the VbusVldand SessEnd comparators can have their interrupts masked to lower the suspend current. Refer toSection 6.1.9.4, "Minimizing Current in Low Power Mode".

While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks arestopped during Low Power Mode.

Figure 6.8 Entering Low Power Mode

Table 6.6 Interface Signal Mapping During Low Power Mode

SIGNAL MAPS TO DIRECTION DESCRIPTION

linestate[0] DATA[0] OUT Combinatorial linestate[0] driven directly by FS analog receiver.

linestate[1] DATA[1] OUT Combinatorial linestate[1] driven directly by FS analog receiver.

reserved DATA[2] OUT Driven Low

int DATA[3] OUT Active high interrupt indication. Must be asserted whenever any unmasked interrupt occurs.

reserved DATA[7:4] OUT Driven Low

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD (reg write) Idle Reg Data[n] Idle

T0 T1 T2 T3 T5T4 T6 T10

TurnAround Low Power Mode

SUSPENDM(ULPI Register Bit)

...



Datasheet

6.1.9.2 Exiting Low Power Mode

To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3300 will beginits start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT andde-assert DIR. Once DIR has been de-asserted, the Link can de-assert STP when ready and startoperating in Synchronous Mode. The PHY will automatically set the SuspendM bit to a 1 in theFunction Control register.

The time from T0 to T1 is given in Table 5.2, “Electrical Characteristics: CLKOUT Start-Up,” onpage 15.

Should the Link de-assert STP before DIR is de-asserted, the USB3300 will detect this as a falseresume request and return to Low Power Mode. This is detailed in section 3.9.4 of the ULPI 1.1specification.

6.1.9.3 Interface Protection

ULPI protocol assumes that both the Link and PHY will keep the ULPI data bus driven by either theLink when DIR is low or the PHY when DIR is high. The only exception is when DIR has changedstate and a turn around cycle occurs for 1 clock period.

In the design of a USB system, there can be cases where the Link may not be driving the ULPI busto a known state while DIR is low. Two examples where this can happen is because of a slow Linkstart-up or a hardware reset.

START UP PROTECTION

Upon start-up, when the PHY de-asserts DIR, the Link must be ready to receive commands and driveIdle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STPbefore DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If theLink doesn’t assert STP before it can receive commands, the PHY may interpret the databus state asa TX CMD and transmit invalid data onto the USB bus, or make invalid register writes.

A Link should be designed to have the default POR state of the STP output high and the data bus tri-stated. The USB3300 has weak pull-downs on the DATA bus to prevent these inputs from floatingwhen not driven.

Figure 6.9 Exiting Low Power Mode

DIR

CLK

DATA[7:0]

STP

NXT

TURNAROUND LOW

POWER MODEDATA BUS IGNORED (SLOW LINK)

IDLE (FAST LINK) IDLE

T0 T1 T2 T3 T5T4

Slow Link Drives Bus Idle and STP lowFast Link Drives Bus

Idle and STP low

...

Note: Not to Scale



Datasheet

In some cases, a Link may be software configured and not have control of its STP pin until after thePHY has started. In this case, the USB3300 has an internal pull-up on the STP input pad which willpull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on PORand can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register.

The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STPhigh. Once the Link completes its start-up, STP can be synchronously driven low.

A Link design which drives STP high during POR can disable the pull-up resistor on STP by settingInterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low PowerMode, STP is held low, which would draw current through the pull-up resistor on STP.

WARM RESET

Designers should also consider the case of a warm restart of a Link with a PHY in Low Power Mode.Once the PHY enters Low Power Mode, DIR is asserted and the clock is stopped. The USB3300 looksfor STP to be asserted to re-start the clock and then resume normal synchronous operation.

Should the USB3300 be suspended in Low Power Mode, and the Link receives a hardware reset,provision is made to allow the PHY to recover from Low Power Mode and start its clock. If the Linkasserts STP on reset, the PHY will exit Low Power Mode and start its clock.

If the Link does not assert STP on reset the interface protection pull-up can be used. When the Linkis reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the PHY torestart its clock.

6.1.9.4 Minimizing Current in Low Power Mode

In order to minimize the suspend current in Low Power Mode, the OTG comparators can be disabledto reduce suspend current. During suspend, the VbusVld and SessEnd comparators are not neededand can be disabled using the USB Interrupt Enable Rise and USB Interrupt Enable Fall registers. Bydisabling the interrupt in BOTH the rise and fall registers, the SessEnd and VbusVld comparators areturned off. When exiting suspend, the Link should immediately re-enable the comparators if host orOTG functionality is needed.

In addition to disabling the OTG comparators in suspend, the Link may choose to disable the InterfaceProtect Circuit. By setting the Interface Control, bit 7, InterfaceProtectDisable high, the Link can disablethe pull-up resistor on STP.

6.1.10 Full Speed/Low Speed Serial Modes

The USB3300 includes two serial modes to support legacy Links which use either the 3pin or 6pinserial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialModeor the 3-pin FsLsSerialMode bit in the Interface control register. The 6-pin Serial Mode is provided forlegacy link designs and is not recommended for new designs.

The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writesthe Interface Control register bit for the specific serial mode. The USB3300 will assert DIR and shutoff the clock after at least five clock cycles. Then the data bus goes to the format of the serial modeselected.

By default, the PHY will shut off the 60MHz clock to conserve power. Should the Link need the 60Mhzclock to continue during the serial mode of operation, the ClockSuspendM bit[3] of the Interface ControlRegister should be set before entering a serial mode. If set, the 60 Mhz clock will be present duringserial modes.

In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source issampled prior to the assertion of DIR and this is compared against the asynchronous level frominterrupt source.

Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signalthe PHY to exit serial mode. Then the PHY can accept a command, DIR is de-asserted and the PHYwill wait until the Link de-asserts STP to resume synchronous ULPI operation.



Datasheet

6.1.10.1 3pin FS/LS Serial Mode

Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.7, "PinDefinitions in 3 pin Serial Mode".

6.1.11 Reset Pin

The reset input of the USB3300 may be asynchronously asserted and de-asserted so long as it is heldin the asserted state continuously for a duration greater than one clkout clock cycle. The reset inputmay be asserted when the USB3300 clkout signal is not active (i.e. in the suspend state caused byasserting the SuspendM bit) but reset must only be de-asserted when the USB3300 clkout signal isactive and the reset has been held asserted for a duration greater than one clkout clock cycle. Noother PHY digital input signals may change state for two clkout clock cycles after the de-assertion ofthe reset signal.

6.2 Hi-Speed USB TransceiverThe SMSC Hi-Speed USB 2.0 Transceiver consists of four blocks in the lower right corner ofFigure 6.1, "Simplified USB3300 Architecture". These four blocks are labeled HS XCVR, FS/LS XCVR,Resistors, and Bias Gen.

6.2.1 High Speed and Full Speed Transceivers

The USB3300 transceiver meets all requirements in the USB 2.0 specification.

The receivers connect directly to the USB cable. This block contains a separate differential receiverfor HS and FS mode. Depending on the mode, the selected receiver provides the serial data streamthrough the multiplexer to the RX Logic block. The FS mode section of the FS/HS RX block alsoconsists of a single-ended receiver on each of the data lines to determine the correct FS linestate. ForHS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is neverinterpreted as data.

The transmitters connect directly to the USB cable. The block contains a separate differential FS andHS transmitter which receive encoded, bit stuffed, serialized data from the TX Logic block and transmitit onto the USB cable.

6.2.2 Termination Resistors

The USB3300 transceiver fully integrates all of the USB termination resistors. The USB3300 includes1.5kΩ pull-up resistors on both DP and DM and a 15kΩ pull-down resistor on both DP and DM. The45Ω high speed termination resistors are also integrated. These resistors require no tuning or trimming

Table 6.7 Pin Definitions in 3 pin Serial Mode

SIGNALCONNECTED

TO DIRECTION DESCRIPTION

tx_enable DATA[0] IN Active High transmit enable

data DATA[1] I/O Tx differential data on DP/DM when tx_enable is highRX differential data from DP/DM when tx_enable is low

se0 DATA[2] I/O Tx SE0 on DP/DM when tx_enable is highRX SE0 from DP/DM when tx_enable is low

interrupt DATA[3] OUT Asserted when any unmasked interrupt occurs. Active high



Datasheet

by the Link. The state of the resistors is determined by the operating mode of the PHY. The possiblevalid resistor combinations are shown in Table 6.8, "DP/DM termination vs. Signaling Mode". Operationis guaranteed in the configurations given in the table below.

RPU_DP_EN activates the 1.5kΩ DP pull-up resistor

RPU_DM_EN activates the 1.5kΩ DM pull-up resistor

RPD_DP_EN activates the 15kΩ DP pull-down resistor

RPD_DM_EN activates the 15kΩ DM pull-down resistor

HSTERM_EN activates the 45Ω DP and DM high speed termination resistors

Table 6.8 DP/DM termination vs. Signaling Mode

SIGNALING MODE

REGISTER SETTINGS RESISTOR SETTINGS

XCVR

SELE

CT[

1:0]

TER

MSE

LEC

T

OPM

OD

E[1:

0]

DPP

ULL

DO

WN

DM

PULL

DO

WN

RPU

_DP_

EN

RPU

_DM

_EN

RPD

_DP_

EN

RPD

_DM

_EN

HST

ERM

_EN

General Settings

Tri-State Drivers XXb Xb 01b Xb Xb 0b 0b 0b 0b 0b

Power-up or Vbus < VSESSEND 01b 0b 00b 1b 1b 0b 0b 1b 1b 0b

Host Settings

Host Chirp 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b

Host Hi-Speed 00b 0b 00b 1b 1b 0b 0b 1b 1b 1b

Host Full Speed X1b 1b 00b 1b 1b 0b 0b 1b 1b 0b

Host HS/FS Suspend 01b 1b 00b 1b 1b 0b 0b 1b 1b 0b

Host HS/FS Resume 01b 1b 10b 1b 1b 0b 0b 1b 1b 0b

Host low Speed 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b

Host LS Suspend 10b 1b 00b 1b 1b 0b 0b 1b 1b 0b

Host LS Resume 10b 1b 10b 1b 1b 0b 0b 1b 1b 0b

Host Test J/Test_K 00b 0b 10b 1b 1b 0b 0b 1b 1b 1b

Peripheral Settings

Peripheral Chirp 00b 1b 10b 0b 0b 1b 0b 0b 0b 0b

Peripheral HS 00b 0b 00b 0b 0b 0b 0b 0b 0b 1b

Peripheral FS 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b

Peripheral HS/FS Suspend 01b 1b 00b 0b 0b 1b 0b 0b 0b 0b

Peripheral HS/FS Resume 01b 1b 10b 0b 0b 1b 0b 0b 0b 0b

Peripheral LS 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b

Peripheral LS Suspend 10b 1b 00b 0b 0b 0b 1b 0b 0b 0b



Datasheet

Note: This is the same as Table 40, Section 4.4 of the ULPI 1.1 specification.

6.2.3 Bias Generator

This block consists of an internal bandgap reference circuit used for generating the driver current andthe biasing of the analog circuits. This block requires an external 12KΩ, 1% tolerance, externalreference resistor connected from RBIAS to ground.

6.3 Crystal Oscillator and PLLThe USB3300 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz referenceclock that is used by the PHY during both transmit and receive. The USB3300 requires a clean 24MHzcrystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHYmay not operate correctly.

The USB3300 can use either a crystal or an external clock oscillator for the 24MHz reference. Thecrystal is connected to the XI and XO pins as shown in the application diagram, Figure 7.1. If a clockoscillator is used the clock should be connected to the XI input and the XO pin left floating. When aexternal clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using anexternal clock the user needs to take care to ensure the external clock source is clean enough to notcorrupt the high speed eye performance.

Once the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHzclock. The USB3300 is guaranteed to start the clock within the time specified in Table 5.2, "ElectricalCharacteristics: CLKOUT Start-Up". The USB3300 does not support using an external 60MHz clockinput.

For Host Applications the USB3300 implements the ULPI AutoResume bit in the Interface Controlregister. The default AutoResume state is 0 and this bit should be enabled for Host applications. Formore details please see sections 7.1.77 and 7.9 of the USB specification.

Peripheral LS Resume 10b 1b 10b 0b 0b 0b 1b 0b 0b 0b

Peripheral Test J/Test K 00b 0b 10b 0b 0b 0b 0b 0b 0b 1b

OTG device, Peripheral Chirp 00b 1b 10b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral HS 00b 0b 00b 0b 1b 0b 0b 0b 1b 1b

OTG device, Peripheral FS 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral HS/FS Suspend 01b 1b 00b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral HS/FS Resume 01b 1b 10b 0b 1b 1b 0b 0b 1b 0b

OTG device, Peripheral Test J/Test K 00b 0b 10b 0b 1b 0b 0b 0b 1b 1b

Table 6.8 DP/DM termination vs. Signaling Mode (continued)

SIGNALING MODE

REGISTER SETTINGS RESISTOR SETTINGS

XCVR

SELE

CT[

1:0]

TER

MSE

LEC

T

OPM

OD

E[1:

0]

DPP

ULL

DO

WN

DM

PULL

DO

WN

RPU

_DP_

EN

RPU

_DM

_EN

RPD

_DP_

EN

RPD

_DM

_EN

HST

ERM

_EN



Datasheet

6.4 Internal Regulators and PORThe USB3300 includes an integrated set of built in power management functions, including a PORgenerator. Internal regulators enable the USB3300 to be powered from a single 3.3 volt power supply,thereby reducing the bill of materials and simplifying product design.

6.4.1 Internal Regulators

The USB3300 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8)from the 3.3volt power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% lowESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since theyexhibit an ESR lower that 0.1ohm at frequencies greater than 10kHz.

Note: The specific capacitor recommendations for each pin are detailed in Table 3.1, "USB3300 PinDefinitions 32-Pin QFN Package", and shown in Figure 7.1 USB3300 Application Diagram(Peripheral)on page 47. The USB3300 regulators are designed to generate a 1.8 volt supplyfor the USB3300 only. Using the regulators to provide current for other circuits is notrecommended and SMSC does not guarantee USB performance or regulator stability.

6.4.2 Power On Reset (POR)

The USB3300 provides an internal POR circuit that generates a reset pulse once the PHY suppliesare stable. This reset will set all of the ULPI registers to their default values and start the PHY in normaloperation. Cycling the 3.3 volt power supply is the only method for the PHY to reset the ULPI registersto their default states. The Link can write the registers to their default states at any time in normaloperation.

The RESET pin has the same functionality as the RESET register in the Function Control Register.

6.5 USB On-The-Go (OTG) ModuleThe USB3300 provides support for USB OTG. OTG allows the USB3300 to be dynamically configuredas a host or a device depending on the type of cable inserted into the Mini-AB connector. When theMini-A plug of a cable is inserted into the Mini-AB connector, the USB device becomes the A-device.When a Mini-B plug is inserted, the device becomes the B-device. The OTG A-device behaves similarto a Host while the B-device behaves similar to a peripheral. The differences are covered in the OTGsupplement.

The OTG Module meets all the requirements in the “On-The-Go Supplement to the USB 2.0Specification”. In applications where only Host or Device is required, the OTG Module is unused.



Datasheet

The OTG Module can be broken into 4 main blocks; ID Detection, VBUS Control, Driving ExternalVbus, and External Vbus Detection. Each of these blocks is covered in the sections below.

6.5.1 ID Detection

The USB3300 provides an ID pin to determine the type of USB cable connected. When the Mini-APlug of a USB cable is inserted into the Mini-AB connector, the ID pin is shorted to ground. When theMini-B Plug is inserted into the Mini-AB connector, the ID pin is allowed to float.

.

The USB3300 provides an integrated pull-up resistor and a comparator to detect if the ID pin is floatingor grounded. An integrated pull-up resistor is provided to pull the ID pin high to VDD3.3 when a Mini-B plug is inserted and the cable is floating. When a Mini-A plug is connected, the pull-up resistor will

Figure 6.10 USB3300 On-the-Go Module

Table 6.9 IdGnd vs. USB Cable Type

USB PLUG OTG ROLE ID VOLTAGE IDGND

A HOST 0 0

B PERIPHERAL 3.3 1

EXTVBUS

CPEN

R=7

5K

R>=

656

R>=

281

OTG Module

VBUS

ID

VDD33

RXCMD VbusValid

IndicatorComplement

[UseExternalVbusindicator, IndicatorPassThru]

[0, X]

VbusValid

SessValid

SessEnd

IdPullup

DischrgVbus

DrvVbus

DrvVbusExternal

IdGnd

ChrgVbus

0.5V

1.4V

4.575V

0.6V

R=1

00K

[1, 0]

[1, 1]

R>1

M



Datasheet

be overpowered and the ID pin will be brought to ground. To save current when a Mini-A Plug isinserted, the ID pull-up resistor can be disabled by clearing the IdPullUp bit in the OTG Control register.To prevent the ID pin from floating to a random value, a weak pull-up resistor is provided at all times.The circuits related to the ID comparator are shown in Figure 6.10, "USB3300 On-the-Go Module" andtheir related parameters are shown in Table 5.6, "OTG Electrical Characteristics".

The status of IdGnd can be read by reading the ULPI USB Interrupt Status register, bit 4. It can alsobe set to generate an interrupt, in host mode, when IdGnd changes with the ULPI Interrupt Enableregisters.

6.5.2 VBUS Control

The USB3300 includes all of the Vbus comparators required for OTG. The VbusVld, SessVld, andSessEnd comparators are fully integrated into the USB3300. These comparators are used to ensurethe Vbus voltage is the correct value for proper USB operation.

The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the Vbusvoltage on the cable is valid. The SessVld comparator is used by the Link when configured as bothan A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is usedby the B-device to indicate a USB session has ended.

Also included in the VBUS Control block are the resistors used for Vbus pulsing in SRP. The resistorsused for VBUS pulsing include a pull-down to ground and a pull-up to VDD3.3.

6.5.2.1 SessEnd Comparator

The SessEnd comparator is designed to trip when Vbus is less than 0.5 volts. When Vbus goes below0.5 volts the session is considered to be ended and SessEnd will transition from 0 to 1. The SessEndcompatator can be disabled by clearing this bit in both the rising and falling interrupt enable registers.When disabled the SessEnd bit in the interrupt status register will read 0. The SessEnd comparatortrip points are detailed in Table 5.6.

6.5.2.2 SessVld Comparator

The SessVld comparator is used when the PHY is configured as both an A and B device. Whenconfigured as an A device, the SessVld is used to detect Session Request protocol (SRP). Whenconfigured as a B device, SessVld is used to detect the presence of Vbus. The SessVld interrupts canbe disabled by clearing this bit in both the rising and falling interrupt enable registers. When theinterrupts are disabled, the SessVld comparator is not disabled and its state can be read in the interruptstatus register. The SessVld comparator trip point is detailed in Table 5.6.

Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-DeviceSession Valid comparator. The USB3300 PHY combines the two comparators into one anduses the narrower threshold range.

6.5.2.3 VbusVld Comparator

The final Vbus comparator is the VbusVld comparator. This comparator is only used when configuredas an A-device. In the OTG protocol the A-device is responsible to ensure that the Vbus voltage iswithin a certain range. The VbusVld comparator can be disabled by clearing both the rising and fallingedge interrupts. When disabled a read of bit 1, in the Interrupt Status Register will return a 0. TheVbusVld comparator trip points are detailed in Table 5.6.

When the A-device is able to provide 8-100mA it must ensure Vbus doesn’t go below 4.4 volts. If theA-device can provide 100-500mA on Vbus it must ensure that Vbus does not go below 4.75 volts.

The internal Vbus comparator is designed to ensure that Vbus remains above 4.4 volts. If the designis required to supply over 100mA the USB3300 provides an input for a more accurate Vbus comparatoror fault (over current) detection described in Section 6.5.4, "External Vbus Indicator".



Datasheet

6.5.2.4 Vbus Pull-up and Pull-down Resistors

In addition to the internal Vbus comparators the USB3300 also includes the integrated Vbus pull-upand pull-down resistors used for Vbus Pulsing. To discharge the Vbus voltage, so that a SessionRequest can begin, the USB3300 provides a pull-down resistor from Vbus to Ground. This resistor iscontrolled by the DischargeVbus bit 3 of the OTG Control register, defined in the ULPI specifications.The pull-up resistor is connected between Vbus and VDD3.3. This resistor is used to pull Vbus above2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pull-up resistor is controlled by the bit 4 ChargeVbus of the OTG Control register, defined in the ULPIspecifications. The Pull-Up and Pull-Down resistor values are detailed in Table 5.6.

6.5.2.5 Vbus Input Impedance

The OTG Supplement requires an A-Device that supports Session request protocol to have an inputimpedance less than 100kohm and greater the 40kohm to ground. In addition, if configured as a B-Device, the PHY cannot draw more then 150uA from Vbus. The USB3300 provides a 75kΩ nominalresistance to ground which meets the above requirements, see Table 5.6.

6.5.3 Driving External Vbus

When a system is operating as a host, it is required to source 5 volts on VBUS. The USB3300 fullysupports VBUS power control using external devices. The USB3300 provides an active high controlsignal, CPEN, which is dedicated to controlling the Vbus supply when configured as an A-Device. TheUSB3300 also supports external Vbus fault detection detailed in Section 6.5.4.

CPEN is asserted when the ULPI OTG Control register bit 5 DrvVbus or bit 6, DrvVbusExternal is sethigh. To be compatible with Link designs that support both internal and external Vbus supplies theDrvVbus and DrvVbusExternal bits in the OTG Control Register are or’d together. This enables theLink to set either bit to access the external Vbus enable (CPEN.) This logic is shown in Figure 6.10,"USB3300 On-the-Go Module". DrvVbus and DrvVbusExternal are set to 0 on POR.

6.5.4 External Vbus Indicator

The USB3300 has fully implemented the External Vbus detection described in the ULPI 1.1specification. The block diagram of the External Vbus detection is shown in Figure 6.10 and inTable 6.10.

Table 6.10 External Vbus Indicator Logic

TYPICAL APPLICATION

USE EXTERNAL

VBUS INDICATOR

INDICATOR PASS THRU

INDICATOR COMPLEMENT

RXCMD VBUS VALIDENCODING SOURCE

OTG Device 0 X X Internal VbusVld comparator (Default)

1 1 0 External active high VbusVld signal

1 1 1 External active low VbusVld signal

1 0 0 External active high power fault signal qualified with internal VbusVld comparator. (Note 6.1)

1 0 1 External active low power fault signal qualified with internal VbusVld comparator. (Note 6.1)



Datasheet

Note 6.1 SMSC does not recommend using the ExternalVbus signal qualified with the internalVbusVld comparator.

Note 6.2 A peripheral should not use VbusVld to begin operation. The peripheral should useSessVld because the internal VbusVld threshold can be above the Vbus voltage requiredfor USB peripheral operation.

A host PHY may use an active high or low fault by setting the IndicatorComplement bit [5] in theInterface Control register. Also this implementation supports the IndicatorPassThru bit [6] in theInterface Control register, which allows a choice of having the External Vbus input qualified (and’ed)w i th the ex te rna l vbus compara to r ou tpu t . To use the Ex te rna l Vbus Inpu t theUseExternalVbusIndicator bit [7] must be set in the OTG control register. The default is not to use thisinput.

The EXTVBUS pin has a built in pull down resistor that is controlled by the UseExternalVbusIndicatorbit [7] of the OTG control register. When UseExternalVbusIndicator is set to 0 (default) the pull downresistor is activated to prevent the pin from floating when it is unused. When UseExternalVbusIndicatoris set to 1 the pull down resistor is disconnected.

Standard Host 1 1 0 External active high power fault signal

1 1 1 External active low power fault signal

Standard Peripheral

0 X X Internal VbusVld comparator. This should not be used by the Link. (Note 6.2)

Table 6.10 External Vbus Indicator Logic (continued)

TYPICAL APPLICATION

USE EXTERNAL

VBUS INDICATOR

INDICATOR PASS THRU

INDICATOR COMPLEMENT

RXCMD VBUS VALIDENCODING SOURCE



Datasheet

Chapter 7 Application Notes

The USB3300 requires few external components as shown in the application diagrams. In someapplications, the power supplied on the VBUS and GND pins of the USB connector is used as thesource of system power. The USB2.0 standard restricts the voltage at the VBUS pin to a maximumvalue of 5.25V. In some applications, it may be required to provide protection to the USB3300 VBUSpin if the VBUS voltage exceeds the USB2.0 specifications.

One method of protecting the VBUS pin from excessive voltage (transients) is to place a resistor(RVBUS) in series as shown in Figure 7.1, "USB3300 Application Diagram (Peripheral)" and Figure 7.2,"USB3300 Application Diagram (Host or OTG)". The resistor provides protection against transients thatexceed the value of VVBUS provided in Table 4.2, "Recommended Operating Conditions". When RVBUSis installed, the transient must not be allowed to exceed the value of VVBUS for longer than 500 μs.

To protect the VBUS pin against a steady state voltage on the USB connector that exceeds the valueof VVBUS provided in Table 4.2, an Over Voltage Protection (OVP) component can be used as shownin Figure 7.3, "USB3300 Application Diagram (Peripheral with Over Voltage Protection)".

In addition to the capacitors shown in the application diagrams, each VDD pin should have anadditional capacitor to ground, of value 0.01 or 0.1 μF (not shown for clarity). Approximately equalnumbers of each value should be used.

Table 7.1 Component Values in Application Diagrams

REFERENCEDESIGNATOR VALUE DESCRIPTION NOTES

COUT 4.7μF Bypass capacitors to ground (<1Ω ESR) for regulator stability.

Place as close as possible to the PHY.

CVBUS See Table 7.2, "Capacitance Values at VBUS of USB Connector"

Capacitor to ground required by the USB Specification. SMSC recommends <1Ω ESR.

Place near the USB connector.

CBYP System dependent.

Bypass capacitor to ground. Place as close as possible to the PHY.

CDC_BLOCK System dependent.

The USB connector housing may be AC-coupled to the device ground.

Industry convention is to ground only the host side of the cable shield.

RVBUS Max of 820Ω in Host or OTG applications.

Series resistor to reduce any transient voltage on the VBUS pin of the USB3300.

The transient must not be allowed to exceed the value of VVBUS for longer than 500 μs

ID Pin Okay to leave No Connection (NC) in device mode.

Table 7.2 Capacitance Values at VBUS of USB Connector

MODE MIN VALUE MAX VALUE

Host 120μF

Device 1μF 10μF

OTG 1μF 6.5μF



Datasheet

7.1 Application Diagrams

Figure 7.1 USB3300 Application Diagram (Peripheral)

Link ControllerUSB3300

RBIAS

DIRNXTSTP

CLKOUT

DATA7DATA6DATA5DATA4DATA3DATA2

DATA0DATA1

VDD3.3

VDD3.3

VBUS

DM

DP

ID

RESET

USB Receptacle

DM

DP

DIRNXTSTP

CLKOUT


DATA0DATA1

7

8

32

GND FLAG

2

3

VBUS 1

SHIELD

GND

16

6

4

5

CBYP

CVBUS

3.3VSupply

RVBUS may be installed in this configuration to assist in protecting the VBUS pin. 820 Ohms will protect against VBUS transients up to 8.5V. 10K Ohms will protect against transients up to 10V.

VDDA1.8 29

CDC_BLOCK 12.0k1%

Steady state voltage at the VBUS pin must not be allowed to exceed VVBUS.

RVBUS

NC

1718192021222324131112149

COUT

XI 28

CPEN3NC

XO 27

1MΩCLOAD

CLOAD

REG_EN

VDD3.330

31

VDD1.8 26

1 2

VDD1.8 15

COUT

VDD3.325

EXTVBUS10NC

The capacitor CVBUS must be installed on this side of RVBUS.



Datasheet

Figure 7.2 USB3300 Application Diagram (Host or OTG)


RBIAS

DIRNXTSTP

CLKOUT


DATA0DATA1

VDD3.3

VDD3.3

VBUS

DM

DP

ID

RESET

USB Receptacle

DM

DP

DIRNXTSTP

CLKOUT


DATA0DATA1

7

8

32

GND FLAG

2

3

VBUS 1

ID

16

6

4

5

CBYP

CVBUS

3.3V

RVBUS may be installed to assist in protecting the VBUS pin. 820 Ohms will protect against VBUS transients up to 8.5V.

VDDA1.8 29

12.0k1%


RVBUS

1718192021222324131112149

COUT

XI 28

XO 27

1MΩCLOAD

CLOAD

REG_EN

VDD3.330

31

VDD1.8 26

1 2

VDD1.8 15

COUT

VDD3.325


CPEN3

VBUS Switch

OUTENIN

EXTVBUS10FLG

GND

SHIELD

4

5V



Datasheet

Figure 7.3 USB3300 Application Diagram (Peripheral with Over Voltage Protection)


RBIAS

DIRNXTSTP

CLKOUT


DATA0DATA1

VDD3.3

VDD3.3

VBUS

DM

DP

ID

RESET

USB Receptacle

DM

DP

DIRNXTSTP

CLKOUT


DATA0DATA1

7

8

32

GND FLAG

2

3

VBUS 1

SHIELD

GND

16

6

4

5

CBYP

CVBUS

3.3VSupply

VDDA1.8 29

CDC_BLOCK 12.0k1%


NC

1718192021222324131112149

COUT

XI 28

CPEN3NC

XO 27

1MΩCLOAD

CLOAD

REG_EN

VDD3.330

31

VDD1.8 26

1 2

VDD1.8 15

COUT

VDD3.325

EXTVBUS10NC


Over-voltage device may be desired to protect against out-of-spec chargers.

OptionalOver-voltageProtection



Datasheet

7.2 Multi-port ApplicationsTo support multiple ports a single USB3300 host can be combined with one of SMSC’s many hubproducts to expand the number of ports. SMSC has 2-port, 3-port, 4-port, and 7-port hub designs whichcan be used to expand the number of ports in a design.

Using a SMSC hub to expand the number of ports allows a single Link to run several USB deviceswithout a separate Link to support each USB port. Another advantage of using a SMSC hub is onproducts where the main board is not located near the USB ports. The USB3300 can be placed onthe main board with the Link ASIC and the hub can be placed on a separate board next to the USBports. The only data connection required between the boards is DP and DM.

The CPEN output of the USB3300 is optional and can be used to turn the Hub on or off to lower currentwhen the USB connection isn’t needed.

7.3 Evaluation BoardAn evaluation board, EVB-USB3300, is available for building a prototype system with the USB3300.The evaluation board provides an industry standard T&MT connector to interface a ULPI Link controllerand a Mini-AB connector for the USB cable. A 500mA fault protected 5V Vbus switch that is controlledby the USB3300 is also included.

7.4 ESD PerformanceThe USB3300 is protected from ESD strikes. By eliminating the requirement for external ESDprotection devices, board space is conserved, and the board manufacturer is enabled to reduce cost.The advanced ESD structures integrated into the USB3300 protect the device whether or not it ispowered up. When the USB3300 is not powered, the digital I/O pins are loaded by the ESD structures,and must not be driven by external signals.

Figure 7.4 Expanding Downstream Ports for USB3300 Host Applications

USB3300

DPDM

CPENUSBDP0USBDM0

VBUS_DET

SOC w/ULPI Link

DPDM

USB Port 1

USBDP1USBDN1

DIRNXTSTP

DATA[7]DATA[6]DATA[5]DATA[4]DATA[3]DATA[2]DATA[1]DATA[0]

CLOCK

DIRNXTSTP

DATA[7]DATA[6]DATA[5]DATA[4]DATA[3]DATA[2]DATA[1]DATA[0]

CLOCK

USB2502

DPDM

USB Port 2

USBDP2USBDN2

DPDM

USB Port 3

USBDP3USBDN3

DPDM

USB Port 4

USBDP4USBDN4

DPDM

USB Ports 5-7

USBDP5-7USBDN5-7

USB2507

USB2503

USB2504



Datasheet

7.4.1 Human Body Model (HBM) Performance

HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling andmanufacturing, and is done without power applied to the IC. To pass the test, the device must haveno change in operation or performance due to the event. All pins on the USB3300 provide ±8kV HBMprotection.

7.4.2 IEC61000-4-2 Performance

The IEC61000-4-2 ESD specification is an international standard that addresses system-level immunityto ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are performedat the device level with the device powered down.

SMSC contracts with independent laboratories to test the USB3300 to IEC61000-4-2 in a workingsystem. Reports are available upon request. Please contact your SMSC representative, and requestinformation on 3rd party ESD test results. The reports show that systems designed with the USB3300can safely dissipate ±15kV air discharges and ±8kV contact discharges per the IEC61000-4-2specification without additional board level protection.

Both air discharge and contact discharge test techniques for applying stress conditions are defined bythe IEC61000-4-2 ESD document.

7.4.2.1 Air Discharge

To perform this test, a charged electrode is moved close to the system being tested until a spark isgenerated. This test is difficult to reproduce because the discharge is influenced by such factors ashumidity, the speed of approach of the electrode, and construction of the test equipment.

7.4.2.2 Contact Discharge

The uncharged electrode first contacts the pin to prepare this test, and then the probe tip is energized.This yields more repeatable results, and is the preferred test method. The independent test laboratoriescontracted by SMSC provide test results for both types of discharge methods.



Datasheet

Chapter 8 Package OutlineThe USB3300 is offered in a compact 32 pin lead-free QFN package.

Notes:1. Controlling Unit: millimeter.2. Dimension b applies to plated terminals and is measured between 0.15mm and 0.30mm from the

terminal tip. Tolerance on the true position of the leads is ± 0.05 mm at maximum materialconditions (MMC).

3. Details of terminal #1 identifier are optional but must be located within the zone indicated.4. Coplanarity zone applies to exposed pad and terminals.

Figure 8.1 USB3300-EZK 32 Pin QFN Package Outline, 5 x 5 x 0.9 mm Body (Lead-Free)

Table 8.1 32 Terminal QFN Package Parameters

MIN NOMINAL MAX REMARKSA 0.70 ~ 1.00 Overall Package Height

A1 0 0.02 0.05 StandoffA2 ~ ~ 0.90 Mold ThicknessA3 0.20 REF Copper Lead-frame Substrate D 4.85 5.0 5.15 X Overall Size

D1 4.55 ~ 4.95 X Mold Cap SizeD2 3.15 3.3 3.45 X exposed Pad SizeE 4.85 5.0 5.15 Y Overall Size

E1 4.55 ~ 4.95 Y Mold Cap SizeE2 3.15 3.3 3.45 Y exposed Pad SizeL 0.30 ~ 0.50 Terminal Lengthe 0.50 BSC Terminal Pitchb 0.18 0.25 0.30 Terminal Width

ccc ~ ~ 0.08 Coplanarity



Datasheet

Figure 8.1 QFN, 5x5 Taping Dimensions and Part Orientation



Datasheet

Figure 8.2 Reel Dimensions for 12mm Carrier Tape



Datasheet

Note: Standard reel size is 4000 pieces per reel.

Figure 8.3 Tape Length and Part Quantity
