Unit 1: p-n JUNCTION AND TRANSISTOR

This Unit includes following topics:

1.1 SEMICONDUCTOR MATERIAL

1.2 P-N JUNCTION

1.3TRANSISTOR

Learning Objectives

By the end of Unit 1, learners should be able to:

** Explain the fundamentals of semiconductor material

** Explain the fundamental concept of pn junction and its operation

**Describe characteristics and operation of different types transistor

Definition of a semiconductor

**A solid material whose conductivity lies in between metal and insulator

** The electrical conductivity of semiconductor is lower than metal but larger than insulator.

** Behaves as insulator at absolute zero temperature (i.e. T=0K) and shows some conductivity behavior at finite temperature

** Examples are Silicon, Germanium and GaAs etc.

** The conductivity of semiconductor material is generally sensitive to temperature, illumination and impurities added.

** Conductivity of semiconductor material increases with temperature, illumination and adding impurities.

This sensitivity in conductivity makes the semiconductor one of the attractive materials for electronic devices.

** Conductivity of metal decreases with temperature.

conductivity/resistivity range of various crystalline solid state materials.

** On the basis of the composition, a semiconductor material can be classified as

Elemental semiconductor

And

Compound Semiconductor.

** On the basis of purity, the semiconductor can be divided into;

Intrinsic Semiconductor

And Extrinsic Semiconductor

Elemental Semiconductor

** Are composed of single species of atoms.

** Most common elemental semiconductors are silicon and Germanium.

** These two elemental semiconductors are found in fourth group of periodic table and have four valence electrons.

** Silicon and Germanium have diamond lattice structure and form covalent bond.

In modern technology,

Silicon technology is one of the most advanced technologies among all semiconductor technologies.

Silicon is widely used in semiconductor industry because it is available in abundant amount in nature in form of sand.

Other important properties of silicon which make it favorable than germanium is: Silicon has excellent processing properties, relatively easy to fabricate in pure form. Silicon devices also exhibit better properties at room temperature.

Compound Semiconductor:

** Are composed of two or more different elements.

** Most of the compound semiconductors are formed from special combination of third group and fifth group elements of

the periodic table e.g. Gallium Arsenide (GaAs) etc.

** The compound semiconductors are widely used in high speed devices and optoelectronic devices.

Conduction and Valence Band

** Valence band: In this band, all electrons are tightly bound to nucleus. No free electrons

** Conduction band: In this band, all electrons are free and take part in conduction process.

In semiconductor material,

At T=OK all the energy states of valence band are occupied whereas all energy levels in conduction band are empty.

Conduction band edge: The lowest energy level in conduction band. Represented by EC

Valence band edge: The upper energy level in valence band. Represented by EV.

Forbidden gap or energy gap (Eg),

The separation between conduction band edge to valence band edge.

•The forbidden gap of two elementary semiconductors, at T=0K,

•Si=1.12eV and Ge=0.72eV.

•The energy band gap is 1.143eV for GaAs at T=0K.

Energy band diagram of metal (conductor)

OR

Due to zero forbidden gap, even at T=0K

electrons in metal can easily jump from valence band to conduction band where they can move freely in partially filled conduction band in presence of electric field.

In insulator, there is large forbidden gap, of order of ≥3eV.

The thermal energy or energy acquired from applied electric field is not sufficient to move the valence electrons to conduction band at any temperature which results in a very-2 low or almost zero current.

Intrinsic Semiconductor ** No foreign elements or impurities are added.

** Electrons are thermally excited from valence band to conduction band.

** Each free electron in conduction band will produce Hole in valence band.

** This process is called electron-hole pair generation (EHP).

** In intrinsic semiconductor, number of free electrons in conduction band is equal to number of holes in valence band

at any temperature i.e.n0=p0=ni

** n0 : thermal electron concentration in conduction band,

p0 : thermal hole concentration in valence band.

ni: Intrinsic carrier concentration.

** Carrier concentration is always expressed in cm-3.

** At room temperature: ni =1.5x1010 /cm3 .

** This means at room temperature,

There are 1.5x1010 number of electrons/cm3 in conductance band and equal number of holes/cm3 is available in valence band.

Due to low concentration at room temperature, the conductivity of silicon is very poor.

It is very difficult to get an intrinsic semiconductor at room temperature.

In intrinsic semiconductor material, conductivity is controlled by temperature only.

Extrinsic Semiconductor

** Electrical properties can be greatly altered in a controlled manner by adding small amount of foreign elements, called impurities or dopants.

** Process of injection of impurities into pure semiconductor (intrinsic) is called doping.

** When the impurity atoms have one more or one less number of valence electrons than pure semiconductor atom, then this electron will change the electrical behavior of semiconductor materials.

There are mainly two types of impurities added into silicon materials:

First type - From Vth group of the periodic table such as Arsenic and Phosphorous: results in n-type semiconductor

second type - From IIIrd group of the periodic table such as Boron. Results in p-type semiconductor

n-type semiconductor•Adding fifth group elements

• Results in one extra electron in silicon crystal because out of five valence electrons of impurity element four will form a covalent bond with their four neighboring silicon atoms and fifth impurity electron is left unbonded.

•This fifth electron of the impurity atom is loosely bound to the nucleus and hence in most of the cases, the thermal energy at room temperature is sufficient to free this electron

•These free electrons jump to conduction band where they move in presence of electric field.

•Such type of impurity is called donor impurity.

** Due to free electrons in conduction band, resulting material is known as n-type semiconductor

** Electrons are majority carriers and holes (absence of valence electrons) are minority carriers.

** Band formation is shown below:

** This fifth group impurity is called Donor impurity.

** Band diagram

** Due to donor impurities, new energy level just below the conduction band edge: Called Donor energy level.

p-type semiconductor

** An impurity atom of IIIrd group (number of valence electrons=3) is substituted in silicon crystal

** All the valence electrons of the impurity atom form covalent bond with electrons of neighboring silicon atom but one of the bond in the lattice structure cannot be completed because of the deficiency of one electron in the impurity atom.

** Due to deficiency of one valence electron in the impurity atom, a hole exists in the lattice.

** Such impurity is called as acceptor impurity .

** A pure semiconductor materials doped with IIIrd group impurity atoms are called p-type semiconductor

** Majority carriers are holes and minority carriers are electrons.

Band Diagram:

In extrinsic semiconductor material;n0≠p0≠ni.

But the mass-action law;

200 inpn

holds good for both intrinsic semiconductor as well as extrinsic semiconductor at any temperature.

n-type semiconductor:

n0>>p0

p-type Semiconductor

p0>>n0

Example 1: A piece of silicon has been doped with 1x1016 atom- cm-3. Calculate the electron and hole concentrations at thermal equilibrium for this sample at room temperature?

Solution: Na=Na-=1016cm-3

Means p0=1016cm-3

Using formula;n0= ni

2/p0=(1.5x1010)2/1016=2.25x104cm-3

Construction and operation of p-n junction

A p-n junction is formed;

when one region of a single-crystal semiconductor material is doped with donor impurities (Vth group) to create n-type and immediately adjacent region with acceptor impurities (third group) to create p-type.

The interface separating n-type region from p-type region is known as metallurgical junction.

Symbol:

When the two isolated semiconductor materials are joined together then electrons will diffuse to p-region from n-region where these diffused electrons become minority carriers and holes will diffuse to n-region from p-region due to concentration gradient and become minority carriers.

Due to diffusion of carriers on either side of junction will result in a current, called diffusion current

In the absence of any external field:

There is uncompensated ionized donor impurities (Nd+) near the junction of n-side and uncompensated negatively charged acceptor (Na-) impurities near the p-side junction

This results in accumulation of immobile charges near the junction.

The region on both sides of junction up to which immobile charges are accumulated is called space charge region or depletion region.

At thermal equilibrium, the diffusion current is exactly balanced by drift current and hence, net current through p-n junction is zero.

The potential gradient across the junction is called built-in-potential, (also called barrier potential) which cannot be measured directly with a voltmeter.

This built-in-potential is necessary to establish the equilibrium at the metallurgical junction and also does not imply any external potential. The built cannot be measured.

This induced electric field causes mobile carriers to drift near the junction and results in current which is known as drift current.

The space charge region induces an electric field that is directed from positive charge to negative charge.

Current flow in p-n junction

•For current flow in the junction diode, one has to disturb the equilibrium.

• which can be achieved by applying an external electric field on the p-n junction diode.

•Depending upon the polarity of the external voltage source across the two terminals of p-n junction diode, there are mainly two biasing schemes: Reverse bias and Forward bias.

Reverse Bias:

**The external potential is applied in such a way that the positive terminal is connected to n-type semiconductor material and negative terminal is connected to p-type semiconductor material.

Due to reverse bias, majority carriers move away from junction in their respective side and minority carriers will cross the junction.

This results in increase in number of uncovered positive immobile charges in n-type material and immobile negative charges in p-type material near the junction.

Therefore, the net effect of reverse bias is to widen the depletion regions on both sides of the junction.

This widening of the depletion region will enhance the potential barrier height for majority carriers and hence the diffusion of carriers will reduce to zero.

The movement of minority carriers on both side of junction due to applied external reverse bias gives the current which is known as reverse saturation current

Represented by IS.

Reverse saturation current is sensitive to temperature change and becomes double for every 100 C rise in temperature.

For germanium, the leakage current is orders of magnitude higher than silicon.

Since germanium semiconductors are rarely used today, this is not a problem in practice.

Forward Bias:

**Positive polarity of voltage source is connected to p-side of the junction and negative polarity is connected to n-side of the junction.

V

V

**Forward bias potential across the junction will enhance the diffusion process i.e. more majority carriers will diffuse on either side of the junction due to repel force on the majority carriers.

The potential barrier height will also reduce. Decrease in potential barrier height will reduce the depletion width and hence, more and more majority carriers now cross the junction which results in forward current. At a certain forward bias potential (Called cut-in or Knee or off-set voltage), total depletion width as well as potential barrier height reduces to zero, and measurable current will flow.

for Silicon semiconductor diode is 0.7V. The typical value of forward bias current is of order of mA.

This voltage is represented by

Current-voltage characteristics of p-n junction diode

•The net current in the p-n junction diode in the presence of reverse and forward bias is given by Shockley’s equation as;

]1).([exp t

DSD v

vII

where ID is diode current and IS is reverse saturation current. η is ideality factor and lies in between 1 and 2. vt is thermal energy=(kT/q) (≈26meV at T=300K) and vD is voltage drop across the diode.

Let us consider three cases:

Case1: Reverse Bias: In this case vD is negative and

1

t

D

v

v

e Means;

ID=-IS

Means, in reverse bias: contribution of majority carriers in current flow is zero and total reverse current is due to minority carriers only.

Case 2: Forward Bias: vD is positive

).(expt

DSD v

vII

current is increasing exponentially with applied forward bias voltage and total current is due to majority carriers.

Case 3: No Bias:

**vd=0 results ID =0. This clearly suggests that no current flow in the diode in absence of applied potential and system is at thermal equilibrium.

The current-voltage characteristic of a real diode

Ideal diode model:

The ideal model of diode is a simple switch. When diode is in forward bias, it acts like a closed switch and becomes ON and diode acts as an open –circuit or OFF in reverse bias. For an ideal diode: Knee voltage or Offset voltage in forward bias is zero. Diode does not offer any resistance in forward bias.

Rf≈0 or (very-2 small) Rr=∞ohm

Real/Practical diode:

when real diode is in forward bias it is equivalent to a closed switch in series with a small equivalent voltage source equal to offset voltage,

In reverse bias, it is equivalent to an open switch with a resistance Rr,

Forward bias

Reverse bias

The complete circuit model for a real p-n junction diode is

Example 2: In the circuit, shown below, the source voltage is given as;vs=1.1+0.1sin1000tFind iD, assume that ηVt=40mV and Vf=0.7V.

Solution: Its model Parameter equivalent circuit

** Assuming diode is ON.Mesh AnalysisDc component only;[vs-vf]/100=ID

Or ID=4mA

AC component only;Rf=ηVt/ID=10ohmApplying KVL (replacing diode by its Forward bias resistance)vs=RfiD+RLiDOriD=0.91sin1000tmATotal diode current;iD[4+0.91sin1000t)mA

Bipolar junction transistor (BJT), its construction and operation

•it is a bipolar device in which both majority carriers as well as minority carriers are responsible for current.

• It is a three terminal device with two junctions. These three terminals are: emitter (E), base (B) and collector (C).

•Emitter emits or supplies the carriers (mainly majority carriers) into collector through base.

•Collector collects these injected carriers.

•Emitter region should be heavily doped

•collector should be lightly doped whereas base should be moderately doped.

•For efficient heat dissipation collector region should be wider.

•To avoid any recombination of injected carriers from emitter into base, base region should be as thin as possible. Emitter region should be wider than base but narrower than collector regions.

On the basis of types of carriers in the respective regions, a BJT can be classified as n-p-n transistor or p-n-p transistor. In n-p-n transistor, emitter and collector are n-types and base is p-type whereas in p-n-p transistor emitter and collector regions are p-type and base is n-type semiconductor.

A transistor can be biased in four different regions:

(1) Forward active mode: In this mode, emitter-base junction forward bias and collector base junction reverse

bias.

(2) Saturation region: both junctions should be forward bias

(3) Cut-off region: both junctions should be reverse bias

(4) reverse active mode: emitter-base junction reverse bias and collector-base junction forward bias.

The minimum voltage required on emitter-base junction of silicon transistor to make it forward bias is 0.7V whereas in

saturation region VCE≈0.2V

Current flow mechanism in BJT

• In absence of the any external voltage across the junction, a depletion region forms near the junction which prevents the movement of carriers and results in net zero current. •** let us apply forward bias to emitter-base junction and reverse bias to collector- base junction of n-p-n transistor.

•Due to forward bias emitter-base junction, depletion region shrinks near the emitter-base (E-B) junction and widens near the collector-base (C-B) junction.

•Due to forward E-B junction, electron will diffuse to base region and holes will diffuse to emitter region.

•This results in emitter current which is equal to IE=IEn+IEp.

•Since, base region is thin and lightly doped, therefore, only a small fraction of injected electrons from emitter will recombine with holes in the base region and rest will be attracted towards the collector due to applied positive potential.

•These relatively few recombined electrons in the base region form the base current (IB) and flows out of the base lead.

•The reverse biased collector-base junction blocks the movement of majority carrier holes from base to collector but allows the movement of minority carrier electrons (mostly diffused electrons from emitter) from base to collector and holes from collector to base. Therefore, total collector current is given as;

IC =ICn+ICBO

Collector current is much larger than the base current.

Total diffused electron from emitter is contributing base current and collector current and emitter current is equal to sum of base current and collector current. Mathematically;

IE=IB +IC

Transistor Parameter

Two important parameters to characterize the BJT are βdc and α.

The ratio of dc collector current to dc base current is defined as beta or dc current gain of the transistor.

It is mathematically expressed as;βdc =[IC /IB]=β.

For transistor action, it is required that β should be large.

Typical values of β are less than 20 t0 200 or higher.

Hybrid (h-) parameter hFE is same as β: called as common emitter current gain.

β is temperature dependent parameter and also depends on the collector current.

At a given temperature, increasing IC causes β to increase to a maximum value. A further increase in IC beyond the maximum point causes β to decrease.

For a given constant IC, β is directly proportional to temperature change.

E

C

I

I

1

1

α is defined as the ratio of the dc collector current to dc emitter current

** Called as common-base current gain.

** α value varies from 0.90 to 0.999 but not equal to unity The ** Relation between α and β is;

or

Biasing Schemes for BJT:

Biasing is required for proper operation of the device. Main concerns with biasing are;

(1)Establishing a constant dc current IE in the transistor which should be predictable and insensitive to variations

in temperature and β.

(2) Locating the dc point (i.e. Q-point) in the current-voltage characteristic to allow for maximum output signal swing.

Simple Bias Circuit (self-bias)

The DC current into the base may be determined by voltage around the base-emitter loop which is given as;

and after solving, dc base current is given as;

For operation in the active region, collector current is

And after solving

** Q-point for the Base-bias configuration depends on the β value of the transistor. The β value is an imprecise quantity

and it is also a quantity whose value changes with temperature. Therefore, the Q-point will shift around as β

changes which is not a desirable characteristic of the design.

Single power supply biasing:

This arrangement is known as voltage-divider arrangement.

Here R1 and R2 form a potential divider, which will fix the base potential of the transistor.

The current through this bias chain is usually set at 10 times greater than the base current required by the transistor.

The base emitter voltage drop of the transistor is approximated as 0.6 volt.

The inclusion of RE helps to stabilize the bias.

The base voltage is calculated by the potential-divider rule and given as;

CCBB VRR

RV *][

21

2

1

,

,1

,

)(

BE

BEBBE

EB

BEBBEEBB

BBEEBEBB

RR

VVI

therefore

IISince

VVRIRI

or

VRIVRI

If VBB >>VBE and RE >>RB /(1+β), then Current IE will be insensitive to temperature and β change.

For a proper design, it is thumb rule that VBB ≈(1/3)VCC , VCB (or VCE )=(1/3)VCC and IC RC ≈(1/3)VCC to make IE insensitive

to temperature change.

The condition RE >>RB /(1+β) can be satisfied by selecting small value of RB .

RB can be adjusted to desire value by using low values of resistances R1 and R2.

Lower value of R1 and R2 means larger current is drawn from power supply.

This results in lowering of the input resistance of the amplifier circuit.

Therefore, thumb rule for selecting the values of R1 and R2 is sets R1 and R2 such that their current is in the range of IE to 0.1IE . A general acceptable design rule is; RB=(1/10)(1+β)RE

Self Stabilizing Bias

This configuration stabilizes the Q-point. The equations to calculate Rc and RB are;

Rc = Vcc / Ic RB =(Vcc – VBE)/ IB

Since, IB = Ic / hFE, therefore, RB = (Vcc –VBE) * hFE / Ic

This circuit is also known as Collector-feedback bias. For this circuit at operating point;

IC≈I=[VCC –VBE ]/{RC+(RB/β)}And collector-to-emitter voltage is;

VCE=VCC-ICRC

Example 3: A transistor with α=0.98 and ICBO=5μA is biased so that IBQ=100μA. Find ICQ and IEQ.

Solution: β=[α/(1-α)]=49

ICEO=(β+1)ICBO=0.25mA

ICQ=βIBQ+ICEO=5.15mA

IEQ=ICQ+IBQ=5.25mA

Principles of Field Effect Transistor (FET)

FET stands for field effect transistor

** In FET current is controlled by controlling the applied voltage at the input

** It is called voltage controlled current device.

** In FET, only majority carriers are responsible for current flow and also called as unipolar device.

** Offers a very high input impedance of order of mega ohm.

The different types of FET:

Junction Field-effect transistor (JFET),

Metal-Semiconductor Field-effect transistor (MESFET),

Metal-Oxide semiconductor Field –effect transistor (MOSFET),

Modulation-doped Field-effect transistor (MODFET).

Junction Field-Effect Transistor: JFET

** Three terminal device with one terminal capable of controlling the current between other two.

** These three terminals are; Source (S) which supplies the carriers into channel, Gate (G) which controls the flow of carriers in the channel and Drain (D) which removes the carriers.

** JFET is a symmetric device, means source and drain can be interchangeable and only applied potential decides the source and drain terminals.

** Available in two polarities, n-channel and p-channel JFETs.

** Their symbol and current direction is shown in Fig. below.

** The arrow in the symbol represents the direction of the current flow.

In the n-channel JFET, drain is at higher positive potential than source whereas in p-channel JFET, source is at higher potential than drain.

Construction of n-channel JFET

** n-channel JFET consists of lightly doped n-type silicon slab with heavily doped p-region on both sides.

** These two heavily doped p-regions (p+-) are tied together and act as a gate.

** The one end of lightly doped region is called source and other end is called drain.

** The region between source and drain is called channel.

** Since, whole region between source and drain is filled with n-type semiconductor material, therefore, this JFET is known as n-channel JFET.

** Gate-source forms a p-n junction and acts like a one sided p-n junction (p+-n).

** The operation of JFET is based on reverse-biased p-n junction.

** In absence of any applied external potential at the terminals of the JFET, the JFET has two p-n junctions under no bias condition. The p-channel JFET is complementary of n-channel JFET.

Operation of n-channel JFET:

The main reason for heavy doping in gates regions is:

Due to heavily doped gate regions, the two depletion regions will move into the channel because it acts as one sided p+-n junction.

The separation between these two regions in the channel will control the movement of carriers in the channel and ultimately the drain current.

The width of two depletion regions in the channel can be controlled by applying negative potential on the gate.

Therefore, this device is a voltage controlled current device.

** No voltage applied in between gate and source, (i.e. Vgs=0)

** Applied drain to source voltage is at small positive potential: Results in symmetrical depletion regions about source and drain regions.

Due to applied positive potential on the drain, electrons will be attracted towards the drain through the channel and results in drain current (ID).

For small VDS, JFET is simply operating as a resistance whose value is controlled by VGS. This region of operation of small VDS is known as Linear or ohmic region.

If VDS is not small then the shape of the depletion regions in the channel is asymmetrical as shown in Fig. (next slide)

The drain-source voltage appears as a voltage drop across the channel length. This drop increases as one moves towards the drain end from source. Drop is minimum or zero at the source end and maximum at the drain end i.e. V(x=L)=VDS. This shows the reverse-bias voltage between gate and channel varies at different points along the channel and channel appears as tapered.

The depletion region is wider towards the drain end then the source end because gate-drain junction is more reverse biased then the gate-source junction. This causes a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase and hence drain current reduces. This results in non-linear current-voltage relation.

If VDS is increased to a value where it appears that the two

depletion regions would touch each other near the drain end then this condition is called Pinch-off Condition.

In the pinch-off condition, channel is completely depleted from mobile carriers and channel, in effect, disappeared.

Disappearance of the channel should cause zero drain current but in reality this is not true but at pinch-off the drain current saturated because still a very small channel exists which gives a very high current density.

The close encounter between two depletion regions increases in length along the channel but the level of the drain current remain essentially same at IDSS, called drain

saturation current.

IDSS is defined as the maximum drain current for JFET at VGS=0

and VDS> PV

This condition is defined as the pinch-off condition and the voltage VDS at which the drain current ID becomes

essentially constant for VGS=0V is defined as Pinch-off

Voltage VP.

Now apply small negative potential on the gate so that gate-source junction should be reverse bias and establish depletion regions similar to those obtained with VGS=0 but at lower value of VDS. Therefore, the effect of increasing VGS in the negative direction will result saturation at lower value of VDS than VGS=0. The resulting saturation level of ID has been reduced and in fact will continue to decrease as VGS made more and more negative.

It is also observed that JFET reaches to pinch-off at value of VDS lower than actual value of VP for VGS=0.

The level of VGS that results in ID=0mA is defined by VGS=-VGS(off) and region of operation is known as cut-off region. It should be noted that VGS(off) and VP are always equal in magnitude but opposite in sign. Due to reverse biased source-gate junction, the gate current IG is equal to zero.

The relationship between drain current ID and gate-source voltage VGS is defined by Shockley’s relation as; ID=IDSS[1-(VGS/VP)2] Where IDSS and VP are treated as constants and VGS is taken as control variable.

This shows a non-linear relationship between drain current and gate-source voltage.

When VGS=0, then ID=IDSS

And when VGS=-VP then ID=0.

Reverse biasing is necessary for proper operation of the JFET.

Due to reverse bias gate-source p-n junction, the input impedance of the JFET is very large of order of mega ohm.

Example 4:Find the equivalent of two identical n-channel JFETs connected in parallel as shown in Fig.

Solution: Assume the devices are described by

then

Because the two devices are identical and connected in

parallel, the equivalent JFET has the same pinchoff

voltage as the individual devices. However, it has a value

of shorted gate current IdSS equal to twice that of the

individual devices.

MOSFET and Types of MOSFET

MOSFET stands for metal-oxide semiconductor field effect transistor.

Current in MOSFET is mainly dominated by one polarity carriers only (either electrons or holes),

MOSFET is usually referred to as a unipolar device.

If current flows due to electrons, then MOSFET is known as n-MOS or n-channel MOSFET. Similarly, if current in the transistor is due to holes, it is known as p-MOS or p-channel MOSFET.

MOSFET is a four terminals device:

These terminals are source (S), drain (D), Gate (G) and substrate or bulk or body (B).

The function of drain and source are same as in JFET.

In MOSFET there is only one gate instead of two gates in JFET.

This gate is separated from channel by an insulating material SiO2.

Due to insulation separation, the input impedance of the MOSFET is very high and gate current is assumed to be zero..

The current flow in MOFET can be altered by applying voltage on the gate, so why MOSFET is a voltage controlled current device.

MOSFET is also a symmetrical device in which source and drain can be interchanged. In n-channel MOSFET, drain should be at higher potential than source and reverse is true for p-MOS.

Basic structure of a MOSFET

Consists of p-type silicon substrate into which two heavily doped n-regions (n+) are created by ion implantation method. These two heavily doped regions can be designated as source and drain.

The gate electrode is usually made of metal or heavily doped poly-silicon material.

The gate is separated from the substrate by a thin silicon dioxide film which is called gate oxide (tOX).

Surface region under gate oxide between source and drain regions is called channel and represented by L (channel length). W is the width of the channel.

MOSFET device acts like two back-to-back p-n junction diodes.

MOSFETs are basically classified into two categories: Enhancement-mode (E-MOSFET) and Depletion-mode (D-MOSFET).

Enhancement-mode MOSFET:Initially at zero gate-source voltage there is no channel exists in between source and drain.

Therefore, E-MOSFET is normally OFF> Channel is formed only when appropriate voltage magnitude and sign is applied on the gate.

The symbols of E-nMOSFET and E-PMOSFET are:

Broken line only represents that channel is not available at VGS=0V.

Depletion-mode MOSFET: In this MOSFET channel is already exists at the time of fabrication. Therefore, D-MOSFET is generally ON device and channel doping is opposite to substrate doping. A negative bias voltage is applied on the gate of the n-MOSFET to remove the existing channel and reverse is true for p-channel depletion transistor.

MOSFET Operation and Current-voltage characteristics:

Enhancement Mode: In nMOSFET source terminal is connected to most negative potential and taken as a reference point.

The voltage at the drain with respect to source is defined by VDS and gate voltage with respect to source is VGS.

It is assumed here that body is connected to source to avoid body effect.

Assume that no gate-source voltage is applied and total region between source and drain is filled with holes.

Now apply positive VDS : still no current flow in the channel and MOS transistor is said to be OFF.

** Now apply positive voltage on the gate of nMOS enhancement mode transistor,: Results in Vertical positive Field: Which attracts the electrons from the two heavily doped n+-regions and substrate towards the Si-SiO2 interface.

This positive electric field will repel the majority carrier holes from interface into deep substrate.

If gate positive bias is continuously increases then population of electrons at the interface becomes more than majority carrier holes.

At a particular positive gate voltage, total region near the interface between source and drain is completely occupied by electrons: This gate voltage is called Threshold Voltage (VTh).

This process is called inversion

A channel of electrons will form near the interface in between source and drain.

And the resulting MOSFET is known as n-channel MOSFET. .

Once, channel is formed then applying even a small positive potential at the drain with respect to source will attract electrons from source to drain and current is called drain current (ID).

If applied drain-source voltage is small, then current will follow the VDS and region of operation is called linear or ohmic or triode region. In this region MOSFET behaves as a voltage controlled resistor.

As drain voltage is increased further then after a particular drain voltage VDSsat., the drain current will saturate and region of operation is called saturation or active region.

Therefore, basically MOSFET operates in three regions, cut-off region, linear region and Saturation region. When gate-source voltage is lower than threshold voltage transistor turns OFF and operates in cut-off region.

For VGS≥VTH, transistor turns ON and operates either in linear region or saturation region depending upon the applied drain-source voltage.

In digital electronics, MOSFET is used as a switch.

Since, gate is insulated from the channel by an insulating material, therefore, gate current is ideally zero i.e. IG=0.

MOSFET is a voltage controlled current device.

GSDSDG VVV

]2

)[(2DS

DSThGSD

VVVVKI

)( ThGSDS VVV

2][2 ThGSD VVK

I

)( ThGSDSsat VVV

The terminal voltages are related as;

For low drain voltage, linear current is given as;

If

or more, then MOSFET is said to be in saturation region and saturation current is given as;

where k=μnCOX(W/L) with μn is mobility of electron, COX

gate oxide capacitance. The saturated drain voltage

Example 5: An Enhancement-type NMOS transistor has the following parameters:

Solution: