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8/16/2019 Ultra Low Power Vedic Multiplier
1/6
Abstr
multi
(EEA
signi
capac
adiab
μmSuite.
funct
energ
integ
Keyw
recensyste
multi
Multi
[9],India
8×8
TSM
suite.
certai
appr time-
ener
noise
effici been
one sand i
In
cons betw
featu
whiccircu
ov
Po
mana
ct — In this pplier structur
L). The powe
icantly low b
itance is most
atic multiplier
MOS process. Both simul
onality of suc
y-aware and
ation (VLSI) c
rds: adiabatic;
plethora of
tly in literatatic design
plier based o
plier Archite
sutra or “Ver n Vedic Math
Vedic multip
C 0.18μm C
diabatic swi
n interest, and
ach is based ovarying clock
y used by slo
immunity a
ent adiabatic lintroduced as
inusoidal pows geared towa
EAL, high
mptions areeen the outp
es simplicity
substantiallt complexity.
l Tra
er Hi
Me
sh.bst@gmail.
aper, we desc
using Ener
consumption
ecause the e
ly recovered.
structure have
technology ation and me
h logic, makin
performance
ircuitry.
single phase; l
I.I NTROD
multiplication
re [1]-[8]. Iethodology f
n Vedic mat
ture is based
tical and Croematics. Con
lier structure
OS technolo
ching [13]-[1
is being impl
n a slow char ed ac power
ly decreasing
d driving a
ogic (EEAL)an adiabatic l
er clock supplrd high-speed
peed operati
ensured by ut nodes and
and static lo
decreases
sistor
gh-spM. Ch
EC
hnad Saha Ins
com1, suvadip
ribe an energ
gy Efficient
of the propo
ergy transfer
he proposed
been designed
d verified byasurement re
g it suitable f
- efficient v
w power, mult
CTION
algorithm ha
n this paperor fast and ar
ematics [3],[
on the Urdh
sswise” algorientional, as
have been i
gy, using CA
5] has recentl
mented in ma
ing of the capand a partial
the supply wi
ility. In this
ased on DCVgic style. EE
y, has simpleand low-ener
on as well
sing a paralle clock suppl
gic resembled
ransistor ove
Leve
ed Aanda
1, S. B
Dept.1&4, VD
titute of Tech
-efficient Ved
diabatic Log
ed multiplier
ed to the lo
8x8 CMOS a
in a TSMC 0.
Cadence Desiults verify t
r implementi
ery-large sca
plier.
been propos
we presenta efficient di
],[9]-[12]. T
a-Tiryakbhya
thm of ancieell as, adiabat
mplemented
ENCE Desi
y become of
ny systems. T
acitive nodesrecovery of t
hout sacrifici
paper, Ener
logic [16], hL requires on
implementatioy VLSI desig
as low ener
l resistive pa. EEAL log
characteristic
heads and t
Real
iabatnerjee
2, D.
TT Dept.2 and
ology1&4, IIT
m2, deepon.sa
ic
ic
is
d
d
8
ne
g
le
d
ait
e
m
ntic
in
n
a
e
ye
g
y
asly
n,n.
y
thic
s,
e
T
descriissue
shows
based
Cross
adiabaof pe
imper
concl
EDCVS
each s
Figure
E
has s previo
of ene
clockoverh
circuit
zatio
c VeSaha
3, S. Ja
ETCE Dept.3
Delhi2, Jadavp
e rest of the
es the operatiof power diss
the general
on Urdhva
ise” algorit
tic 8×8 multirformance of
tive logic sty
sions are give
EAL is a dual network and
tage, as illustr
1. EEAL logic (supply (d
EAL requires
mple impleusly proposed
rgy consumpt
scheme [16],ads. figure 1
and supply cl
of U
ic Min
4
ur University3
2, sankalp.00
paper is org
on of EEAL iipation of thi
implementatio
-Tiryakbhyam
m. Implemen
lier, experimour energy
les are also d
n in section V.
II. EEAL
-rail adiabatica pair of cro
ted by figure
) Block diagram () Cascading of In
only one sin
entation, an adiabatic logi
on. As single
this logic styl(b) and (c) sho
ock () respec
tra L
ltiplie
nized as foll
verter and als proposed lo
n of N×N V
sutra or
tation of co
ental results arecovery lo
tailed in sect
OGIC
logic whichs-coupled P
1(a).
b) Inverter/Buffeerter/Buffer circ
soidal power
performs bc families [13
clock circuit
e can enjoyws the EEAL
tively.
w
r
4
ws. Section I
o addresses thic. Section II
edic multiplie
“Vertical an
ventional an
nd comparisoic with othe
on IV. Finall
onsists of twOS devices i
circuit (c)Power
its
clock suppl
etter than th]-[15] in term
equires simpl
inimal contro buffer/Inverte
I
eI
r
r
es
e
lr
8
978-1-4673-5090-7/13/$31.00 ©2013 IEEE
8/16/2019 Ultra Low Power Vedic Multiplier
2/6
using
(“outup fr
“0” a
P1
follo
comb
nodesuppl
disch“outb
can
node.
MHz
unde
rampCLV
chan
Ediss
Simil proc
E = {
Hencoutp
volta
time,
parameas
In Ealmocomp
Eload
ComCLV
adiab
Adia
Ene
= [{2
= 2{
he operation
figure 1 (b).
” and “outb”)m logic 0 ( “
nd “inb”= “1”
ill be turned
ing the sup
ination of P
is kept at gy clock swin
arged throug” is kept at s
e obtained in
. Output volt
frequencies
he energy a
stood by ass
s up betwee
D over a ti
el resistance
{(CLVDD)/T}2
arly, energyss of the EEA
(R PCL)/T} CL
e R P is the tur t load capacit
ge drop acros
yet due to v
eter is treateures the thres
EAL as chast similar amolete cycle can
2{(RCL)/T}
ared to con
D2 energy in
atic gain (G)
atic Gain (G)
Energy comsu
gy Consumption b
R PCL/T} + {(
PCL/T}×100
of EEAL inve
Assuming the
are initially lo” ) to logic 1
; N1, M1 will
ON. The “o
ly clock ()OS (P1) and
ound potentiags from “VD
the sameme ground po
“out” node a
ge swing for
ith 20 f F capa
vantage of
uming a ram
“0” and “Ve period T.
is,
RT = {(RCL)/
onsumption dL inverter/buf
VDD)2 + ½ CL
-on resistancances, T is th
the resistive
ery small ma
d as constant.old loss whi
ging and disunt of energy, be expressed
CL(VDD)2 + C
ventional C a full cycl
f EEAL beco
in (%)
ption by EEAL pe
y conventional C
V)/VDD}2] ×
(as V
8/16/2019 Ultra Low Power Vedic Multiplier
3/6
squa
be p
Eachwith
writt
cross
signi
and t
initia
3.2
Imulti
and
consi
(Xa res
The s i) S1 i
ii) S2Y0) a
iii)
gene
adde
iv) S
multishow
divid
eachwe g
(N/2+3)
YL={
e will be divi
rtitioned agai
digit of the
every digit ofn in the sm
wise dotted li
ficant digit of
e rest as the
l carry is take
Figure 3. M
Implementati
n this sectio plier block,
8×8 multip
dering two i
X1X0 and Y
lt, by doing v
teps are:
s the result of
is the additio
nd (X0 and Y1
3 is the verti
ated from the
with the vert
is the carry g
y using this
plier block can in figure 4,
ed into two e
halve. Assumet XL= {X1 X
….X N}as two
Y1 Y2 Y3…Y
ed into N2 (=
n by crosswis
multiplier isthe multiplica
all square bo
e are added t
the obtained
arry for the n
as “logic 0”.
ltiplication using
n of general
we first dishich will be
lier structur
puts (X and
Y1Y0), we get
ertical and cro
Vertical multi
n of crosswir
.
cal product
previous step
cal product to
nerated durin
2×2 multiplie
n be impleme-bit multiplie
ual halves, c
ing N-bit mul
2 X3….X N/2}
halves of X.
/2} and YH={
16) no. of squ
e line, as sho
hen independd and the two
. All the di
the previous
umber acts a
xt step. In thi
UrdhvaTiryakbhy
edic multiplie
cuss the orgafurther used t
s. In 2×2
Y) having t
four outputs (
ss-multiplicati
lication betw
bit multiplic
f X1 and Y1,
s, otherwise
generate S3 as
addition of S
r block 4×4,
ted. For N×r and multipli
nsisting of N
tiplication betand XH= {X (For Y, its tw
(N/2+1) Y(N/2+2)
ares, which w
n in Figure
ently multipli-digit product
its lying on
carry. The lea
the result di
above examp
am Sutra
structure
ization of 2 configure 4
multiplicatio
wo digits ea
SS4S3S2S1)on and additio
en X0 and Y0.
tion of (X1 a
if no carry
arry bit will
a sum.
3.
8×8, 16×16 e
multiplicatioand first will
2 no. of bits
ween X and
/2+1) X (N/2+2) halves will
Y(N/2+3) ….Y N
ll
3.
dis
a
st
it
le
24
n,
h
as
n.
d
is
e
tc
n,e
in
,X
e
}.
So, X
steps
1) Fi
Y
fi
N
bi
2) In
,{
S
a
c
3)
V bi
Oc
T N
S(a
4) C
c
a
T
law
th
S(
and Y can be
re given bello
rst vertical
L(N/2 bits) wi
st N/2 bits {
/2 outputs {S1t in next steps.
next steps cr
L) and (XL ,
HL(1) SHL(2) S
H(N)} respecti
ded up to pro
rry.
Figure 4. Gene
ertical multiplts) also produ
ut of thesescaded with
..SLL(N)}, of
ese total N n bit adder, S11 N/2+1) to S(3N/2dition also pr
1 and C2 are
rry bits. (N/2-
d sum to pro
ese N/2 bits
st N/2 bits ofhich are {SHHese N/2 bits a
3N/2+1) to S(2N))
represented a
w,
ultiplication
ll produce tot
SLL(1) SLL(2)
S2 ….S N}. La
.
ss-multiplicat
YH)to produc
HL(3)…..SHL(N)}ely. These t
duce another
ral lock diagram
ication betweces N no. of b
bits, first Nthe last N/
ertical multip
o. bits will beto S1N, to pro
)) of N×N m
duces a carry,
ent to the hal
2) no. of zero
uce a set of
ill be added
vertical multip
N/2+1) SHH(N/2+2ddition will pr
of N×N multi
XH XL and
between XL
l N no. of bit
..SLL(N/2)} ar
t N/2 bits will
ions have don
two sets ofand {SLH(1) SLo sets of N
no. bits,S11 t
of NxN Vedic M
n XH (N/2 bitits, {SHH(1) SH2 bits, SHH(1)2 bits, {SLL(lication betwe
added with thuce total N n
ultiplier. This
C2.
f adder to ge
will be insert
/2 bits, as sho
p by a N/2 bit
lication betw
) …..SHH(N)} .
oduce the last
lier.
HYL . Now th
(N/2 bits) an
s. Out of thes
taken as firs
be used for N
e between (X
N no. of bit
H(2) SLH(3) ….
no. of bits ar
o S1N and C1 a
ultiplier
s) and YH (N/H(2) …..SHH(N)}
to SHH(N/2) ar
N/2+1) SLL(N/2+en XL and Y
output of firso. of bits (fro
second N bi
erate sum an
ed before carr
wn in figure 4
adder with th
en XH and YThe outputs o
N/2 bits (fro
e
e
t
-
e
s
e
t
t
e
f
8/16/2019 Ultra Low Power Vedic Multiplier
4/6
multi
Figur
the
impl prese
EEA
usingrepla
NAN
sum
blocstand
as b
and
spectPMOwher
3.3
All s
Duriand
Henc
input{A}
0000
0001
0000CM
respe
multi
multi
o in a N×
pliers, two N
5. DCVS networ
tatic conventi
conventional
mentation, fir nt the design
L logic. Com
simple NMcing the DC
D gate with
and carry blo
are shown iard-cell librar
ffer/inverter,
multiplier blo
re circuit simuS and NMOSe =0.9 m.
Results and Si
imulations ha
g simulation
0} and {B} =
e random patt
bit (Ai or Bi{01010101,
1111, 001100
0101, 00001
1111 and 001S and Vedic
ctively. Perfo
plier circuit a
pliers with v
multiplicati
it adders, a h
k (a) Sum block (
onal CMOS l
Vedic multi
st we describ of adiabatic
plex gates ca
S based DS network
EAL circuit
ck of Full ad
figure 5. Wy, consisting
two inputs an
ck of varyin
lator in 0.18μ
are taken wi
mulations
ve been don
we apply {A}{B7, B6, B5,B
rns consist of
where i = 00001111, 00
11 and 0001
111, 00110
10011}. Themultiplier are
mance meas
long with Ca
rying bit-size
on, we need
lf adder and a
) Carry block (c)
gic style is us
lier. In cas
the EEAL ga8x8 Vedic
n be easily i
VS network.e can imple
topology. DC
er circuits, a
e have designf common di
d three-input
g bit length
technology.h W/L = 12
under 1.8V
= {A7, A6, A, B3, B2, B1 a
four bits are a
to 7). The as110011,00010
0101} and {
11, 011100
simulated walso shown i
rement of 8×
ry-Save, Arra
s (2-bit, 4-bit,
four N/2×N
N/2 bit adder.
AND NAND blo
ed to impleme
e of adiabat
tes and thenultiplier usi
mplemented
In Fig. 1,ent the AN
S network f
ong with AN
ed an adiabatgital gates su
unctions, add
using Caden
W/L ratio of t /2 and 6 /
supply voltag
5,A4, A3, A2,d B0} as inpu
ssigned for ea
signed bits ar 101, 0001010
B}={0111001
11, 0001010
veform of 8 Figure 6 &
CMOS Ved
y, Wallace tr
and 8-bit) h
/2
k
nt
ic
eg
y
y-
or
D
ich
er
e
e
e.
1 s.
h
e;1,
1,
1,
87
ic
e
as
been c
are al
simulthe m
minim
is 180
Figu
ompared. Per
so compared
tions have beultiplier circu
um transistor
m.
e 6. Output wave
ormances of a
with the C
n done to veriits using CA
width in the 0
orm of 8×8 Conv
diabatic 8×8
OS counter
fy the functioENCE Spic
.18μm CMOS
entional(CMOS)
edic multiplie
art. Extensiv
ality of the al Spectra. Th
n-well proces
edic Multiplier
r
e
le
s
8
8/16/2019 Ultra Low Power Vedic Multiplier
5/6
cons
Sinc
multidirec
10M
30%
Wall
Figure 7. Outp
able 1 show
mption comp
greater nu
pliers, the poly extrapolat
z 2×2, 4×4 a
and 41% of t
ce tree multi
t waveform of 8×
s that Vedic
ared to other
bers of add
er savings fod to higher o
nd 8×8 Vedic
e total powe
plier respecti
8 Adiabatic Vedic
multiplier sho
optimized m
r cells are
smaller oper erand multipl
multiplier con
consumed b
ely. Table 1
Multiplier
ws least pow
ltiplier circui
sed for larg
nd sizes canier modules.
sume only 33
carry save a
also shows th
er
s.
er
eIn
,
d
at
Vedic
existi
multip produ
multip
almos
faster
multip
length69% (
multip
(EDP)
energ
Tablecarry
operat
(8×8)
16.9%array,
the fo
produworse
due to
EEAL
yet du
reducsaves
conve
Tab
Bit L
Conve
Mul
2
4
8
Bit L
Conve
Mul
2
4
8
multiplier is
g multiplier,
lier are gainets with their
lications tho
same speed
than the othe
lier is reporte
, delay of 4×451%) of the to
lier circuit unHence we
which shoul
is more re
2 shows thatsave and Bit-
ion yet deviat
Vedic multi
(33.4 %) anWallace tree
llowing resul
t (PDP) ofthan the PDP
the negligibl
logic. Thoug
e to very lowd significantl
almost 16.5%
tional 8x8 (2
le 1. Power dissip
circuits with var
ength
f
ntional
iplier
Power
Vedic
×2 27
×4 104
×8 892
ength
f
ntional
iplier Vedic
×2 0.23
×4 0.58
×8 1.38
considerabl
as the spe
d by paralleliconcurrent s
gh the other
et the Vedic
rs. Due to si
as 230 ps onl
(8×8) Vedictal delay sho
er same bit lealso compar
combine a
evant metric
though the enarray multipli
ions occur in
lier achieves
20% (28.6%and carry sav
ts can be su
he 8x8 convof the fully ad
amount of n
h adiabatic c
ower consumy. 8x8 (2x2)
(57.1%) of t
2) Vedic mul
ation, delay and E
ing bit lengths fo
consumption (μW)
Carry-save
81
427
2060
Delay (ns) of diffe
Carry-save
0.46
0.66
1.68
faster com
d improvem
ing the gener ummations. I
multiplier c
ultiplier is al
plicity, delay
y. However o
multiplier is 8n by carry-sa
gth conditione the energy
easure of pe
than Power-
ergy-delay pr rs are almost
4×4 and 8×8
almost 11.1
of total EDe multipliers.
marized, th
entional Vediiabatic Vedic
n-adiabatic lo
unterpart is l
ption, poweradiabatic V
tal energy co
iplier.
nergy-delay of C
180nm CMOS T
of different type o
Bit-array
92
449
2090
rent type of Multip
Bit-array
0.45
0.84
2.69
ared to othe
nts of Vedi
ation of parti case of 2×
rcuits achiev
ost two time
of 2×2 Vedi
increasing bi
8% (82%) ane and Bit arra
.-delay produ
rformance an
delay produc
duct of Vedi same for 2×
operation. 4×
1% (11.3 %
shown by BiFrom Table 2
power dela
c multiplier i8x8 multiplier
ss of propose
ittle bit slowe
elay product idic multiplie
nsumed by th
OS multiplier
echnology
Multiplier units
Wallace Tree [5]
185
389
2172
ier units
Wallace Tree
0.42
0.73
1.53
r
c
e
s
c
t
t
t
ss
r
s
re
8
8/16/2019 Ultra Low Power Vedic Multiplier
6/6
Bit Length
of
Conventional
Multiplier
Energy-Delay Product (×10-25 Js) comparison of different type
of Multiplier units
Vedic Carry-save Bit-arrayWallace Tree
2×2 0.14 0.17 0.173.20
4×4 3.50 18.80 30.5020.70
8×8 169.80 589.60 1505.10508.40
Table 2. Performance comparison of conventional and adiabatic Vedic
multiplier circuits with varying bit lengths at 10 MHz for 180nm Technology
Bit Length of
Multiplier
Power consumption (μW) of Multiplier
Conventional Vedic Adiabatic Vedic Savings (%)
2×2 27 9.64 64.3
4×4 104 45.76 56.0
8×8 892 526.28 41
Bit Length of
Multiplier
Propagation Delay (ns) of Multiplier
Conventional Vedic Adiabatic Vedic Savings (%)
2×2 0.23 0.25 -8.0
4×4 0.58 0.67 -15.5
8×8 1.38 1.87 -35.5
Bit Length of
Multiplier
Energy-Delay Product (×10-25 Js) comparison of Multiplier
Conventional Vedic Adiabatic Vedic Savings (%)
2×2 0.14 .06 57.1
IV.CONCLUSION
An energy efficient new adiabatic multiplier structure
based on Urdhva Tiryakbhyam sutra of Vedic mathematics has
been proposed using EEAL style. On basis of Cadence spectre
simulations, it can be concluded that this Vedic multiplier ismore efficient than array multiplier, Booth multiplier and
Wallace-Tree multiplier, in terms of timing efficiency and
speed. The speed improvements are gained by parallelizing the
generation of partial products with their concurrent
summations. It is also shown that energy efficiency can beenhanced significantly in low frequency domain using the
newly proposed adiabatic approach.
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