UCC28880 700V 最低静态电流离线开关 datasheet · 9 Power Supply Recommendations ... ICH1 Charging VDD Cap current VVDD = 4.4V, ... TA = 25°C 170 210 260 mA Static, TA =

AC Input Voltage (VRMS)

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mW

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50 100 150 200 250 3000

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1.2-W Buck No-load Input PowerUCC28880 Standby Power

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UCC28880

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Folder

Sample &Buy

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UCC28880ZHCSCP2 –JULY 2014

UCC28880 700V 最最低低静静态态电电流流离离线线开开关关

1 特特性性 3 说说明明

1• 集成式功率金属氧化物半导体场效应晶体管 UCC28880 在一个单片器件中集成了控制器和 700V(MOSFET)（开关），漏源电压额定值为 700V 功率 MOSFET。该器件还集成了高压电流源，能够在

• 集成高压电流源，用于生成内部低压电源经整流的市电电压下直接启动和运行。• 软启动

而且其静态电流较低，能够提供出色的效率。凭借• 自偏置开关（直接在经整流的市电电压下启动和运

UCC28880，使用最少的外部元件即可构建降压、降行）压/升压以及反激拓扑等最为常用的转换器拓扑。• 支持降压、降压/升压和反激拓扑结构

• 器件静态电流 <100μA UCC28880 集成了软启动功能，用于控制功率级启

• 性能优异，可防止电感器电流击穿动，能够最大程度减小对功率级元件的压力。

• 保护器器件件信信息息(1)

– 电流限制保护部部件件号号封封装装封封装装尺尺寸寸（（标标称称值值））

– 过载和输出短路保护小外形尺寸集成电路UCC28880 5.00mm x 6.20mm– 过热保护 (SOIC) (7)

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。2 应应用用

• AC-DC 电源（在温度和输入电压范围内的输出电流高达100mA）

• 计量、家庭自动化、基础设施开关模式电源(SMPS)

• 晶闸管 (TRIAC) 驱动器的低侧降压拓扑

• 家用电器、大型家用电器和发光二极管 (LED) 驱动器

功功率率与与输输入入电电压压间间的的关关系系简简化化电电路路原原理理图图

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SLUSC05

http://www.ti.com.cn/product/cn/UCC28880?dcmp=dsproject&hqs=pf

http://www.ti.com.cn/product/cn/UCC28880?dcmp=dsproject&hqs=sandbuy&#samplebuy

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http://www-s.ti.com/sc/techlit/SLUSC05.pdf

UCC28880ZHCSCP2 –JULY 2014 www.ti.com.cn

目目录录

7.2 Functional Block Diagram ......................................... 91 特特性性.......................................................................... 17.3 Feature Description................................................. 102 应应用用.......................................................................... 17.4 Device Functional Modes........................................ 103 说说明明.......................................................................... 1

8 Application and Implementation ........................ 144 修修订订历历史史记记录录 ........................................................... 28.1 Application Information............................................ 145 Pin Configuration and Functions ......................... 38.2 Typical Application .................................................. 146 Specifications......................................................... 3

9 Power Supply Recommendations ...................... 276.1 Absolute Maximum Ratings ...................................... 310 Layout................................................................... 276.2 Handling Ratings....................................................... 4

10.1 Layout Guidelines ................................................. 276.3 Recommended Operating Conditions....................... 410.2 Layout Example .................................................... 276.4 Thermal Information .................................................. 4

11 器器件件和和文文档档支支持持 ..................................................... 286.5 Electrical Characteristics........................................... 511.1 Trademarks ........................................................... 286.6 Switching Characteristics .......................................... 611.2 Electrostatic Discharge Caution............................ 286.7 Typical Characteristics .............................................. 711.3 术语表 ................................................................... 287 Detailed Description .............................................. 9

12 机机械械封封装装和和可可订订购购信信息息 .......................................... 287.1 Overview ................................................................... 9

4 修修订订历历史史记记录录

日日期期修修订订版版本本注注释释

2014 年 7 月 * 最初发布。

2 Copyright © 2014, Texas Instruments Incorporated


http://www.ti.com.cn

DRAIN

NC

HVIN

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GND

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VDD

UCC28880www.ti.com.cn ZHCSCP2 –JULY 2014

5 Pin Configuration and Functions

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.GND 1 G GroundGND 2 G GroundFB 3 I Feedback terminalVDD 4 O Supply pin, supply is provided by internal LDOHVIN 5 P Supply pinNC 6 N/C Not internally connectedDRAIN 8 P Drain pin

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1) (2)

MIN MAX UNITHVIN –0.3 700 (3) VDRAIN Internally 700 (3) V

clampedIDRAIN Positive drain current single pulse, pulse max duration 25 μs 320 mAIDRAIN Negative drain current –320 mAFB –0.3 6 VVDD –0.3 6 V

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. These ratings apply over theoperating ambient temperature ranges unless otherwise noted.

(3) TA = 25°C

Copyright © 2014, Texas Instruments Incorporated 3




6.2 Handling RatingsMIN MAX UNIT

Tstg Storage temperature range –65 150°C

Lead temperature 1.6 mm (1/16 inch) from case 10 seconds 260Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000pins (1)

Human Body Model (HBM) per ANSI/ESDA/JEDEC JS-001,V(ESD) Electrostatic discharge –1500 1500 VHVIN pin (1)

Charged device model (CDM), per JEDEC specification –500 500JESD22-C101, all pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITVVDD Voltage On VDD pin 5 VVFB Voltage on FB pin –0.2 5 VTA Operating ambient temperature –40 105 °CTJ Operating junction temperature –40 125 °C

6.4 Thermal InformationUCC28880

THERMAL METRIC (1) SOIC (D) UNIT7 PINS

RθJA Junction-to-ambient thermal resistance 134.4RθJC(top) Junction-to-case (top) thermal resistance 42.6RθJB Junction-to-board thermal resistance 85 °C/WψJT Junction-to-top characterization parameter 6.4ψJB Junction-to-board characterization parameter 76

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.




http://www.ti.com/cn/lit/pdf/spra953


6.5 Electrical CharacteristicsVHVIN = 30 V, TA = TJ = –40°C to 125°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITVHVIN(min) Minimum Voltage to startup 30 VINL Internal supply current, no load FB = 1.25 V (> VFB_TH) 58 100 µA

Internal supply current, fullIFL FB = 0.75 V (> VFB_TH) 72 120 µAloadICH0 Charging VDD Cap current VVDD = 0 V, –3.8 –1.6 –0.4 mAICH1 Charging VDD Cap current VVDD = 4.4V, VFB = 1.25 V –3.40 –1.30 –0.25 mA

Internally regulated lowVVDD Voltage supply (supplied from 4.5 5.0 5.5 V

HVIN pin)VFB_TH FB pin reference threshold 0.94 1.02 1.10 VVVDD(on) VDD turn-on threshold VDD low-to-high 3.55 3.92 4.28 V

VDDON - VDD turn-offΔVVDD(uvlo) VDD high-to-low 0.28 0.33 0.38 VthresholdDMAX Maximum Duty Cycle FB = 0.75 V 45% 55%

Static, TA = –40°C 300 mAILIMIT Current Limit Static, TA = 25°C 170 210 260 mA

Static, TA = 125°C 140 mAThermal ShutdownTJ(stop) Internal junction temperature 150 °CTemperature

TJ(hyst) Thermal Shutdown Hysteresis Internal junction temperature 50 °CPower Mosfet BreakdownBV TJ = 25°C 700 °CVoltagePower MOSFET On- ID = 30 mA, TJ = 25°C 32 40 Ω

RDS(on) Resistance (includes internalID = 30 mA, TJ = 125°C 55 68 Ωsense-resistor)VDRAIN = 700V, TJ = 25°C 5 µAPower MOSFET off stateDRAIN_ILEAKAGE leakage current VDRAIN = 400 V, TJ = 125°C 20 µAVHVIN = 700 V, TJ = 25°C, VVDD = 4.0 7.5 12.0 µA5.8 V

HVIN_IOFF HVIN off state currentVHVIN = 400 V, TJ = 125°C, VVDD = 20 µA5.8 V





6.6 Switching Characteristicsover operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITfSW(max) Maximum switching frequency 52 62 75 kHz

Maximum switch on time (currenttON_MAX FB = 0.75 V 5.7 7.6 9.5 µslimiter not triggered),Minimum switch off time followstOFF_MIN FB = 0.75 V 5.7 7.6 9.5 µsevery tON time,

tMIN Minimum on time 0.17 0.22 0.30 µsMax off time (OL condition), tOFF(ovl)tOFF(ovl) 130 200 270 µs= tSW – tON(max)




Temperature (°C)

VV

DD

(on)

and

'V

DD

(uvl

o) (

norm

aliz

ed to

25°

C)

-50 0 50 100 1500.985

0.99

0.995

1

1.005

1.01

1.015

D013

VVDD(on)'VDD(uvlo)

DRAIN Voltage

DR

AIN

Cur

rent

(m

A)

0 10 20 30 40 50 60 700

50

100

150

200

250

300

350

400

450

500

D006

IdrainIdrain

Temperature (°C)

Nor

mal

ized

Cha

nnel

Cur

rent

(A

)

-40 -25 -10 5 20 35 50 65 80 95 110 1250.4

0.6

0.8

1

1.2

1.4

1.6

D008

ICHOICH1

Temperature (°C)

I FL

and

I NL

(nor

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ized

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Inpu

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-40 -25 -10 5 20 35 50 65 80 95 110 1250

10

20

30

40

50

60

70

80

90

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D002

IDDFLIDDNL


6.7 Typical Characteristics

Figure 1. ILIMIT vs Temperature Figure 2. ILIMIT vs Drain Current Slope

Figure 3. INL and IFL vs Temperature Figure 4. ICH0 and ICH1 vs Temperature

Figure 5. VVDD(on) and ΔVUVLO vs Temperature Figure 6. IDS vs VDS at 25°C and 125°C




Temperature (°C)

VD

DO

N V

olta

ge (

V)

-40 -25 -10 5 20 35 50 65 80 95 110 1250.98

0.99

1

1.01

1.02

1.03

1.04

1.05

1.06

D008

tOFF(max)tON(min)

Temperature (°C)

L MIN

/VIN

(PH

/V)

0 30 60 90 120 1502.1

2.2

2.3

2.4

2.5

2.6

2.7

D014

Temperature (°C)

Fee

dbac

k V

olta

ge (

V)

-40 -25 -10 5 20 35 50 65 80 95 110 1250.96

0.97

0.98

0.99

1

1.01

1.02

D005Temperature (°C)

FS

W(m

ax) (

norm

aliz

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25°

C)

-50 0 50 100 1500.96

0.97

0.98

0.99

1

1.01

1.02

D012


Typical Characteristics (continued)

Figure 7. Maximum Switching Frequency vs Temperature Figure 8. VFB_TH vs Temperature

Figure 10. (LMIN/VIN )MIN vs TemperatureFigure 9. tON(max) and tOFF(min) vs Temperature




3

4 LDO

Control and Reference

8

VDD

IFB = 1 V

DRAIN

5

HVIN

FB

UVLO

+ PWM Controller and Output Short Circuit Protection

LEB

Leading Edge Blanking Time

S Q

QR

Current Limit

1, 2

GND

Gate

High Voltage Current Source

Thermal Protection


7 Detailed Description

7.1 OverviewThe UCC28880 integrates a controller and a 700-V power MOSFET into one monolithic device. The device alsointegrates a high-voltage current source, enabling start up and operation directly from the rectified mains voltage.

The low-quiescent current of the device enables excellent efficiency. The device is suitable for non-isolated AC-to-DC low-side buck and buck-boost configurations with level-shifted direct feedback, but also more traditionalhigh-side buck, buck boost and low-power flyback converters with low standby power can be built using aminimum number of external components.

The device generates its own internal low-voltage supply (5 V referenced to the device’s ground, GND) from theintegrated high-voltage current source. The PWM signal generation is based on a maximum constant ON-time,minimum OFF-time concept, with the triggering of the ON-pulse depending on the feedback voltage level. EachON-pulse is followed by a minimum OFF-time to ensure that the power MOSFET is not continuously driven in anON-state. The PWM signal is AND-gated with the signal from a current limit circuit. No internal clock is required,as the switching of the power MOSFET is load dependent. A special protection mechanism is included to avoidrunaway of the inductor current when the converter operates with the output shorted or in other abnormalconditions that can lead to an uncontrolled increase of the inductor current. This special protection feature keepsthe MOSFET current at a safe operating level. The device is also protected from other fault conditions withthermal shutdown, under-voltage lockout and soft-start features.

7.2 Functional Block Diagram





7.3 Feature DescriptionThe device integrates a 700-V rated power MOSFET switch, a PWM controller, a high-voltage current source tosupply a low-voltage power supply regulator, a bias and reference block, and the following protection features,current limiter, Over Temperature Protection (OTP), Under Voltage Lockout (UVLO) and overload protection forsituations like short circuit at the output.

In low-side buck and buck-boost topologies, the external level-shifted direct feedback circuit can be implementedby two resistors and a high-voltage PNP transistor.

The positive high-voltage input of the converter node (VIN+) functions as a system reference ground for theoutput voltage in low-side topologies. In the low-side buck topology the output voltage is negative with respect tothe positive high-voltage input (VIN+), and in low-side buck-boost topology the output voltage is positive withrespect to the positive high-voltage input (VIN+).

In high-side buck configuration, as well as in non-isolated flyback configuration, the output voltage is positive withrespect to the negative high-voltage input (VIN-), which is the system reference ground.

The device has a low-standby power consumption (no-load condition), only 18 mW (typical) when connected to a230-VAC mains and 9 mW when connected to an 115-VAC mains.

The standby power does not include the power dissipated in the external feedback path, the power dissipated inthe external pre-load, the inductor in the freewheeling diode and the converter input stage (rectifiers and filter).

7.4 Device Functional Modes

7.4.1 Startup OperationThe device includes a high-voltage current source connected between the HVIN pin and the internal supply forthe regulator. When the voltage on the HVIN pin rises, the current source is activated and starts to supply currentto the internal 5-V regulator. The 5-V regulator charges the external capacitor connected between VDD pin andGND pin. When the VDD voltage exceeds the VDD turn on threshold (VVDD(on)) device starts operations. Theminimum voltage across HVIN and GND pins to ensure enough current to charge the capacitance on VDD pin isVHVIN(min). At the First switching cycle the minimum MOSFET off time is set to be > 100 μs and cycle-by-cycle isprogressively reduced up to tOFF(min) providing soft start.

7.4.2 Feedback and Voltage Control LoopThe feedback circuit consists of a voltage comparator with the positive input connected to an internal referencevoltage (referenced to GND) and the negative input connected to FB pin. When the feedback voltage at the FBpin is below the reference voltage VFB_TH logic high is generated at the comparator output. This logic hightriggers the PWM controller, which generates the PWM signal turning on the MOSFET. When the feedbackvoltage at the FB pin is above the reference voltage, it indicates that the output voltage of the converter is abovethe targeted output voltage set by the external feedback circuitry and MOSFET cannot be turned on.




FB_COMP_OUT

PWM

CURRENT LIMIT

GATE

RSTN

t

t

t

t

t

t

VFB_TH

VFB

tON(max) tOFF(min) tON(max) tOFF(min) tON(max) tOFF(min) tON(max) tOFF(min)


Device Functional Modes (continued)7.4.3 PWM ControllerThe PWM controller's input comes from the feedback comparator. When the feedback comparator output goeshigh, the PWM controller is triggered. This starts the ON-time generation. The ON-time pulse is defined astON(max) and at the end of every ON-time pulse an OFF-time (logic low) pulse starts. The OFF-time pulse is longas tOFF(min) during converter normal operation, it can be longer up to tOFF(ovl) at start up or if risk of inductorcurrent runaway is detected. The output of the PWM controller is the PWM signal (See Figure 11). After the OFF-time pulse has ended, the PWM controller can again receive the feedback comparator’s output. If the feedbackcomparator’s output is still high, then a new ON-time pulse followed by an OFF-time pulse is generated for thePWM signal. If the feedback comparator’s output is low at the point the OFF-time has ended, then the PWMcontroller continues to output a logic low signal at the output (the PWM signal). The PWM signal stays low untilthe feedback comparator output goes high, at which point the PWM controller is again triggered, and the ON-time+ OFF-time pulse is generated.

The PWM controller does not need a clock signal, and the PWM signal is load dependent. The PWM signal’smaximum frequency is set to fSW(max) = (1/(tON(max) + tOFF(min))) which occurs when the voltage on the FB pin iscontinuously below VFB_TH.

Figure 11. UCC28880 Timing Diagram




PWM

Gate

Current Limit

Increase tOFF

( Decrease fSW )

ILIMIT

Drain Current

CNT_IN

tON_MAX tOFF

LEB

~200 ns

Decrease tOFF

(Increase fSW )

tON_TO

tON_TO tON_TO

Inductor Current

t

t

t

t

t

t

t

~200 ns

tON tON


Device Functional Modes (continued)7.4.4 Current LimitThe current limit circuit senses the current through the power MOSFET. The sensing circuit is located betweenthe source of the power MOSFET and the GND pin. When the current in the power MOSFET exceeds thethreshold ILIMIT, the internal current limit signal goes high, which sets the internal RSTN signal low. This disablesthe power MOSFET by driving its gate low. The current limit signal is set back low after the falling edge of thePWM signal. After the rising edge of the GATE signal, there is a blanking time. During this blanking time, thecurrent limit signal cannot go high.

7.4.5 Inductor Current Runaway ProtectionTo protect the device from overload conditions, including a short circuit at the output, the PWM controllerincorporates a protection feature which prevents the inductor current from runaway. When the output is shortedthe inductor demagnetization is very slow, low di/dt, and when the next switching cycle starts energy stored inthe inductance is still high. After the MOSFET switches on, the current starts to rise from pre-existing DC valueand reaches the current-limit value in a short duration of time. Because of the intrinsic minimum on-time of thedevice the MOSFET on-time cannot be lower than tMIN, in an overload or output short circuit the energyinductance is not discharged sufficiently during MOSFET off-time, it is possible to lose control of the currentleading to a runaway of the inductor current. To avoid this, if the ON time is less than tON_TO (tON_TO is a deviceinternal time out), the controller increases the MOSFET OFF time (tOFF). If the MOSFET ON-time is longer thantON_OL then tOFF is decreased. The controller increases tOFF, cycle-by-cycle, through discrete steps until the ON-time continues to stay below tON_TO. The tOFF is increased up to tOFF(ovl) after that, if teh ON-time is still belowtON_OL the off time is kept equal to tOFF(ovl). The controller decreases tOFF cycle-by-cycle until the ON-timecontinues to stay above tON_TO up to tOFF(min). This mechanism prevents control loss of the inductor current andprevents over stress of the MOSFET (see typical waveforms in Figure 12 and Figure 13). At start up, the tOFF isset to tOFF(ovl) and reduced cycle-by-cycle (if the ON time is longer than tON_TO) up to tOFF(min) providing a soft startfor the power stage.

Figure 12. Current Runaway Protection Logic Timing Diagram




MINR(max) IN(max)

IN MIN

LL T V

V

ª º§ ·! u« »¨ ¸« »© ¹¬ ¼

INDUCTOR

CURRENT

DRAIN

CURRENTt

t

GATE

t

Output Shorted Here

tON_TO

tON < tON_TO

tON_TO

tON < tON_TO tON < tON_TO

tON_TO tON_TO

tON < tON_TO

tON_TO

ILIMIT

VFB_TH

VFB


Device Functional Modes (continued)

Figure 13. Current Runaway Protection, Inductor and MOSFET Current

A minimal value needs to be imposed on the inductance value to avoid nuisance tripping of the protection featurethat prevents the loss of control of the inductor current. Inadvertent operation of the protection feature limits theoutput-power capability of the converter. This condition depends on the converter's maximum input operatingvoltage and temperature. Use Equation 1 to calculate your minimum inductance value.

(1)

The value of Equation 1 can be found by characterization graph of Figure 10.

If the inductance value is too low, such that the MOSFET on-time is always less than tON_TO timeout and thedevice progressively increases the MOSFET off-time up to tOFF(ovl), the output power is reduced and theconverter fails to supply the load.

7.4.6 Over-Temperature ProtectionIf the junction temperature rises above TJ(stop), the over-temperature protection is triggered. This disables thepower MOSFET switching. To re-enable the switching of the MOSFET the junction temperature has to fall byTJ(hyst) below the TJ(stop) where the device moves out of over temperature.




HVIN

VDD

FB

DRAIN

GND

UCC28880

CVDD

100 nF10 V

C24.7 PF400 V

C14.7 PF400 V

D21N4937

D31N4007

10

AC(115 V/230 V)

RFB1

590 k:+/- 1%

CL

4.7 PF16 V

RL

402 k:

RFB2

51 k:+/- 1%

Q1500 V

L12.2 mH330 mA

L21 mH

VOUT12 V

100 mA

+

-

D1600 VW5575 ns


8 Application and Implementation

8.1 Application InformationThe UCC28880 can be used in various application topologies with direct or isolated feedback. The device can beused in low-side buck, where the output voltage is negative, or as a low-side buck-boost configuration, where theoutput voltage is positive. In both configurations the common reference node is the positive input node (VIN+).The device can also be configured as a LED driver in either of the above mentioned configurations. If theapplication requires the AC-to-DC power supply output to be referenced to the negative input node (VIN-), theUCC28880 can also be configured as a traditional high-side buck as shown in Figure 17. In this configuration,the voltage feedback is sampling the output voltage VOUT, making the DC regulation less accurate and loaddependent than in low-side buck configuration, where the feedback is always tracking the VOUT. However, high-conversion efficiency can still be obtained.

8.2 Typical Application

8.2.1 12-V, 100-mA Low-Side Buck ConverterFigure 14 shows a typical application example of a non-isolated power supply, where the UCC28880 isconnected in a low-side buck configuration having an output voltage that is negative with respect to the positiveinput voltage (VIN+). The output voltage is set to 12 V in this example, but can easily be changed by changingthe value of RFB1. This application can be used for a wide variety of household appliances and automation, orany other applications where mains isolation is not required.

Figure 14. Universal Input, 12-V, 100-mA Output Low-Side Buck

8.2.1.1 Design Requirements

Table 1. Table 1 Design specificationDESCRIPTION MIN MAX UNIT

Design InputVIN AC input voltage 85 265 VRMS

fLINE Line frequency 47 63 HzIOUT Output current 0 100 mADesign RequirementsPNL No-load input power 50 mWVOUT Output voltage 12 13 VΔVOUT Output voltage ripple 350 mVη Converter efficiency 68%




BULK(min)

BULKn(min)CBULK

CC 8.7 F

1 TOL! P

BULK(min)IN

LINE(min) IN(min)BULKmin 2 2

IN(min) BULK(min)

V2 P 1 1arccos

f RCT 2 2 VC

2 V V

½§ ·u ° °¨ ¸u u® ¾¨ ¸uS u° °© ¹¯ ¿

u


8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Input Stage (RF, D2, D3, C1, C2, L2)• Resistor RF is a flame-proof fusible resistor. RF limits the inrush current, and also provide protection in case

any component failure causes a short circuit. Value for its resistance is generally selected between 4.7 Ω to15 Ω.

• A half-wave rectifier is chosen and implemented by diode D2 (1N4937). It is a general purpose 1-A, 600-Vrated diode. It has a fast reverse recovery time (200 ns) for improved differential-mode-conducted EMI noiseperformance. Diode D3 (1N4007) is a general purpose 1-A, 1-kV rated diode with standard reverse recoverytime (>500 ns), and is added for improved common-mode-conducted EMI noise performance. D3 can beremoved and replaced by a short if not needed.

• EMI filtering is implemented by using a single differential-stage filter (C1-L2-C2).

Capacitors C1 and C2 in the EMI filter also acts as storage capacitors for the high-voltage input DC voltage(VIN).The required input capacitor size can be calculated according formula (1).

where• CBULK(min) is minimum value for the total input capacitor value (C1 + C2 in the schematic of Figure 14).• RCT = 1 in case a single wave rectifier and RCT = 2 in case of full-wave rectifier (for the schematic reported in

Figure 20 RCT = 1 because of a single rectifier).• PIN is the converter input power.• VIN(min) is the minimum RMS value of the AC input voltage.• VBULK(min) is the minimum allowed voltage value across bulk capacitor during converter operation.• fLINE(min) is the minimum line frequency when the line voltage is VIN(min).

The converter input power can be easily calculated as follow:• The converter maximum output power is: POUT = IOUT x VOUT = 0.1 A x 12.5 V = 1.25 W• Assuming the efficiency η = 68.% the input power is PIN = POUT/η = 1.765 W

Using the following values for the other parameters• VBULK(min) = 80 V• VIN(min) = 85 VRMS (from design specification table)• fLINE(min) = 57 Hz (2)

CBULK(min) = 6.96 μF. Considering that electrolytic capacitors, generally used as bulk capacitor, have 20% oftolerance in value, the minimum nominal value required for CBULK is:

(3)

Select C1 and C2 to be 4.7μF each (CBULK = 4.7 μF + 4.7 μF = 9.4 μF > CBULKn(min)).

By using a full-wave rectifier allows a smaller capacitor for C1 and C2, almost 50% smaller.

8.2.1.2.2 Regulator Capacitor (CVDD)

Capacitor CVDD acts as the decoupling capacitor and storage capacitor for the internal regulator. A 100-nF, 10-Vrated ceramic capacitor is enough for proper operation of the device's internal LDO.




IN(max)MINJ(max) IN(max) ON_ TO

IN LIMIT

VL HL1 MIN T V L1 t 2.65 375V 1mH

V I V

ª º§ · P§ ·! u ! u u u #« »¨ ¸ ¨ ¸

© ¹« »© ¹¬ ¼

OUT d

L SW _ VIN(max)

V VL1 2mH

I f

! ' u

MINSW _ VIN(max) SW(max) SW(max)

ON_ TO

DF MIN f f 66kHz

t

§ · ¨ ¸

¨ ¸© ¹

OUT dMIN

IN(max) d

V VD 3.61%

V V

MINSW _ VIN(max) SW(max)

ON _ TO

DF MIN f

t

§ · ¨ ¸

¨ ¸© ¹

OUT OUT dMIN

LIMIT IN(max) d

I V VD 2

I V V

u

OUT dMIN

IN(max) d

V VD

V V

2L LIMIT LIMIT OUTI MIN I I I' u

D1(max) IN(max)V 2 V 2 265V 375V u u


8.2.1.2.3 Freewheeling Diode (D1)

The freewheeling diode has to be rated for high-voltage with as short as possible reverse-recovery time (trr).

The maximum reverse voltage that the diode should experience in the application, during normal operation, isgiven by Equation 4.

(4)

A margin of 20% is generally considered.

The chosen freewheeling diode for the application example is a 600-V, 1-A rated diode with a trr ≤ 75 ns. It ispossible to use a diode with higher trr but this leads to higher switching losses and lower efficiency.

8.2.1.2.4 Inductor (L1)

Initial calculations:

Ripple current at full load:

(5)

Average MOSFET conduction minimum duty cycle at full load and maximum input voltage is:

(6)

If the converter operates in continuous conduction mode:

(7)

Maximum allowed switching frequency at VIN_MAX and full load:

(8)

ILIMIT = 150 mA, the worst case but assuming ΔIL = 100mA.

The converter works in continuous conduction mode (ΔIL < ILIMIT) so the

(9)

The maximum allowed switching frequency is:

(10)

The duty cycle does not force the MOSFET on time to go below tON_TO. If DMIN/TON_TO < fSW(max), the switchingfrequency is reduced by current runaway protection and the maximum average switching frequency is lower thanfSW(max).

The minimum inductance value satisfies both the following conditions:

(11)

(12)

In the application example, 2.2 mH is selected as the minimum standard value that satisfy Equation 11 andEquation 12.




OUTESR

LIMIT

VR 1

I

' :

LIMIT OUTL

SW(max) OUT

I I 270mA 100mAC 4 4 30 F

f V 350mV 66kHz

! u u Pu' u


8.2.1.2.5 Output Capacitor (CL)

The value of the output capacitor impacts the output ripple. Depending on the combination of capacitor value andequivalent series resistor (RESR). A larger capacitor value also has an impact on the start-up time. For a typicalapplication, the capacitor value can start from 47 μF, to hundreds of μF. A guide for sizing the capacitor valuecan be calculated by the following equations:

(13)

(14)

Take into account that both CL and RESR contribute to output voltage ripple. A first pass capacitance value can beselected and the contribution of CL and RESR to the output voltage ripple can be evaluated. If the total ripple istoo high the capacitance value has to increase or RESR value must be reduced. In the application example CLwas selected (47 µF) and it has an RESR of 0.3 Ω. So the RESR contributes for 1/3 of the total ripple. The formulathat calculates CL is based on the assumption that the converter operates in burst of four switching cycles. Thenumber of bursts per cycle could be different, the formula for CL is a first approximation.

8.2.1.2.6 Load Resistor (RL)

The resistor should be chosen so that the output current in any standby/no-load condition is higher than theleakage current through the integrated power MOSFET. If the standby load current is ensured to always belarger than the specified ILEAKAGE, the RL is not needed. If OVP protection is required for safety reasons, then azener could be placed across the output (not fitted in the application example). In the application example RL =402 kΩ. This ensures a minimum load current of at least ~30 µA when VOUT = 12 V.




OUT BEFB1 FB1

FB _ TH

V V 12V 0.5 VR R 51k 586k

V 1 V

u u : :

FB _ THFB2

FB

V 1.0 VR 50k

I 20 A :

| P

FB1OUT FB _ TH BE

FB2

RV V V

R u


8.2.1.2.7 Feedback Path (Q1, RFB1, RFB2)

The feedback path of Q1, RFB1 and RFB2 implements a level-shifted direct feedback. RFB2 sets the currentthrough the feedback path, and RFB1 sets the output voltage. Q1 acts as the level shifter and needs to be ratedfor high voltage. The output voltage is determined as follows:

where• VOUT is the output voltage.• VFB_TH is the FB pin voltage threshold = VFB_TH.• VBE is the base-Emitter saturation voltage of the external PNP transistor.• RFB1 is the external resistor setting the output voltage (depending on the current set by RFB2, and the Vbe).• RFB2 is the external resistor setting the current through the external feedback path. (15)

For the application example a target of ~20-μA of current is selected through the external feedback path (IFB).

(16)

Choose a standard resistor size for RFB2 = 51 kΩ. For the high-voltage PNP transistor choose a 500-V ratedtransistor with a VBE ≈ 0.5 V for the feedback current. To achieve the 12-V output voltage RFB1 needs to be:

(17)

Choose a standard resistor size for RFB1 = 591 kΩ.

To change the output voltage, change the value for RFB1. For example, to target a 5-V output voltage, RFB1should be changed to a 230-kΩ resistor.

Accuracy of the output-voltage level depends proportionally on the variation of VFB_TH, and on the absoluteaccuracy of VBE according to Equation 16 and Equation 17.

The current through the feedback path is connected over the high voltage input (VIN), and this feedback currentis always on. Higher current provides less noise-sensitive feedback, the feedback current should be minimized inorder to minimize the total power consumption.




Output Power (W)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.50

10

20

30

40

50

60

70

80

90

D016

85 V115 V230 V265 V

Ouput Current (A)

Out

put V

olta

ge (

V)

0 0.05 0.1 0.15 0.2 0.250

2

4

6

8

10

12

14

D017

85 V115 V230 V265 V


8.2.1.3 Application CurvesFigure 15 shows the efficiency diagram of the converter, a design previous discussed. Figure 16 shows theoutput voltage vs output current diagram. The two diagrams were obtained by measuring efficiency (Figure 15),output current and output voltage (Figure 16) moving resistive load value from infinite (load disconnected) up tozero (output shorted). The different curves of the diagram correspond to different AC input voltage.

Figure 15. Efficiency vs Output Power Diagrams Figure 16. Output Voltage vs Output Current Diagram

Table 2 shows converter efficiency. Table 3 shows the converter input power in no-load conditions and outputshorted conditions. The no-load condition shows the converter stand-by performance.

Table 2. Converter EfficiencyVIN_AC (VRMS) LOAD (mA) EFFICIENCY (%) AVERAGE EFFICIENCY (%)

25 80.350 81.4

115 81.375 81.6100 81.925 78.550 81.1

230 81.275 82.1100 82.7

Table 3. No-Load and Output Shorted Converter Input PowerVIN (VRMS) NO LOAD PIN (mW) OUTPUT SHORTED PIN (mW) OUTPUT SHORTED IOUT (mA)

85 16 453 214115 19.5 435 213140 22.5 417 211170 26 443 213230 33 430 209265 37.5 344 182




HVIN

VDD

FB

DRAIN

GND

UCC28880

VIN

+

-

RFB2

RFB1

CFB

CL

D4

D1VOUT

+

-RL

RF

C1

C2

CVDD

L2D2

D3

L1


8.2.2 12-V, 100-mA, High-Side Buck ConverterFigure 17 shows a typical application example of a non-isolated power supply, where the UCC28880 isconnected in a high-side buck configuration having an output voltage that is positive with respect to the negativehigh-voltage input (VIN-).

Figure 17. High-Side Buck Converter Schematic

8.2.2.1 Design Requirements

Table 4. 2 Design specificationDESCRIPTION MIN MAX UNIT

Design InputVIN AC input Voltage 85 265 VRMS

fLINE Line frequency 47 63 HzIOUT Output current 0 100 mADesign requirementsPNL No-load input power 50 mWVOUT Output voltage 12 14 VΔVOUT Output voltage ripple 250 mVη Converter efficiency 68%




FB FB FB1 FB2 L L1

C R R C R10

W u # u u

OUT(T) d4 d1 FB _ TH OUT(T) FB _ THFB1

FB2 FB _ TH FB _ TH

V V V V V VRR V V

#


8.2.2.2 Detailed Design ProcedureThe low-side buck converter and high-side buck converter design procedures are very similar.

8.2.2.2.1 Feedback path (CFB, RFB1 and RFB2) and Load Resistor (RL)

In low-side buck converter the output voltage is always sensed by the FB pin and UCC28880 internal controllercan turn on the MOSFET on VOUT. In high-side buck converter applications the information on the outputvoltage value is stored on CFB capacitor. This information is not updated in real time. The information on CFBcapacitor is updated just after MOSFET turn-off event. When the MOSFET is turned off, the inductor currentforces the freewheeling diode (D1 in Figure 17) to turn on and the GND pin of UCC28880 goes negative at -Vd1(where Vd1 is the forward drop voltage of diode D1) with respect to the negative terminal of bulk capacitor (C1 inFigure 17). When D1 is on, through diode D4, the CFB capacitor is charged at VOUT – Vd4 + Vd1. Set the outputvoltage regulation level using Equation 18.

where• VFB_TH is the FB pin reference voltage.• VOUT_T is the target output voltage.• RFB1, RFB2 is the resistance of the resistor divider connected with FB pin (see Figure 17)• The capacitor CFB after D1 is discharged with a time constant that is τfb = CFB x (RFB1 + RFB2 ).• Select the time constant τFB, given in Equation 19 (18)

(19)

The time constant selection leads to a slight output-voltage increase in no-load or light-load conditions. In orderto reduce the output-voltage increase, increase τFB. The drawback of increasing τFB is t in high-load conditionsVOUT could drop.




Output Current (A)

Out

put V

olta

ge (

V)

0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.2250

2

4

6

8

10

12

14

D018

85 V115 V230 V265 V

Output Power (W)

Effi

cien

cy (

%)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.2505

101520253035404550556065707580

D020

85 V115 V230 V265 V


8.2.2.3 Application CurvesFigure 18 shows the output voltage vs output current. Different plots correspond to different converter AC inputvoltages. Figure 19 shows efficiency changes vs output power. Different plots correspond to different converterAC input voltages.

Figure 18. Output IV Characteristic Figure 19. Efficiency vs POUT

Table 5. Converter EfficiencyVIN_AC (VRMS) LOAD (mA) EFFICIENCY (%) AVERAGE EFFICIENCY (%)

115 25 75.2 76.850 77.175 77.6100 77.7

230 25 72.6 74.850 75.175 75.7100 76.3

Table 6. No-Load and Output Shorted Converter Input PowerVIN (VRMS) NO LOAD PIN (mW) OUTPUT SHORTED PIN (mW) OUTPUT SHORTED IOUT (mA)

85 31 415 212115 34 399 209140 36 414 211170 38 401 208230 44 394 195265 47 333 174




HVIN

VDD

FB

DRAIN

GND

UCC28880

L1

CL

D1

RSENSEC1

R1

R2

Q2

Q1

Current Feedback

RFB1

RFB1

VOUT

VIN

+

-

HVIN

VDD

FB

DRAIN

GND

UCC28880

L1

RFB2

RFB1

CL

VIN

VOUT

D1

Q1

+

-

+

-


8.2.3 Additional UCC28880 Application Topologies

8.2.3.1 Low-Side Buck and LED Driver – Direct Feedback (level-shifted)Features include:• Output Referenced to Input• Negative Output (VOUT) with Respect to VIN+• Step Down: VOUT < VIN• Direct Level-Shifted Feedback

Figure 20. Low-Side Buck – Direct feedback (level-shifted)

Figure 21. Low-Side Buck LED Driver – Direct feedback (level-shifted)




HVIN

VDD

FB

DRAIN

GND

UCC28880

VIN

+

-

RFB2

D1

L1

VOUT

+

-

CL

HVIN

VDD

FB

DRAIN

GND

UCC28880

VIN

+

-

RFB2

10

CFB

CL

D2

D1

L1

VOUT

+

-


8.2.3.2 12-V, 100-mA High-Side Buck ConverterFeatures include:• Output Referenced to Input• Positive Output (V ) with Respect to VIN-• Step Down (VOUT < VIN)

Figure 22. High-Side Buck Converter Schematic

8.2.3.3 Non-Isolated, Low-Side Buck-Boost ConverterFeatures Include:• Output referenced to input• Positive output (VOUT) with respect to VIN+• Step Up, Step Down: VOUT </> VIN• Direct Level-Shifted Feedback

Figure 23. Low-Side Buck-Boost Converter




HVIN

VDD

FB

DRAIN

GND

UCC28880

RFB2

RFB1

CVDD

RFB2

CL

VIN

+

-

VOUT+

-

HVIN

VDD

FB

DRAIN

GND

UCC28880

VIN

+

-

RFB2

RFB1

CFB

CL

D2

D1L1

VOUT+

-


8.2.3.4 9.5 Non-Isolated, High-Side Buck-Boost ConverterFeatures include:• Output Referenced to Input• Positive Output (VOUT) with Respect to VIN-• Step Up, Step Down: VOUT </> VIN

Figure 24. High-Side Buck-Boost Converter

8.2.3.5 9.6 Non-Isolated Flyback ConverterFeatures include:• Output Referenced to Input• Positive Output (VOUT) with Respect VIN-• Direct Feedback

Figure 25. Non-Isolated Flyback Configuration




HVIN

VDD

FB

DRAIN

GND

UCC28880

RFB

CVDD

RFB2

CL

VIN

+

-

VOUT+

-


8.2.3.6 Isolated Flyback ConverterFeatures include:• Output Isolated from• Input Direct Feedback

Figure 26. Isolated Flyback Converter




VDD

DRAINGND

FB NC

HVIN

AC INPUT

DC OUTPUT

GND

L2

C1 C2

RF

D2

D3

RFB2Q1

60 m

ils

L1D1

= top layer

= bottom layer

= connect top and bot

RFB1

RL

CL

VDD


9 Power Supply RecommendationsThe VDD capacitor recommended value is 100 nF to ensure high phase margin of the internal 5V- regulator andit should be placed close to VDD pin and GND pins to minimize the series resistance and inductance.

The VDD pin provides a regulated 5V output but it is not intended as a supply for external load. Do not supplyVDD pin with external voltage source (for example the auxiliary winding of flyback converter).

Always keep GND pin 1 and GND pin 2 connected together with the shortest possible connection.

10 Layout

10.1 Layout Guidelines• In both buck and buck-boost low-side configurations, the copper area of the switching node DRAIN should be

minimized to reduce EMI.• Similarly, the copper area of the FB pin should be minimized to reduce coupling to feedback path. Loop CL,

Q1, RFB1 should be minimized to reduce coupling to feedback path.• In buck and buck-boost high side the GND, VDD and FB pins are all part of the switching node so the copper

area connected with these pins should be minimized• Minimum distance between 700-V coated traces is 1.41 mm (60 mils).

10.2 Layout ExampleFigure 27 shows and example PCB layout for UCC28880 in low-side buck configuration.

Figure 27. UCC28880 Layout Example





11 器器件件和和文文档档支支持持

11.1 TrademarksAll trademarks are the property of their respective owners.

11.2 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.3 术术语语表表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

12 机机械械封封装装和和可可订订购购信信息息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。




http://www.ti.com/cn/lit/pdf/SLYZ022

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http://www.ti.com.cn/home_a_vi

http://www.ti.com.cn/microcontrollers

http://www.ti.com.cn/rfidsys

http://www.ti.com/omap

http://www.ti.com.cn/home_p_wirelessconnectivity

PACKAGE OPTION ADDENDUM

www.ti.com 7-Aug-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

UCC28880D ACTIVE SOIC D 7 75 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28880

UCC28880DR ACTIVE SOIC D 7 2500 Green (RoHS& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 U28880

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

http://www.ti.com/product/UCC28880?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/UCC28880?CMP=conv-poasamples#samplebuy

http://www.ti.com/productcontent

PACKAGE OPTION ADDENDUM

www.ti.com 7-Aug-2014

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com

PACKAGE OUTLINE

C

.228-.244 TYP[5.80-6.19]

.069 MAX[1.75]

.100[2.54]

7X .012-.020 [0.31-0.51]

2X.150[3.81]

.005-.010 TYP[0.13-0.25]

0 - 8 .004-.010[0.11-0.25]

.010[0.25]

.016-.050[0.41-1.27]

4X .050[1.27]

A

.189-.197[4.81-5.00]

NOTE 3

B .150-.157[3.81-3.98]

NOTE 4

(.041)[1.04]

SOIC - 1.75 mm max heightD0007ASMALL OUTLINE INTEGRATED CIRCUIT

4220728/A 01/2018

NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash.5. Reference JEDEC registration MS-012, variation AA.

18

.010 [0.25] C A B

54

PIN 1 ID AREA

SEATING PLANE

.004 [0.1] C

SEE DETAIL A

DETAIL ATYPICAL

SCALE 2.800

www.ti.com

EXAMPLE BOARD LAYOUT

.0028 MAX[0.07]ALL AROUND

.0028 MIN[0.07]ALL AROUND

(.213)[5.4]

4X (.050 )[1.27]

7X (.061 )[1.55]

7X (.024)[0.6]

(.100 )[2.54]


4220728/A 01/2018

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METALSOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAILS

EXPOSEDMETAL

OPENINGSOLDER MASK METAL UNDER

SOLDER MASK

SOLDER MASKDEFINED

EXPOSEDMETAL

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE:8X

SYMM

1

45

8

SEEDETAILS

SYMM

www.ti.com

EXAMPLE STENCIL DESIGN

7X (.061 )[1.55]

7X (.024)[0.6]

4X (.050 )[1.27]

(.213)[5.4]

(.100 )[2.54]


4220728/A 01/2018

NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLEBASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

SYMM

SYMM

1

45

8

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