Tutorial Sheet FET Amplifier

Tutorial Sheet Part-3 (FET amplifier)

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1. Show that for a common source (CS) amplifier, the voltage gain

Dd

D

vRr

RA , input resistance

GiRR and output resistance

dOrR .

2. Show that for a common source amplifier with a resistance s

R connected

between source terminal and ground, the voltage gain

)1(SDd

D

vRRr

RA , the input resistance

GiRR and output resistance

SdORrR )1(

3. Show that for a common drain amplifier (CD), the voltage gain

)1(Sd

S

vRr

RA , the input resistance

GiRR and the output resistance

1

d

O

rR

4. Show that for a common gate amplifier with signal source resistance sig

R , the

voltage gain

sigs

sigS

Dd

D

v

RR

RRRr

RA

)1(

)1(, the input resistance

SDd

SDd

siRRr

RRrRR

)1( and the output resistance

dOrR

5. An n-channel JFET utilizes a self biased circuit. The pinch-off voltage

VVp

0.2 and mAIDSS

65.1 . It is desired to bias the circuit at

mAID

8.0 , using VVDD

24 . Assume Dd

Rr . Find (a) GS

V , (b) m

g , (c)S

R

and (d) D

R such that the voltage gain is at least 10, with S

R bypassed with a

very large capacitance s

C as shown in Fig. 1. Ans. (a) -0.62V, (b) 1.14mA/V,

(c) 770 , (d) 8.76 k.

Fig. 1


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6. Show that the trans-conductance m

g of a JFET is related to the drain

current DS

I by

DSDSS

p

mII

Vg

2

7. Starting with the definition of m

g and d

r , show that if two identical FETs are

connected in parallel, m

g is doubled and d

r is halved and remains

unchanged.

8. Find the voltage amplification S

O

vV

VA for the circuit shown in Fig. 2. Use

Miller’s theorem to consider the effect of f

R . The FET parameters are 30

and Krd

5 Ans. -18.7

Fig. 2

9. For the circuit shown in Fig. 3, find the expression of (a) the voltage gain

S

O

VV

VA , (b) the input resistance, (c) the output resistance

Ans. (a) SDd

D

vRRr

RA

)1(

)1(, (b)

)1(

Dd

si

RrRR

(c)Sdo

RrR )1(


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Fig.3

10. For a FET amplifier configuration as shown in Fig. 4, find the voltage gains

(a) s

o

vV

VA

1

1, (b)

s

o

vV

VA

2

2.

Ans. (a) SDd

D

vRRr

RA

)1(1

, (b) sDd

S

vRRr

RA

)1(2

Fig. 4

11. In the circuit shown in Fig.5, 02

V , krRdD

10 , kRS

1 and 19 .

If the output is taken from D2 terminal to ground, find (a) the voltage gain ,

(b) the output resistance. [ Hints. Use derivation of the problem 10]

Ans. (a) 3.17, (b) 6.67 k


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Fig. 5

12. The CS amplifier shown in Fig. 6 has the following parameters: kRD

12 ,

MRG

1 , 470S

R , VVDD

30 , s

C is arbitrarily large, mAIDSS

3 ,

VVp

4.2 , and Dd

Rr . Determine (a) the gate to source bias voltage GS

V ,

(b) the drain current D

I , (c) the quiescent voltage DS

V , (d) the small signal

voltage gain V

A

Ans: (a) -0.7V, (b) 1.5mA, (c) 11.25V, (d) -21.2 [ Hint : See prob.5 ]

Fig. 6


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13. The amplifier shown in Fig. 7 uses an n-channel FET having mAIDSS

1 ,

VVp

1 . If the quiescent drain-to-ground voltage is 10V, find 1

R .

Ans. 2kohms

Fig. 7

14. The FET shown in Fig. 8 has the following parameters : mAIDSS

6.5 ,

VVp

4 . (a) Find O

v when i

v =0 , (b) Find O

v when i

v =10V, (c) Find i

v

when 0

v =0V. { Note i

v and o

v are dc voltages ( not small signal voltages ) }

Ans: (a) 2V, (b) 11.4V, (c) -2.15V


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Fig. 8

15. If Die

Rh , die

rh , 1fe

h , and 1 for the circuit in Fig. 9, show

that (a) Sfem

Sfem

i

o

vRhg

Rhg

v

vA

1

1

1 (b)

Sfem

cSfem

i

o

vRhg

RRhg

v

vA

1

)(2

2. Use the

approximate model for the BJT.

Fig. 9

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Tutorial Sheet FET Amplifier