TUSB73x0 Board Design and Layout Guidelines (Rev. E) · PDF fileTUSB73x0 Board Design and Layout Guidelines User's Guide Literature Number: SLLU149E June 2011–Revised February 2016

TUSB73x0 Board Design and Layout Guidelines

User's Guide

Literature Number: SLLU149EJune 2011–Revised February 2016

2 SLLU149E–June 2011–Revised February 2016Submit Documentation Feedback

Copyright © 2011–2016, Texas Instruments Incorporated

Contents

Contents

1 Recommended Documents to Review .................................................................................... 72 Typical System Implementation ............................................................................................. 93 Power ............................................................................................................................... 11

3.1 Digital Supplies ............................................................................................................. 123.2 Analog Supplies ............................................................................................................ 123.3 Ground Terminal ........................................................................................................... 123.4 Capacitor Selection Recommendations ................................................................................. 133.5 USB VBUS .................................................................................................................. 13

4 Device Reset...................................................................................................................... 155 General High Speed Layout Guidelines ................................................................................. 17

5.1 Printed Circuit Board Stackup (FR-4 Example) ........................................................................ 175.2 Return Current and Plane References .................................................................................. 185.3 Split Planes – What to Avoid ............................................................................................. 185.4 Avoiding Crosstalk ......................................................................................................... 20

6 USB Connection................................................................................................................. 226.1 Internal Chip Trace Length Mismatch ................................................................................... 236.2 High-Speed Differential Routing.......................................................................................... 256.3 SuperSpeed Differential Routing ......................................................................................... 25

7 Package and Breakout ........................................................................................................ 287.1 Routing Between Pads .................................................................................................... 287.2 Pads.......................................................................................................................... 297.3 Solder Stencil ............................................................................................................... 30

8 PCI Express Connection ..................................................................................................... 328.1 Internal Chip Trace Length Mismatch ................................................................................... 328.2 Transmit and Receive Links .............................................................................................. 338.3 PCI-Express Reference Clock Input ..................................................................................... 358.4 PCI Express Reset ......................................................................................................... 358.5 PCI Express WAKE/CLKREQ ............................................................................................ 35

9 Wake from S3 .................................................................................................................... 3810 Device Input Clock ............................................................................................................. 4011 JTAG Interface ................................................................................................................... 4212 Differential Pair ESD Protection ........................................................................................... 4413 SuperSpeed Redriver .......................................................................................................... 4614 SMI Pin Implementation ...................................................................................................... 4815 Schematics........................................................................................................................ 50

15.1 TUSB7320 DEMO EVM REVB Schematics ............................................................................ 5115.2 TUSB7340 DEMO EVM REVB Schematics ............................................................................ 55

Revision History.......................................................................................................................... 60Revision History.......................................................................................................................... 60Revision History.......................................................................................................................... 60Revision History.......................................................................................................................... 60

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Contents

Revision History.......................................................................................................................... 60

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List of Figures

List of Figures2-1. Typical Application........................................................................................................... 93-1. TUSB7320 Power Consumption ......................................................................................... 113-2. TUSB7340 Power Consumption ......................................................................................... 113-3. Board Ground Connection ................................................................................................ 124-1. 1.1-V Regulator ............................................................................................................. 155-1. Nominal 4-Layer PCB Stackup ........................................................................................... 175-2. PCB Layer Configuration Suggestions .................................................................................. 185-3. Overlapping Analog and Digital Planes ................................................................................. 195-4. Incorrect Routing ........................................................................................................... 195-5. Proper Routing.............................................................................................................. 205-6. Ways to Avoid Crosstalk .................................................................................................. 206-1. USB3 and USB2 Signals from the USB Connector to the Device ................................................... 246-2. Length Matching............................................................................................................ 246-3. Differential Routing......................................................................................................... 267-1. Routing Between Pads .................................................................................................... 287-2. Pads.......................................................................................................................... 297-3. Solder Mask................................................................................................................. 307-4. Thermal Pad Stencil Thickness .......................................................................................... 308-1. PCIe TX and RX Signals from the Edge Connector to the Device .................................................. 328-2. Length Matching at the Device ........................................................................................... 338-3. Connection of WAKE#..................................................................................................... 3610-1. Dual Crystal/Oscillator Footprint.......................................................................................... 4012-1. TPD2EUSB30 ESD Protection ........................................................................................... 4413-1. Typical Application of SuperSpeed Redriver ........................................................................... 46

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List of Tables

List of Tables6-1. Length Mismatch ........................................................................................................... 238-1. Internal Chip Trace Length Mismatch ................................................................................... 328-2. Transmit and Receive Terminals......................................................................................... 34

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List of Tables

ABSTRACT:These guidelines are intended to provide developers with the resources needed to properly layout theTUSB7320/TUSB7340. They are intended as a follow-on document to the USB 2.0 Board Design andLayout Guidelines (SPRAAR7) which describes general PCB design and layout guidelines for the USB 2.0differential pair (DP/DM). A layout for the TUSB7340 will seamlessly accommodate the TUSB7320.

This document is focused on the layout and routing of the USB 3.0 SuperSpeed USB and PCI Express. Itis intended for developers familiar with high-speed PCB design and layout. Knowledge of the USB 3.0 andPCI Express specifications and protocols are required as well.

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Recommended Documents to Review

Chapter 1SLLU149E–June 2011–Revised February 2016


TI Customer DEMO EVM Reference Schematic and Layout files

PCB Design and Layout Guidelines for the USB 2.0 Differential Pair (SPRAAR7)

PCI Express Card Electromechanical 2.0 Specification:http://www.pcisig.com/specifications/pciexpress/base2

USB 3.0 Specification: http://www.usb.org/developers/docs

PCI Express Base Specification 2.1: http://www.pcisig.com/specifications/pciexpress



http://www.pcisig.com/specifications/pciexpress/base2

http://www.usb.org/developers/docs

http://www.pcisig.com/specifications/pciexpress

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PC

SS USB Device

Or

HS/FS/LS USB

Device

SS USB Device

Or

HS/FS/LS USB

Device

SS USB Device

Or

HS/FS/LS USB

Device

SS USB Device

Or

HS/FS/LS USB

Device

TUSB73x0

PCIe

To

USB 3.0

Host Controller



Typical System Implementation



The TUSB73x0 is an xHCI SuperSpeed USB host controller that interfaces to the PC host system via aPCIe x1 Gen 2 or PCIe Gen 1 interface, providing SuperSpeed, High-speed, Full-speed, or Low-speedconnections on the downstream USB ports. The TUSB7340 supports up to four downstream ports, andthe TUSB7320 supports up to two downstream ports.

Figure 2-1. Typical Application


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TUSB7340 Power Consumption

ASPM=1/P3_ENABLE=1

VCore V I/O

1.05 3.3

mA mW mA mW

Total

mW

4 SuperSpeed Devices Connected (ACTIVE) 880 924.00 115 379.50 1303.50

4 SuperSpeed Devices Connected (IDLE) 790 829.50 115 379.50 1209.00





1 SuperSpeed Device Connected (ACTIVE) 420 441.00 115 379.50 820.50

1 SuperSpeed Device Connected (IDLE) 376 394.80 115 379.50 774.30

PCI D0 - No Device Connected (IDLE) 168 176.40 42 138.60 315.00

PCI D3 - No Device Connected 63 66.15 4 13.20 79.35

Hibernate (ACPI S5) - No Device Connected 63 66.15 4 13.20 79.35

TUSB7320 Power Consumption

ASPM=1/P3_ENABLE=1

VCore V I/O

1.05 3.3

mA mW mA mW

Total

mW

2 SuperSpeed Devices Connected (ACTIVE) 507.00 532.35 112.00 369.60 901.95

2 SuperSpeed Devices Connected (IDLE) 445.00 467.25 112.00 369.60 836.85

1 SuperSpeed Device Connected (ACTIVE) 392.00 411.60 112.00 369.60 781.20

1 SuperSpeed Device Connected (IDLE) 331.00 347.55 112.00 369.60 717.15

PCI D0 - No Device Connected (IDLE) 156.00 163.80 40.00 132.00 295.80

PCI D3 - No Device Connected 56.00 58.80 3.50 11.55 70.35

Hibernate (ACPI S5) - No Device Connected 56.00 58.80 3.50 11.55 70.35



Power


Power

See Achieving_Lowest_Power_with_TUSB73X0.pdf for more information on the settings used to get theselow power numbers.

Figure 3-1. TUSB7320 Power Consumption

Figure 3-2. TUSB7340 Power Consumption


Digital Supplies www.ti.com



Power

3.1 Digital SuppliesBoth VDD1P1 and VDD3P3 supplies must have 0.1-µF bypass capacitors to VSS (ground) in order forproper operation. The recommendation is one capacitor for each power terminal. Place the capacitor asclose as possible to the terminal on the device and keep the traces as short and wide as possible to thevias that are used to connect to the power planes. Smaller value capacitors like 0.01 µF are alsorecommended on the digital supply terminals.

When placing and connecting all bypass capacitors, high-speed board design rules must be followed.

3.2 Analog SuppliesSince circuit noise on the analog power terminals must be minimized, an appropriate LC type filter isrecommended for each supply. For EMI concerns, appropriate ferrite beads should be used instead ofinductors in the LC filter circuit.

Analog power terminals should have a 0.1-µF bypass capacitor connected to VSS (ground) in order forproper operation. Place the capacitor as close as possible to the terminal on the device and keep thetraces as short and wide as possible to the vias that are used to connect to the power planes. Smallervalue capacitors like 0.01 µF are also recommended on the analog supply terminals.

Analog power terminals should have a 0.1-µF bypass capacitor connected to VSS (ground) in order forproper operation. Place the capacitor as close as possible to the terminal on the device and keep thetraces as short and wide as possible to the vias that are used to connect to the power planes. Smallervalue capacitors like 0.01 µF are also recommended on the analog supply terminals.

3.3 Ground TerminalThe thermal pad is also the board ground connection. Care should be taken to make sure any traces orvias under the device are far enough away from the thermal pad to prevent shorts. As shown in Figure 3-3, it is recommended to have at least 16 vias connecting the thermal pad to the board ground plane.

Figure 3-3. Board Ground Connection

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Power

3.4 Capacitor Selection RecommendationsWhen selecting bypass capacitors, X7R-type capacitors are recommended. The frequency versusimpedance curves, quality, stability, and cost of these capacitors make them a logical choice for mostcomputer systems.

The selection of bulk capacitors with low-ESR specifications is recommended to minimize low frequencypower supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolyticcapacitors. These capacitors typically have ESR specifications that are less than 0.01 Ω at 100 kHz. Also,several manufacturers sell “D” size surface mount specialty polymer solid aluminum electrolytic capacitorswith ESR specifications slightly higher than 0.01 Ω at 100 kHz. Both of these bulk capacitor optionssignificantly reduce low-frequency power supply noise and ripple.

3.5 USB VBUSThe TPS2560 is a dual channel power distribution switch that can handle high capacitive loads and shortcircuit conditions. The output current for each channel can be adjusted up to 2.8 A, making it ideal for SSUSB ports.

Each channel can be seamlessly and independently controlled by the TUSB73x0. The TPS2560 alsoprovides a seamless, per port fault indication. Refer to the datasheet for more information regarding thisdevice.

More information can be found at: http://focus.ti.com/docs/prod/folders/print/tps2560.html

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http://focus.ti.com/docs/prod/folders/print/tps2560.html

USB VBUS www.ti.com



Power

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EN 1P 1

SS1P1FB_1P T1VL

ED

3V

BOARD_1P1V

BOARD_3P3V

BOARD_3P3V

G RSTZ

D 5

LED reen 0805

D 5

LED G 0805

U 5

TPS74401RGW T

U 5

O UT1

NC

2

NC

3

NC

4

IN5

IN6

IN7

IN8

PG9

BIAS10

EN11

GN

D12

NC

13

NC

14

SS15

FB16

NC

17

O UT18O UT19O UT20

PA

D21

C 6910uFC 6910uF C 85

0.1uF

C 85

0.1uF

R 3433004025%

R 3433004025%

C 7022uFC 7022uF

R 32

4.7K

0402

5%

R 32

4.7K

0402

5%

R 31

10K

0402

5%

R 31

10K

0402

5%

C 71

0.01uF

C 71

0.01uF

R 331.87K

04021%

R 331.87K

04021%

C 72

N O PO P

R 354.99K

04021%

R 354.99K

04021%



Device Reset


Device Reset

There is no GRST# timing constraint with respect to the power supplies, other than it should not bedeasserted until the power supplies are stable.

However, extreme care must be taken if a passive reset is used, such as using the internal GRST# pull upor an external RC circuit, to ensure that the GRST# does not deassert until the 3.3-V and 1.1-V rails arewithin 10% of nominal. If the 3.3-V power ramps before the 1.1-V supply, and GRST# is deasserted, thedevice I/O is in an undefined state before the core logic is active. This allows the potential for the GRST#I/O cell to incorrectly configure as an output and drive the GRST# signal high until the core logic ispowered on and correctly configures the cell.

It is highly recommended that the GRST# input be connected to a power good output from a power supplyto ensure that it does not deassert until both the 3.3-V and 1.1-V power rails are within 10% of theirnominal value. The recommended sequence is to have the 3.3-V feed a 1.1-V regulator and then use the1.1-V Power Good signal to drive GRST# as outlined below.

Figure 4-1. 1.1-V Regulator


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Device Reset

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General High Speed Layout Guidelines



5.1 Printed Circuit Board Stackup (FR-4 Example)

Figure 5-1. Nominal 4-Layer PCB Stackup


Return Current and Plane References www.ti.com




PCB layer configuration suggestions for stackup symmetry and signal integrity.

Figure 5-2. PCB Layer Configuration Suggestions

5.2 Return Current and Plane ReferencesHigh frequency return signal/current is defined as the path that a signal follows back to its original sourceas all signals flow in a closed loop. Minimizing the loop area of the closed loop is beneficial for both EMI(Electro-Magnetic Interference) reduction and signal integrity.

The best way to minimize loop area is to always have a signal reference their nearest solid ground orpower plane. Obstructions to the return signal will cause signal integrity problems like reflections,crosstalk, undershoot and overshoot.

Signals can reference either power or ground planes, but ground is preferred. Without solid planereferences, single ended and differential impedance control is very hard to accomplish; crosstalk to othersignals may happen as the return signals will have no other path. This type of crosstalk is difficult totroubleshoot.

Symmetric pairing of solid planes in the layer stackup can significantly reduce warping of the PCB duringthe manufacturing process. Warping of the PCB is crucial to minimize on boards that utilize BGAcomponents.

5.3 Split Planes – What to AvoidNever route signals over splits in their perspective reference planes.

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www.ti.com Split Planes – What to Avoid




Figure 5-3. Overlapping Analog and Digital Planes

Figure 5-4. Incorrect Routing

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Avoiding Crosstalk www.ti.com




Figure 5-5. Proper Routing

5.4 Avoiding CrosstalkCrosstalk is defined as interference from one trace to another by either or both inductive and capacitivecoupling. Best ways to avoid crosstalk are:• Provide stable reference planes for all high speed signals (as noted in previous sections).• Use the 3W rule (3 times the width of trace for separation) where applicable on all signals, but

absolutely use on clock signals.• Use ground traces/guards around either “victim” or “aggressor” signals prone to crosstalk.• When constrained and space limited on areas of the PCB to route parallel buses, series and/or end

termination resistors can be used to route traces closer than what is normally recommended. However,calculations and simulations must be done to validate the use of series or end termination resistors toeliminate crosstalk.

Figure 5-6. Ways to Avoid Crosstalk

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USB Connection


USB Connection

There are three sets of differential pairs associated with each SuperSpeed USB port. One set for High-Speed and two sets for SuperSpeed.

WARNINGDo not connect the USB2 and SS USB connections on one USB3connector to two different host chips. For instance, do not use theSS USB TX/RX from the TUSB73x0 and the USB2 DP/DM fromanother USB2 host.Doing this may cause USB compliance failures and xHCI driverissues.


www.ti.com Internal Chip Trace Length Mismatch



USB Connection

6.1 Internal Chip Trace Length MismatchRouting of the differential pair on the PCB will need to account for length mismatch in the package. This isdue to offset pin and the associated bond wire mismatch.

Table 6-1. Length Mismatch

NetName Bondwire Length (mil) Difference (mil)USB_SSTXN_DN1 96

20USB_SSTXP_DN1 116USB_SSRXN_DN1 91

20USB_SSRXP_DN1 111

USB_DM_DN1 8322

USB_DP_DN1 105USB_SSTXP_DN2 104

31USB_SSTXN_DN2 73USB_SSRXP_DN2 67

27USB_SSRXN_DN2 94

USB_DM_DN2 12734

USB_DP_DN2 93USB_SSTXP_DN3 73


31USB_SSRXN_DN3 113

USB_DP_DN3 10434

USB_DM_DN3 138USB_SSTXP_DN4 58


22USB_SSRXN_DN4 80

USB_DM_DN4 8626

USB_DP_DN4 60

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Internal Chip Trace Length Mismatch www.ti.com



USB Connection

Figure 6-1. USB3 and USB2 Signals from the USB Connector to the Device

Figure 6-2 shows length matching at the device. Length matching must be done at the device side, not atthe connector.

Figure 6-2. Length Matching

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www.ti.com High-Speed Differential Routing



USB Connection

6.2 High-Speed Differential RoutingThe high-speed differential pair (USB_DM and USB_DP) is connected to a type A USB connecter. Thedifferential pair traces should be routed with 90 Ω ±15% differential impedance. The high-speed signal pairshould be trace length matched. Max trace length mismatch between high speed USB signal pairs shouldbe no greater than 150 mils. Keep total trace length to a minimum, if routing longer than eight inchescontact TI to address signal integrity concerns.

Route differential traces first. Route the differential pairs on the top or bottom layers with the minimumamount of vias possible. No termination or coupling caps are required. If a common mode choke isrequired then place the choke as close as possible to the USB connector signal pins. Likewise ESDclamps should also be placed as close as possible to the USB connector signal pins (closer than thechoke).

For more detailed information, you may also see the USB 2.0 Board Design and Layout Guidelines(SPRAAR7) which describes general PCB design and layout guidelines for the USB 2.0 differential pair(DP/DM).

6.3 SuperSpeed Differential RoutingSuperSpeed consists of two differential routing pairs, a transmit pair (USB_SSTXM and USB_SSTXP) anda receive pair (USB_SSRXM and USB_SSRXP). Each differential pair traces should be routed with 90 Ω±15% differential impedance. The high-speed signal pair should be trace length matched. Maximum tracelength mismatch between SuperSpeed USB signal pairs should be no greater than 5 mils. The total lengthfor each differential pair can be no longer than eight inches, this is based on the SS USB compliancechannel spec, and should be avoided if at all possible. TI recommends that the SS diff pairs be as shortas possible.

The transmit differential pair does not have to be the same length as the receive differential pair. Keeptotal trace length to a minimum. Route differential traces first. Route the differential pairs on the top orbottom layers with the minimum amount of vias possible. The transmitter differential pair requires 0.1-µFcoupling capacitors for proper operation. The package/case size of these capacitors should be no biggerthan 0402. C-packs are not allowed. The capacitors should be placed symmetrically as close as possibleto the USB connector signal pins.

If a common mode choke is required, then place the choke as close as possible to the USB connectorsignal pins (closer than the transmitter capacitors). Likewise, ESD clamps should also be placed as closeas possible to the USB connector signal pins (closer than the choke and transmitter capacitors).

It is permissible to swap the plus and minus on either or both of the SuperSpeed differential pairs. Thismay be necessary to prevent the differential traces from crossing over one another. However it is notpermissible to swap the transmitter differential pair with the receive differential pair.

It is recommended to use a 2010 pad for the inside pins provided no pad is used for adjacent pins.Instead use a pad on one of the inside pins then for the next pad route the trace between the outer pins toa via.

There is enough space to route a 3.78-mil trace between the outside pads while leaving 5-mil spacingbetween the trace and pad, it is then possible to increase the trace width to 4 mils after the breakout. InFigure 6-3 the red pads are USB_SS_RXP/USB_SS_RXN and the blue pads areUSB_SS_TXP/USB_SS_TXN.

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SuperSpeed Differential Routing www.ti.com



USB Connection

Figure 6-3. Differential Routing

In order to minimize cross-talk on the SS USB differential signal pair, it is recommended that the spacingbetween the TX and RX signal pairs for each interface be five times the width of the trace (5W rule). Forinstance, if the SS USB TX differential pair trace width is 5 mils, then there should be 25 mils of spacebetween the TX and RX differential pairs.

If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should bemaximized as much as possible and ground-fill should be placed between the two. In this case, it is betterto route each differential pair on opposite sides of the board with a ground plane between them.

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USB Connection

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Package and Breakout



Package DrawingSee Mechanical Data for RKM package (MPQF258A).

7.1 Routing Between PadsFigure 7-1 illustrates a 0.10-mm trace width and 0.125-mm space, with a 20-mil via pad with 0.10-mm gapto nearest metal.

Figure 7-1. Routing Between Pads


http://www.ti.com/lit/pdf/MPQF258A

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7.2 PadsIt is recommended that a “Non Solder Mask Defined Pad” (NSMD) be used. This type of stencil will havean area greater than the actual pad size.

Figure 7-2. Pads

Land Pattern RecommendationSee Land Pattern for RKM package (LPPD235).

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http://www.ti.com/lit/pdf/LPPD235

Solder Stencil www.ti.com




7.3 Solder StencilThe solder mask is defined as a 1:1 ratio.

Figure 7-3. Solder Mask

For the thermal pad, a 0.10-mm stencil thickness is recommended. The actual package exposed pad is5.5 mm x 5.5 mm.

Figure 7-4. Thermal Pad Stencil Thickness

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PCI Express Connection



8.1 Internal Chip Trace Length MismatchRouting of the differential pair on the PCB will need to account for length mismatch in the package. This isdue to offset pin and the associated bond wire mismatch.

Table 8-1. Internal Chip Trace Length Mismatch

NetName Bondwire Length (mil) Difference (mil)PCIE_TXN 118

28PCIE_TXP 89PCIE_RXN 112

27PCIE_RXP 85

PCIE_REFCLKN 8719

PCIE_REFCLKP 106

Figure 8-1. PCIe TX and RX Signals from the Edge Connector to the Device


www.ti.com Transmit and Receive Links




Length matching must be done at the device side, not at the connector.

Figure 8-2. Length Matching at the Device

8.2 Transmit and Receive LinksThe TUSB73x0 has an x1 PCI Express interface that runs at 5-Gb/s and is fully compliant to the PCIExpress Base Specification, Revision 2.0.

The TUSB73x0 TX and RX terminals attach to the upstream PCI Express device over a 5-Gb/s high-speed differential transmit and receive PCI Express x1 Link. The connection details are provided in thefollowing table.

It is permissible to swap the plus and minus on either or both of the PCIe differential pairs. This may benecessary to prevent the differential traces from crossing over one another. However it is not permissibleto swap the transmitter differential pair with the receive differential pair.

In order to minimize cross-talk on the PCIe differential signal pair, it is recommended that the spacingbetween the TX and RX signal pairs for each interface be five times the width of the trace (5W rule). Forinstance, if the PCIe TX differential pair trace width is 5 mils, then there should be 25 mils of spacebetween the TX and RX differential pairs.

If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should bemaximized as much as possible and ground-fill should be placed between the two. In this case, it is betterto route each differential pair on opposite sides of the board with a ground plane between them.

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Transmit and Receive Links www.ti.com




Table 8-2. Transmit and Receive Terminals

TUSB73x0 Terminal Name Upstream PCIe DeviceTerminal Name Description

TXP RXP TUSB73x0 transmit positive differential terminal connects to theupstream device receive positive differential terminal.

TXP RXN TUSB73x0 transmit negative differential terminal connects to theupstream device receive negative differential terminal.

RXP TXP TUSB73x0 receive positive differential terminal connects to theupstream device transmit positive differential terminal.

RXN TXP TUSB73x0 receive negative differential terminal connects to theupstream device transmit negative differential terminal.

The TUSB73x0 TXP and TXN terminals comprise a low-voltage, 100-Ω differential signal pair. The RXPand RXN terminals for the TUSB73x0 receive a low-voltage, 100-Ω differential signal pair. The TUSB73x0has integrated 50-Ω termination resistors to VSS on both the RXP and RXN terminals eliminating the needfor external components.

The TX lane of the differential signal pair must be ac-coupled. The recommended value for the seriescapacitor is 0.1 μF. To minimize stray capacitance associated with the series capacitor circuit board solderpads, 0402 sized capacitors are recommended.

When routing a 5-Gb/s low-voltage, 100-Ω differential signal pair, the following circuit board designguidelines must be considered:1. The PCI-Express drivers and receivers are designed to operate with adequate bit error rate margins

over a 20-inch maximum length signal pair routed through FR4 circuit board material.2. Each differential signal pair must have a 100-Ω differential impedance, with each single-ended lane

measuring in the range of 50-Ω to 55-Ω impedance to ground.3. The differential signal trace lengths associated with a PCI Express high-speed link must be length

matched to minimize signal jitter. This length matching requirement applies only to the P and N signalswithin a differential pair. The transmitter differential pair does not need to be length matched to thereceiver differential pair. The absolute maximum trace length difference between the TXP signal andTXN signal must be less than 5 mils. This also applies to the RXP and RXN signal pair.

4. If a differential signal pair is broken into segments by vias, series capacitors, or connectors, the lengthof the positive signal trace must be length matched to the negative signal trace for each segment.Trace length differences over all segments are additive and must be less than 5 mils.

5. The location of the series capacitors is critical. For add-in cards, the series capacitors are locatedbetween the TXP/TXN terminals and the PCI-Express connector. In addition, the capacitors are placednear the PCI Express connector. This translates to two capacitors on the motherboard for thedownstream link and two capacitors on the add-in card for the upstream link. If both the upstreamdevice and the downstream device reside on the same circuit board, the capacitors are located nearthe TXP/TXN terminals for each link.

6. The number of vias must be minimized. Each signal trace via reduces the maximum trace length byapproximately 2 inches. For example: if 6 vias are needed, the maximum trace length is 8 inches.

7. When routing a differential signal pair, 45° angles are preferred over 90° angles. Signal trace lengthmatching is easier with 45° angles and overall signal trace length is reduced.

8. The differential signal pairs must not be routed over gaps in the power planes or ground planes. Thiscauses impedance mismatches.

9. If vias are used to change from one signal layer to another signal layer, it is important to maintain thesame 50-Ω impedance reference to the ground plane. Changing reference planes causes signal traceimpedance mismatches. If changing reference planes cannot be prevented, bypass capacitorsconnecting the two reference planes next to the signal trace vias will help reduce the impedancemismatch.

10. If possible, the differential signal pairs must be routed on the top and bottom layers of a circuit board.Signal propagation speeds are faster on external signal layers.

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www.ti.com PCI-Express Reference Clock Input




8.3 PCI-Express Reference Clock InputThe TUSB73x0 requires an external reference clock for the PCI-Express interface. The PCI Express BaseSpecification and PCI Express Card Electromechanical Specification provide information concerning therequirements for this reference clock. The TUSB73x0 is designed to meet all stated specifications whenthe reference clock input is within all PCI Express operating parameters. This includes both standard clockoscillator sources or spread spectrum clock oscillator sources.

The TUSB73x0 supports a 100-MHz common differential reference clock. The PCI Express clock istypically a system-wide, 100-MHz differential reference clock. A single clock source with multipledifferential clock outputs is connected to all PCI Express devices in the system. The differential connectionbetween the clock source and each PCI Express device is point-to-point. This system implementation isreferred to as a common clock design.

The TUSB73x0 is optimized for this type of system clock design. The REFCLK+ and REFCLK- terminalsprovide differential reference clock inputs to the TUSB73x0. The circuit board routing rules associated withthe 100-MHz differential reference clock are the same as the 5-Gb/s TX and RX link routing rules itemizedin Section 8.2. The only difference is that the differential reference clock does not require seriescapacitors. The requirement is a DC connection from the clock driver output to the TUSB73x0 receiverinput. Electrical specifications for these differential inputs are included in the TUSB73x0 Data Manual.

Terminating the differential clock signal is circuit board design specific. But, the TUSB73x0 design has nointernal 50-Ω to ground termination resistors. Both REFCLK inputs, at approximately 20 kΩ to ground, arehigh-impedance inputs.

8.4 PCI Express ResetThe TUSB73x0 PCI Express reset (PERST) terminal connects to the upstream PCI Express device’sPERST output. The PERST input cell has hysteresis and is operational during both the main power stateand VAUX power state. No external components are required.

Please reference the TUSB73x0 Data Manual and PCI-Express Card Electromechanical Specification tofully understand the PERST electrical requirements and timing requirements associated with power-upand power-down sequencing. Also, the Data Manual identifies all configuration and memory-mappedregister bits that are reset by PERST.

8.5 PCI Express WAKE/CLKREQ

Leakage Current on Pins WAKE# and CLKREQ#WAKE# and CLKREQ# pins are high impedance (~4.5 MΩ) pins and a positive constant current of 1 µAflowing into the pins could develop 4.5 V at the pin. When the VDD33 is at 0 V the pin can be overstressedand cause permanent leakage.

Care should be taken on pins WAKE# and CLKREQ# when VDD33 is at 0 V. If a voltage over 4.6 V isapplied to these pins when VDD33 = 0, the pins could be degraded causing a leakage current. 4.6-V isabove the maximum rated voltage (VDD33 + 0.5) and above the maximum operating voltage of 3.3 V.

This stress condition does not occur in normal operation mode where the maximum voltage that could beseen at WAKE# is 3.6 V.

RecommendationsCare should be taken during 'Bed of Nail' or 'In Circuit Test' so that a constant current source is not usedto test continuity on the WAKE# pin. A negative current test is recommended as there is a ground diodeon the device that will clamp the voltage at the WAKE# and CLKREQ# pins.

Avoid using a handheld multimeter to test continuity of the WAKE# and CLKREQ# pins. Many multimetersuse a constant current source that could be as high as 1 mA which could expose WAKE# and CLKREQ#pins to the high voltage.

On running projects that are already in production, if the stress voltage on the WAKE# pin of TUSB7320< 4.6 V when VDD33 is zero, there is no risk on the shipping platform.

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G

D S

10KR

VDD33

To WAKE# terminal on TUSB73X0To PCIE WAKE#

Power Good (1)

Q2 (2)

C10.001uF

PCI Express WAKE/CLKREQ www.ti.com




On new projects in design or projects that are not in mass production yet, TI suggests ODMs adding aFET (make sure parasitic diode is reversed bias) and 10-kΩ pull up resistor on WAKE# to preventoverstress (see Figure 8-3). Also, due to an erratum on TUSB73x0, a 0.001-µF capacitor to ground isrequired on the WAKE# and CLKREQ# signals. The rise time must be greater than 450 ns. See the errata(SLLZ067) for a more detailed explanation.

(1) Power Good is a 3.3-V signal asserted high when VDD33 is at its valid operating voltage (see RecommendedOperating Conditions table in the Data Manual, SLLSE76).

(2) N-Channel MOSFET 2N7002 or 2N7002K are suitable devices for use in the circuit.

Figure 8-3. Connection of WAKE#

In all projects going forward, do not use constant current during 'In Circuit Test'. If that is not possible, omitWAKE# and CLKREQ# pins from the 'ICT'.

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http://www.ti.com/lit/pdf/SLLZ067

http://www.ti.com/lit/pdf/SLLSE76

www.ti.com PCI Express WAKE/CLKREQ




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Wake from S3


Wake from S3

WAKE is an open-drain output from the TUSB73x0 that is driven low to re-activate the PCI Express linkhierarchy’s main power rails and reference clocks. This PCI Express side-band signal is connected to theWAKE input on the upstream PCI Express device. WAKE is operational during both the main power stateand VAUX power state.

Since WAKE is an open-drain output, a system side pullup resistor is required to prevent the signal fromfloating. The drive capability of this open-drain output is 4 mA. Therefore, the value of the selected pullupresistor must be large enough to assure a logic low signal level at the receiver. A robust system designwill select a pullup resistor value that de-rates the output driver current capability by a minimum of 50%. At3.3 V with a de-rated drive current equal to 2 mA, the minimum resistor value is 1.65 kΩ. Larger resistorvalues are recommended to reduce the current drain on the VAUX supply.

Hardware requirements for supporting wake from S3:1. All power rails on the TUSB73x0 must remain powered.2. AUX_DET terminal must be pulled high.3. WAKE# terminal must be connected to PCIe bus wake signal.4. A 0.001-µF capacitor should be placed on WAKE# terminal to ground.5. VBUS must remain powered such that power can be applied to attached keyboard/mouse during S3.

The conditions for WAKE# to assert are:1. The PME enable bit must be set (PME status bit must be cleared).2. The PCIe link must be in D3.3. PERST# must be asserted.4. The TUSB73x0 has to receive the RESUME command from the attached USB peripheral.


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Wake from S3

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Device Input Clock


Device Input Clock

The TUSB73x0 supports an external oscillator source or a crystal unit. If a clock is provided to XI insteadof a crystal, it must be a 1.8-V clock source, XO should be left open and VSSOSC is connected to thePCB ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below.

In Figure 10-1, XY1 is a dual crystal/oscillator footprint. To use a crystal only populate R13, C16, and C18.To use an oscillator only populate C17, R74, R75, and R76.

Figure 10-1. Dual Crystal/Oscillator Footprint

Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as shortas possible and away from any switching leads. It is also recommended to minimize the capacitancebetween XI and XO. This can be accomplished by connecting the VSSOSC lead to the two externalcapacitors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not beconnected to PCB ground if using a crystal.

Load capacitance (Cload) of the crystal varying with the crystal vendors is the total capacitance value ofthe entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 andCL2. The trace length between the decoupling capacitors and the corresponding power pins on theTUSB73x0 needs to be minimized. It is also recommended that the trace length from the capacitor pad tothe power or ground plane be minimized.

See the TUSB73x0 Data Sheet for input clock parameters.


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Device Input Clock

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JTAG Interface


JTAG Interface

The TUSB73x0 supports JTAG (IEEE 1149.1 and 1149.6) for board level test. Contact TI for BSDL files.

The JTAG TRST signal must be pulled to ground for proper device operation.


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JTAG Interface

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Differential Pair ESD Protection



If more protection is required then the TPD2EUSB30 can be used, the device meets or exceedsIEC61000-4-2 (Level 4) requirements. This device can be used on any of the differential pairs and can beplaced on a single layer and causes no signal distortion due to layout mismatch. Place the device as closeas possible to the signal pins of the connector. Refer to the datasheet for more information regarding thisdevice.

More information can be found at: http://focus.ti.com/docs/prod/folders/print/tpd2eusb30.html

Figure 12-1. TPD2EUSB30 ESD Protection


http://focus.ti.com/docs/prod/folders/print/tpd2eusb30.html

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SuperSpeed Redriver


SuperSpeed Redriver

The SN65LVPE502 USB SuperSpeed redriver (does not support the High Speed signals) can be used ifthe SuperSpeed differential pairs must be driven longer than eight inches, through connectors, or overless than desirable cables. This device makes “bad signals good” again. Refer to the datasheet for moreinformation regarding this device.

More information can be found at: http://focus.ti.com/docs/prod/folders/print/sn65lvpe502.html

Figure 13-1. Typical Application of SuperSpeed Redriver


http://focus.ti.com/docs/prod/folders/print/sn65lvpe502.html

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SuperSpeed Redriver

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SMI Pin Implementation



The SMI pin is actively driven by the TUSB73x0. It should not have a pull up resistor. To guarantee thatno interrupts are generated when power is removed from the TUSB73x0, a pull down can be used. This isnot required as long as the TUSB73x0 has a ground connection.


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Schematics


Schematics

The following pages contain schematics for the TUSB7320 and TUSB7340.


EPROM

I2C

DP/DM

(U1)TUSB7320

RX/TX USB3TYPEA

PCIECONNECTOR

DOWNSTREAMPORT1

DOWNSTREAMPORT2USB3

TYPEA

DP/DM

RX/TX

RX/TX

VIA AND TRACE REQUIREMENTS:- MIN VIA PAD SIZE 20mils- MIN spacing between trace and pad is 5mils- MIN spacing between VIA and pad is 5mils- MIN width of trace is 4mils

IMPEDANCE REQUIREMENTS:- USB_DP/M must be 90-ohm differential (+/-15%)- USB_SSTXP/N must be 90-ohms differential (+/-15%)- USB_SSRXP/N must be 90-ohms differential (+/-15%)- PCIE_TXP/N must be 100-ohms differential (+/-10%)- PCIE_RXP/N must be 100-ohms differential (+/-10%)- PCIE_REFCLKP/N must be 100-ohms differential (+/-10%)

LENGTH MATCHING REQUIREMENTS:- USB_DP/M within 25mils.- USB_SSTXP/N within 5mils- USB_SSRXP/N within 5mils- PCIE_TXP/N within 5mils- PCIE_RXP/N within 5mils- PCIE_REFCLKP/N within 25mils.

Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7320 DEMO REVB_48

Friday, May 09, 2014

B

1 4Sheet of

SIZE

SCALE: NONE

DWG NO:



B

1 4Sheet of

SIZE

SCALE: NONE

DWG NO:



B

1 4

www.ti.com TUSB7320 DEMO EVM REVB Schematics



Schematics

15.1 TUSB7320 DEMO EVM REVB Schematics

http://www.ti.com


PLACE CLOSE TO U1

AU

X_

DE

T

SDA

R1EXT

R1EXTRTN

VSS_OSC

XO

XI

FREQSEL

SCL

GPIO0GPIO1GPIO2GPIO3

VDDA3P3VBOARD_1P1V BOARD_3P3VBOARD_3P3V

BOARD_3P3V

BOARD_3P3V

USB_DP_DN2 pg3USB_DM_DN2 pg3

USB_SSTXP_DN2 pg3USB_SSTXN_DN2 pg3

USB_SSRXP_DN2 pg3USB_SSRXN_DN2 pg3

OVERCUR2Z pg3PWRON2Z pg3

USB_DM_DN1 pg3USB_DP_DN1 pg3

USB_SSRXN_DN1 pg3USB_SSRXP_DN1 pg3

USB_SSTXN_DN1 pg3USB_SSTXP_DN1 pg3

PWRON1Z pg3OVERCUR1Z pg3

PCIE_REFCLKNpg3PCIE_REFCLKPpg3

PCIE_RXNpg3PCIE_RXPpg3

PCIE_TXNpg3PCIE_TXPpg3

PERSTZpg3

WAKEZpg3

GRSTZpg4

1

Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7320


C

2 4Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7320


C

2 4Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7320


C

2 4

J22

HDR2X1 M .1

12

R3NOPOP

04025%

C2

18pF

Y1

ECS-48MHZ

U2

24LC01_NF

A01

A12

A23

GND4

SDA5SCL6WP7VCC8

R114.7K

04025%

R1NOPOP

04025%

R39

0

R210K

04025%

R38

0

C3

18pF

R12 1M

R10 9.09K 1%

R4NOPOP

04025%

TUSB7320

TUSB7320_REVA

U1

CLKREQ#B36

FREQSELB14

GPIO0A49

GPIO1B46

GPIO2B47

GPIO3B48

GRST#A15

JTAG_RST#B32

JTAG_TCKA32

JTAG_TDIA35

JTAG_TDOB31

JTAG_TMSB30

PCIE_REFCLKNB41

PCIE_REFCLKPA45

PCIE_RXNA42

PCIE_RXPB39

PCIE_TXNA41

PCIE_TXPB38

PERST#A40

SCLB2

SDAA2

SMIB3

WAKE#B35

OVERCUR1#A36

OVERCUR2#A37

NC18B43

NC26B45

PWRON1#B33

PWRON2#B34

NC17A46

NC25A48

R1EXTA24

R1EXTRTNB23

USB_DM_DN1B18

USB_DM_DN2A13

NC11A27

NC19A5

USB_DP_DN1A20

USB_DP_DN2B12

NC12B25

NC20B5

USB_SSRXN_DN1B16

USB_SSRXP_DN2B9

NC13A29

NC21A7

USB_SSRXP_DN1A18

USB_SSRXN_DN2A10

NC14B27

NC22B6

USB_SSTXN_DN1B15

USB_SSTXN_DN2B10

NC15A30

NC23A8

USB_SSTXP_DN1A17

USB_SSTXP_DN2A11

NC16B28

NC24B7

VSS_OSCB21

XIA23

XOA22

AU

X_D

ET

A52

VD

DA

_3P

3A

25

VD

D11

A1

VD

D11

A12

VD

D11

A16

VD

D11

A28

VD

D11

A31

VD

D11

A33

VD

D11

A38

VD

D11

A4

NC

6A

43

VD

D11

A50

VD

D11

A6

VD

D11

A9

VD

D11

B1

VD

D11

B17

VD

D11

B19

VD

D11

B24

VD

D11

B37

VD

D11

B40

VD

D11

B42

VD

D11

B44

NC

29

B8

VD

D33

A3

VD

D33

A34

VD

D33

A39

VD

D33

A47

VD

D33

A51

VD

DA

_3P

3A

19

VD

DA

_3P

3A

21

VD

DA

_3P

3A

44

VD

DA

_3P

3B

11

VD

DA

_3P

3B

22

NC

28

B26

NC

27

B4

NC

1A

14

NC

2A

26

NC

3B

13

NC

4B

29

VS

SB

20

VS

SA

53

NC

7C

1

NC

8C

2

NC

9C

3

NC

10

C4

C1

0.1uF

BOARD_1P1V

C32

0.1uF

C17

0.1uF

C36

0.01uF

C12

0.01uF

C31

0.1uF

C18

0.01uF

C34

0.1uF

C20

0.1uF

C21

0.01uF

C23

0.1uF

C16

0.1uF

C37

0.1uF

C13

0.1uF

C30

0.01uF

C33

0.01uF

C24

22uF

C19

0.1uF

C35

0.1uF

C14

0.1uF

C22

0.1uF

C15

0.01uF


BOARD_3P3V

R7NOPOP

04025%

R6NOPOP

04025%

R8NOPOP

04025%

R5NOPOP

04025%

VDDA3P3VBOARD_3P3V

C6

0.1uF

C28

0.1uF

FB1

220 @ 100MHZ

C25

0.1uF

C9

0.1uF

C7

0.01uF

C11

0.1uF

C29

0.1uF

C5

0.01uF

C26

0.1uF

C10

0.01uFC422uF

C8

0.1uF

C27

0.1uF

POPULATE R2 FOR WAKE SUPPORT. JUMPER J22 FOR NO WAKE SUPPORT

POPULATE PULLDOWN IF I2C EEPROM

NOT USED AND DO NOT POPULATE

PULLUP.

TUSB7320 DEMO EVM REVB Schematics www.ti.com



Schematics

http://www.ti.com


DOWNSTREAMPORT1

DOWNSTREAMPORT2

JUMPER BETWEEN 1 AND2 FOR NORMALOPERATION.

JUMPER BETWEEN 2 AND3 FOR WAKE TESTING.

PCIE CEM SPEC MAX VALUES:PCIE_3P3V: 3 AMPS.VAUX: 375mA

ILIM1

DS1_VBUS

DS2_VBUS

LE

DD

S1

LE

DD

S3

CAP_US_TXNCAP_US_TXP

PCIE_PRSNTZ

PCIE_TDITDO

WAKEZ_R

USB_SSRXN_DN1

IND_USB_DP_DN1

DS1_VBUS

USB_SSRXP_DN1

IND_USB_DM_DN1

CAPDSTXP1

CAPDSTXN1

DS_SHLD

IND_DS_TXP1

IND_DS_TXN1

IND_DS_TXN2CAPDSTXP2

CAPDSTXN2

IND_USB_DP_DN2

DS2_VBUS

USB_SSRXN_DN2USB_SSRXP_DN2

IND_USB_DM_DN2

IND_DS_TXP2

DS_SHLDDS_SHLD

BOARD_5V

BOARD_3P3V

PCIE_3P3VPCIE_3P3V BOARD_12VVAUX

BOARD_3P3V

PWRON2Zpg2

PWRON1Zpg2

PCIE_RXP pg2PCIE_RXN pg2

PCIE_REFCLKN pg2PCIE_REFCLKP pg2

WAKEZpg2 PERSTZ pg2

PCIE_TXN pg2

PCIE_TXP pg2

OVERCUR1Z pg2

OVERCUR2Z pg2

USB_DM_DN1 pg2

USB_SSRXN_DN1 pg2

USB_SSRXP_DN1 pg2

USB_DP_DN1 pg2

USB_SSTXP_DN1 pg2

USB_SSTXN_DN1 pg2

USB_SSTXP_DN2 pg2

USB_SSTXN_DN2 pg2

USB_DM_DN2 pg2

USB_DP_DN2 pg2

USB_SSRXN_DN2 pg2

USB_SSRXP_DN2 pg2

Sheet of

SIZE

SCALE: NONE

DWG NO:

USB3 AND PCIE CONNECTORS


C

3 4Sheet of

SIZE

SCALE: NONE

DWG NO:



C

3 4Sheet of

SIZE

SCALE: NONE

DWG NO:



C

3 4

R17

1M

0402

R13

10K

0402

5%

Side BComponent Side

Side ASolder Side

Key

P1

PCI Express x1 Edge Connector

12V1B1

12V2B2

12V5B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

3.3VB8

J_TRST#B9

3.3VauxB10

WAKE#B11

RSVD2B12

GND3B13

PETp0B14

PETn0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

12V3A2

12V4A3

GND9A4

J_TCKA5

J_TDIA6

J_TDOA7

J_TMSA8

3.3V1A9

3.3V2A10

PERST#A11

GND8A12

REFCLK+A13

REFCLK-A14

GND7A15

PERp0A16

PERn0A17

GND6A18

J40

HDR1x3

123

R18

NOPOP

C62

NOPOP

R14

10K

0402

5%

U26

TPD2EUSB30_NF

D+1

D-2

GND3

C79

1000pF

C48 0.1uF

R1533004025%

+ C80NOPOP

+ C44150uF

L4

TDK_TCE_1210

1

2 3

4

R50 0

C41

0.1uF

C47 0.1uF

C43

0.1uF

R20

NOPOPD1

LED Green 0805

+ C46150uF

C64

22uF

U3

TPS2560DRC

GND1

IN2

IN3

EN14

EN25

FAULT2Z6

ILIM7

OUT28

OUT19

FAULT1Z10

PAD11

C67 0.1uF

C45

0.1uF

C63

NOPOP

R19

30.9K

0402

1%

C42

0.001uF

C68 0.1uF

L7

TDK_TCE_1210

1

2 3

4

R1633004025%

J4

USB3_TYPEA_CONNECTER

VBUS1

DM2

DP3

GND4

SSRXN5

SSRXP6

GND7

SSTXN8

SSTXP9

SHIELD010

SHIELD111

C49

0.1uF

C50

0.001uF

C40 0.1uF

D2

LED Green 0805L5

TDK_TCE_1210

1

2 3

4

MH2

PLATED_MH

1

R21

1M

0402

C39 0.1uF

MH1

PLATED_MH

1

C38

0.1uF

U27

TPD2EUSB30_NF

D+1

D-2

GND3

L2

TDK_TCE_1210

1

2 3

4J1


VBUS1

DM2

DP3

GND4

SSRXN5

SSRXP6

GND7

SSTXN8

SSTXP9

SHIELD010

SHIELD111




Schematics

http://www.ti.com


1.1V REGULATOR

5V VBUS OPTIONS

NOTE: USE LOW ESR CAP


OPTION 1: 5V REGULATOR OPTION 2: 5V FROM IDE CONNECTOR

NOTE: ONLY POPULATE ONE OPTION

R33 R35 OUTPUT1.13K 4.53K 1.0V1.37K 4.42K 1.05V1.87K 4.99K 1.1V (DEFAULT)2.49K 4.99K 1.2V

EN1P1

SS1P1FB_1PT1V

VSENSE

BOOT PH

LE

D3V

BOARD_1P1V

BOARD_3P3V

BOARD_3P3V

REG_5V BOARD_12VIDE_5V

IDE_5V

REG_5V

BOARD_5V

GRSTZ pg2

Sheet of

SIZE

SCALE: NONE

DWG NO:

POWER


B

4 4Sheet of

SIZE

SCALE: NONE

DWG NO:

POWER


B

4 4Sheet of

SIZE

SCALE: NONE

DWG NO:

POWER


B

4 4

J27

NOPOP

1 2

L1

15uH_NF

R37

3.16K_NF

1%

C78

0.01uF_NF

D5

LED Green 0805

+5VGND0GND1+12V

J5

IDE_PWR_CONN

4321

+ C73330uF_NF

R36

10K_NF

1%

U5

TPS74401RGWT

OUT1

NC

2

NC

3

NC

4

IN5

IN6

IN7

IN8

PG9

BIAS10

EN11

GN

D12

NC

13

NC

14

SS15

FB16

NC

17

OUT18OUT19OUT20

PA

D21

C6910uF

R3433004025%

C85

0.1uF

C7022uF

D6

MBRS540T3_NF

R32

4.7K

0402

5%

C75

0.01uF_NF

C74

0.01uF_NF

R31

10K

0402

5%

C71

0.01uF

R331.87K

04021%

C72

NOPOP

J26

HDR2X1 M .1

1 2

R354.99K

04021%

C7622uF

C7722uF_NF

U6

TPS5450_NF

BOOT1

NC2

NC_3

VSENSE4

ENA5GND6VIN7PH8

GN

D9




Schematics

http://www.ti.com


EPROM

I2C

DP/DM

(U1)TUSB7340

RX/TX USB3TYPEA

PCIECONNECTOR

DOWNSTREAMPORT1

DOWNSTREAMPORT2USB3

TYPEA

USB3TYPEA

USB3TYPEA

DOWNSTREAMPORT3

DOWNSTREAMPORT4

DP/DM

RX/TX

DP/DM

RX/TX

DP/DM

RX/TX

RX/TX

VIA AND TRACE REQUIREMENTS:- MIN VIA PAD SIZE 20mils- MIN spacing between trace and pad is 5mils- MIN spacing between VIA and pad is 5mils- MIN width of trace is 4mils

IMPEDANCE REQUIREMENTS:- USB_DP/M must be 90-ohm differential (+/-15%)- USB_SSTXP/N must be 90-ohms differential (+/-15%)- USB_SSRXP/N must be 90-ohms differential (+/-15%)- PCIE_TXP/N must be 100-ohms differential (+/-10%)- PCIE_RXP/N must be 100-ohms differential (+/-10%)- PCIE_REFCLKP/N must be 100-ohms differential (+/-10%)

LENGTH MATCHING REQUIREMENTS:- USB_DP/M within 25mils.- USB_SSTXP/N within 5mils- USB_SSRXP/N within 5mils- PCIE_TXP/N within 5mils- PCIE_RXP/N within 5mils- PCIE_REFCLKP/N within 25mils.

Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7340_DEMO_REVB_48


B

1 4Sheet of

SIZE

SCALE: NONE

DWG NO:



B

1 4Sheet of

SIZE

SCALE: NONE

DWG NO:



B

1 4




Schematics

15.2 TUSB7340 DEMO EVM REVB Schematics

http://www.ti.com


POPULATE PULLDOWN IF I2C EEPROM

NOT USED AND DO NOT POPULATE

PULLUP.

PLACE CLOSE TO U1

POPULATE R2 FOR WAKE SUPPORT. JUMPER J22 FOR NO WAKE SUPPORT

AU

X_

DE

T

SDA

R1EXT

R1EXTRTN

FREQSEL

VSS_OSC

XO

XI

SCLGPIO0GPIO1GPIO2GPIO3


VDDA3P3VBOARD_1P1V BOARD_3P3VBOARD_3P3V

BOARD_3P3V

BOARD_3P3V

BOARD_3P3V





USB_SSRXN_DN3 pg3


PWRON3Z pg3


USB_SSRXP_DN3 pg3

OVERCUR3Z pg3





USB_DM_DN1 pg3USB_DP_DN1 pg3

USB_SSRXN_DN1 pg3USB_SSRXP_DN1 pg3

USB_SSTXN_DN1 pg3USB_SSTXP_DN1 pg3

PWRON1Z pg3OVERCUR1Z pg3

PCIE_REFCLKNpg3PCIE_REFCLKPpg3

PCIE_RXNpg3PCIE_RXPpg3

PCIE_TXNpg3PCIE_TXPpg3

PERSTZpg3

WAKEZpg3

GRSTZpg4

Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7340

Tuesday, July 19, 2011

C

2 4Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7340


C

2 4Sheet of

SIZE

SCALE: NONE

DWG NO:

TUSB7340


C

2 4

R3NOPOP

04025%

C2

18pF

Y1

ECS-48MHZ

U2

24LC01_NF

A01

A12

A23

GND4

SDA5SCL6WP7VCC8

R114.7K

04025%

R7NOPOP

04025%

R1NOPOP

04025%

R39

0

R38

0

R6NOPOP

04025%

R8NOPOP

04025%

C3

18pF

R12 1M

R10 9.09K 1%

R210K

04025% J22

HDR2X1 M .1

12

R4NOPOP

04025%

C1

0.1uF

TUSB7340

TUSB7340_REVA

U1

CLKREQ#B36

FREQSELB14

GPIO0A49

GPIO1B46

GPIO2B47

GPIO3B48

GRST#A15

JTAG_RST#B32

JTAG_TCKA32

JTAG_TDIA35

JTAG_TDOB31

JTAG_TMSB30

PCIE_REFCLKNB41

PCIE_REFCLKPA45

PCIE_RXNA42

PCIE_RXPB39

PCIE_TXNA41

PCIE_TXPB38

PERST#A40

SCLB2

SDAA2

SMIB3

WAKE#B35

OVERCUR1#A36

OVERCUR2#A37

OVERCUR3#B43

OVERCUR4#B45

PWRON1#B33

PWRON2#B34

PWRON3#A46

PWRON4#A48

R1EXTA24

R1EXTRTNB23

USB_DM_DN1B18

USB_DM_DN2A13

USB_DM_DN3A27

USB_DM_DN4A5

USB_DP_DN1A20

USB_DP_DN2B12

USB_DP_DN3B25

USB_DP_DN4B5

USB_SSRXN_DN1B16

USB_SSRXP_DN2B9

USB_SSRXN_DN3A29

USB_SSRXN_DN4A7

USB_SSRXP_DN1A18

USB_SSRXN_DN2A10

USB_SSRXP_DN3B27

USB_SSRXP_DN4B6

USB_SSTXN_DN1B15

USB_SSTXN_DN2B10

USB_SSTXN_DN3A30

USB_SSTXN_DN4A8

USB_SSTXP_DN1A17

USB_SSTXP_DN2A11

USB_SSTXP_DN3B28

USB_SSTXP_DN4B7

VSS_OSCB21

XIA23

XOA22

AU

X_D

ET

A52

VD

DA

_3P

3A

25

VD

D11

A1

VD

D11

A12

VD

D11

A16

VD

D11

A28

VD

D11

A31

VD

D11

A33

VD

D11

A38

VD

D11

A4

NC

6A

43

VD

D11

A50

VD

D11

A6

VD

D11

A9

VD

D11

B1

VD

D11

B17

VD

D11

B19

VD

D11

B24

VD

D11

B37

VD

D11

B40

VD

D11

B42

VD

D11

B44

NC

5B

8

VD

D33

A3

VD

D33

A34

VD

D33

A39

VD

D33

A47

VD

D33

A51

VD

DA

_3P

3A

19

VD

DA

_3P

3A

21

VD

DA

_3P

3A

44

VD

DA

_3P

3B

11

VD

DA

_3P

3B

22

VD

DA

_3P

3B

26

VD

DA

_3P

3B

4

NC

1A

14

NC

2A

26

NC

3B

13

NC

4B

29

VS

SB

20

VS

SA

53

NC

7C

1

NC

8C

2

NC

9C

3

NC

10

C4

R5NOPOP

04025%

BOARD_1P1V

C32

0.1uF

C17

0.1uF

C36

0.01uF

C12

0.01uF

C31

0.1uF

C18

0.01uF

C34

0.1uF

C20

0.1uF

C21

0.01uF

C23

0.1uF

C16

0.1uF

C37

0.1uF

C13

0.1uF

C30

0.01uF

C33

0.01uF

C24

22uF

C19

0.1uF

C35

0.1uF

C14

0.1uF

C22

0.1uF

C15

0.01uF

VDDA3P3VBOARD_3P3V

C6

0.1uF

C28

0.1uF

FB1

220 @ 100MHZ

C25

0.1uF

C9

0.1uF

C7

0.01uF

C11

0.1uF

C29

0.1uF

C5

0.01uF

C26

0.1uF

C10

0.01uFC422uF

C8

0.1uF

C27

0.1uF




Schematics

http://www.ti.com


DOWNSTREAMPORT1

DOWNSTREAMPORT2

DOWNSTREAMPORT3

DOWNSTREAMPORT4

JUMPER BETWEEN 1 AND2 FOR NORMALOPERATION.

JUMPER BETWEEN 2 AND3 FOR WAKE TESTING.

PCIE CEM SPEC MAX VALUES:PCIE_3P3V: 3 AMPS.VAUX: 375mA

IND_USB_DP_DN1

DS1_VBUS

USB_SSRXP_DN1

IND_USB_DM_DN1

IND_USB_DP_DN2

DS2_VBUS


IND_USB_DM_DN2

ILIM1

DS3_VBUS

DS1_VBUSDS_SHLD

LE

DD

S1

LE

DD

S3

CAP_US_TXNCAP_US_TXP

PCIE_PRSNTZ

PCIE_TDITDO

ILIM2

DS2_VBUS

DS4_VBUS

LE

DD

S4

LE

DD

S2

IND_USB_DP_DN3

DS3_VBUS

USB_SSRXP_DN3

USB_SSRXN_DN3

IND_USB_DM_DN3

IND_USB_DP_DN4

DS4_VBUS


IND_USB_DM_DN4

DS_SHLDDS_SHLD

DS_SHLDDS_SHLD

DS_SHLDDS_SHLD

IND_DS_TXN1

IND_DS_TXP1

IND_DS_TXN2

IND_DS_TXP2

IND_DS_TXN3

IND_DS_TXP3

IND_DS_TXN4

IND_DS_TXP4

WAKEZ_R

USB_SSRXN_DN1

CAPDSTXP1

CAPDSTXN1

CAPDSTXP2

CAPDSTXN2

CAPDSTXP3

CAPDSTXN3

CAPDSTXP4

CAPDSTXN4

BOARD_5V

BOARD_3P3V

BOARD_5V

BOARD_3P3V

PCIE_3P3VPCIE_3P3V BOARD_12V

VAUX

BOARD_3P3V

PWRON1Zpg2

PWRON3Zpg2

PCIE_RXP pg2PCIE_RXN pg2

PCIE_REFCLKN pg2

PCIE_REFCLKP pg2

WAKEZpg2 PERSTZ pg2

PCIE_TXN pg2

PCIE_TXP pg2

PWRON4Zpg2

PWRON2Zpg2

OVERCUR3Z pg2

OVERCUR1Z pg2

OVERCUR2Z pg2

OVERCUR4Z pg2

USB_DM_DN1 pg2

USB_DP_DN1 pg2

USB_SSRXP_DN1 pg2

USB_SSRXN_DN1 pg2

USB_SSTXN_DN1 pg2

USB_SSTXP_DN1 pg2

USB_DM_DN2 pg2

USB_DP_DN2 pg2

USB_SSRXN_DN2 pg2

USB_SSRXP_DN2 pg2

USB_SSTXP_DN2 pg2

USB_SSTXN_DN2 pg2

USB_SSTXN_DN3 pg2

USB_SSTXP_DN3 pg2

USB_DM_DN3 pg2

USB_DP_DN3 pg2

USB_SSRXP_DN3 pg2

USB_SSRXN_DN3 pg2

USB_SSTXP_DN4 pg2

USB_SSTXN_DN4 pg2

USB_DM_DN4 pg2

USB_DP_DN4 pg2

USB_SSRXN_DN4 pg2

USB_SSRXP_DN4 pg2

Sheet of

SIZE

SCALE: NONE

DWG NO:



C

3 4Sheet of

SIZE

SCALE: NONE

DWG NO:



C

3 4Sheet of

SIZE

SCALE: NONE

DWG NO:



C

3 4

C41

0.1uF

C39 0.1uF

R30

1M

0402

L5

TDK_TCE_1210

1

2 3

4

R13

10K

0402

5%

Side BComponent Side

Side ASolder Side

Key

P1

PCI Express x1 Edge Connector

12V1B1

12V2B2

12V5B3

GND1B4

SMCLKB5

SMDATB6

GND2B7

3.3VB8

J_TRST#B9

3.3VauxB10

WAKE#B11

RSVD2B12

GND3B13

PETp0B14

PETn0B15

GND4B16

PRSNT2#B17

GND5B18

PRSNT1#A1

12V3A2

12V4A3

GND9A4

J_TCKA5

J_TDIA6

J_TDOA7

J_TMSA8

3.3V1A9

3.3V2A10

PERST#A11

GND8A12

REFCLK+A13

REFCLK-A14

GND7A15

PERp0A16

PERn0A17

GND6A18

L2

TDK_TCE_1210

1

2 3

4

C62

NOPOP

R14

10K

0402

5%

C49

0.1uF

L4

TDK_TCE_1210

1

2 3

4

R24330

04025% U26

TPD2EUSB30_NF

D+1

D-2

GND3

C51

0.1uF

C56 0.1uF

C50

0.001uF

C42

0.001uF

R1533004025%

D3

LED Green 0805

R21

1M

0402

+ C44150uF

L10

TDK_TCE_1210

1

2 3

4

U27

TPD2EUSB30_NF

D+1

D-2

GND3

C79

1000pF

R50 0

R23

10K

0402

5%

C43

0.1uF

+ C80NOPOP

D1

LED Green 0805

+ C46150uF

C64

22uF

U3

TPS2560DRC

GND1

IN2

IN3

EN14

EN25

FAULT2Z6

ILIM7

OUT28

OUT19

FAULT1Z10

PAD11

R22

10K

0402

5%

C67 0.1uF

C45

0.1uF

+ C55150uF

C63

NOPOP

L8

TDK_TCE_1210

1

2 3

4

C60 0.1uF

R19

30.9K

0402

1%

C68 0.1uF

R1633004025%

J2


VBUS1

DM2

DP3

GND4

SSRXN5

SSRXP6

GND7

SSTXN8

SSTXP9

SHIELD010

SHIELD111

C48 0.1uF

C54

0.1uF

R29

1M

0402

+ C53150uF

U24

TPD2EUSB30_NF

D+1

D-2

GND3

D2

LED Green 0805

C61 0.1uF

MH2

PLATED_MH

1

C58

0.1uF

J40

HDR1x3

123

R25330

04025%

J4


VBUS1

DM2

DP3

GND4

SSRXN5

SSRXP6

GND7

SSTXN8

SSTXP9

SHIELD010

SHIELD111

L13

TDK_TCE_1210

1

2 3

4

C52

0.1uF

C59

0.001uF

U4

TPS2560DRC

GND1

IN2

IN3

EN14

EN25

FAULT2Z6

ILIM7

OUT28

OUT19

FAULT1Z10

PAD11

MH1

PLATED_MH

1

C38

0.1uF

R27

30.9K

0402

1%

C40 0.1uF

D4

LED Green 0805

C65

0.1uF

L7

TDK_TCE_1210

1

2 3

4

U25

TPD2EUSB30_NF

D+1

D-2

GND3

C47 0.1uF

L11

TDK_TCE_1210

1

2 3

4

C66

0.001uF

C57 0.1uF

J1


VBUS1

DM2

DP3

GND4

SSRXN5

SSRXP6

GND7

SSTXN8

SSTXP9

SHIELD010

SHIELD111

J3


VBUS1

DM2

DP3

GND4

SSRXN5

SSRXP6

GND7

SSTXN8

SSTXP9

SHIELD010

SHIELD111

R17

1M

0402




Schematics

http://www.ti.com


1.1V REGULATOR

5V VBUS OPTIONS

R33 R35 OUTPUT1.13K 4.53K 1.0V1.37K 4.42K 1.05V1.87K 4.99K 1.1V (DEFAULT)2.49K 4.99K 1.2V

EN1P1

SS1P1FB_1PT1VL

ED

3V

BOARD_1P1V

BOARD_3P3V

BOARD_3P3V

GRSTZ pg2

D5

LED Green 0805

U5

TPS74401RGWT

OUT1

NC

2

NC

3

NC

4

IN5

IN6

IN7

IN8

PG9

BIAS10

EN11

GN

D12

NC

13

NC

14

SS15

FB16

NC

17

OUT18OUT19OUT20

PA

D21

C6910uF C85

0.1uF

R3433004025%

C7022uF

R32

4.7K

0402

5%

R31

10K

0402

5%

C71

0.01uF

R331.87K

04021%

C72

NOPOP

R354.99K

04021%



OPTION 1: 5V REGULATOR OPTION 2: 5V FROM IDE CONNECTOR

NOTE: ONLY POPULATE ONE OPTION

VSENSE

BOOT PH

REG_5V BOARD_12VIDE_5V

IDE_5V

REG_5V

BOARD_5V

Sheet of

SIZE

SCALE: NONE

DWG NO:

POWER


B

4 4Sheet of

SIZE

SCALE: NONE

DWG NO:

POWER


B

4 4Sheet of

SIZE

SCALE: NONE

DWG NO:

POWER


B

4 4

J27

NOPOP

1 2

L1

15uH_NF

R37

3.16K_NF

1%

C78

0.01uF_NF

+5VGND0GND1+12V

J5

IDE_PWR_CONN

4321

+ C73330uF_NF

R36

10K_NF

1%

D6

MBRS540T3_NFC75

0.01uF_NF

C74

0.01uF_NF

J26

HDR2X1 M .1

1 2

C7722uF_NF

C7622uFU6

TPS5450_NF

BOOT1

NC2

NC_3

VSENSE4

ENA5GND6VIN7PH8

GN

D9




Schematics

http://www.ti.com





Schematics

http://www.ti.com


Revision History www.ti.com



Revision History

Revision History

Changes from D Revision (May 2014) to E Revision ...................................................................................................... Page

• Changed text in Chapter 2 From: "PC host system via a PCIe x1 Gen 2 interface" To: "PC host system via a PCIe x1 Gen2 or PCIe Gen 1 interface" ............................................................................................................... 9

• Changed TUSB7320 schematic........................................................................................................ 52• Changed TUSB7340 schematic........................................................................................................ 56

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Revision History

Changes from C Revision (October 2013) to D Revision ............................................................................................... Page

• Replaced - Chapter 15: Schematics with Rev. B_48 ............................................................................... 50


Revision History

Changes from B Revision (October 2013) to C Revision ............................................................................................... Page

• Deleted - Chapter 14: Failsafe IO ..................................................................................................... 48


Revision History

Changes from A Revision (June 2012) to B Revision .................................................................................................... Page

• Replaced - Chapter 15: Schematics .................................................................................................. 50


Revision History

Changes from Original (June 2011) to A Revision ......................................................................................................... Page

• Changed text in High-Speed Differential RoutingFrom: "if routing longer than six inches contact TI to address signalintegrity concerns." To: "if routing longer than eight inches contact TI to address signal integrity concerns." .............. 25

• Changed text in SuperSpeed RedriverFrom: "differential pairs must be driven longer than 11 inches" To: "differential pairsmust be driven longer than eight inches." ............................................................................................ 46


http://www.ti.com


STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or

documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein.Acceptance of the EVM is expressly subject to the following terms and conditions.1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility

evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are notfinished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. Forclarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditionsset forth herein but rather shall be subject to the applicable terms and conditions that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or productionsystem.

2 Limited Warranty and Related Remedies/Disclaimers:2.1 These terms and conditions do not apply to Software. The warranty, if any, for Software is covered in the applicable Software

License Agreement.2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM

to User. Notwithstanding the foregoing, TI shall not be liable for any defects that are caused by neglect, misuse or mistreatmentby an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in anyway by an entity other than TI. Moreover, TI shall not be liable for any defects that result from User's design, specifications orinstructions for such EVMs. Testing and other quality control techniques are used to the extent TI deems necessary or asmandated by government requirements. TI does not test all parameters of each EVM.

2.3 If any EVM fails to conform to the warranty set forth above, TI's sole liability shall be at its option to repair or replace such EVM,or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during thewarranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects torepair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shallbe warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) daywarranty period.

3 Regulatory Notices:3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kitto determine whether to incorporate such items in a finished product and software developers to write software applications foruse with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unlessall required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not causeharmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit isdesigned to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority ofan FCC license holder or must secure an experimental authorization under part 5 of this chapter.3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTIONThis device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may notcause harmful interference, and (2) this device must accept any interference received, including interference that may causeundesired operation.Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority tooperate the equipment.

FCC Interference Statement for Class A EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment isoperated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if notinstalled and used in accordance with the instruction manual, may cause harmful interference to radio communications.Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required tocorrect the interference at his own expense.

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

SPACER

FCC Interference Statement for Class B EVM devicesNOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 ofthe FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residentialinstallation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordancewith the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interferencewill not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, whichcan be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or moreof the following measures:

• Reorient or relocate the receiving antenna.• Increase the separation between the equipment and receiver.• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210

Concerning EVMs Including Radio Transmitters:This device complies with Industry Canada license-exempt RSS standard(s). Operation is subject to the following two conditions:(1) this device may not cause interference, and (2) this device must accept any interference, including interference that maycause undesired operation of the device.

Concernant les EVMs avec appareils radio:Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitationest autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doitaccepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna typeand its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary forsuccessful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna typeslisted in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibitedfor use with this device.

Concernant les EVMs avec antennes détachablesConformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type etd'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillageradioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotroperayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Leprésent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans lemanuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antennenon inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation del'émetteur

3.3 Japan3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certifiedby TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required by Radio Law ofJapan to follow the instructions below with respect to EVMs:1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal

Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule forEnforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect toEVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japanwith respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please notethat if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

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http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page


【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用

いただく。2. 実験局の免許を取得後ご使用いただく。3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・イ

ンスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

SPACER4 EVM Use Restrictions and Warnings:

4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOTLIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.

4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handlingor using the EVM, including without limitation any warning or restriction notices. The notices contain important safety informationrelated to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user

guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable andcustomary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to inputand output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, orproperty damage. If there are questions concerning performance ratings and specifications, User should contact a TIfield representative prior to connecting interface electronics including input power and intended loads. Any loads appliedoutside of the specified output range may also result in unintended and/or inaccurate operation and/or possiblepermanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting anyload to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuitcomponents may have elevated case temperatures. These components include but are not limited to linear regulators,switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using theinformation in the associated documentation. When working with the EVM, please be aware that the EVM may becomevery warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with thedangers and application risks associated with handling electrical mechanical components, systems, and subsystems.User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees,affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronicand/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safelylimit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility andliability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors ordesignees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal,state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes allresponsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility andliability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and localrequirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurateas possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites asaccurate, complete, reliable, current, or error-free.

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SPACER6. Disclaimers:

6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THEDESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHERWARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIEDWARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANYTHIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS ANDCONDITIONS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANYOTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRDPARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANYINVENTION, DISCOVERY OR IMPROVEMENT MADE, CONCEIVED OR ACQUIRED PRIOR TO OR AFTER DELIVERY OFTHE EVM.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITSLICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES,EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANYHANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS AND CONDITIONS. THIS OBLIGATIONSHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANYOTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability:8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE,

INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESETERMS ANDCONDITIONS OR THE USE OF THE EVMS PROVIDED HEREUNDER, REGARDLESS OF WHETHER TI HASBEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITEDTO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODSOR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS,LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALLBE BROUGHT AGAINST TI MORE THAN ONE YEAR AFTER THE RELATED CAUSE OF ACTION HAS OCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY WARRANTY OR OTHER OBLIGATIONARISING OUT OF OR IN CONNECTION WITH THESE TERMS AND CONDITIONS, OR ANY USE OF ANY TI EVMPROVIDED HEREUNDER, EXCEED THE TOTAL AMOUNT PAID TO TI FOR THE PARTICULAR UNITS SOLD UNDERTHESE TERMS AND CONDITIONS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCEOF MORE THAN ONE CLAIM AGAINST THE PARTICULAR UNITS SOLD TO USER UNDER THESE TERMS ANDCONDITIONS SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s)will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not ina resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicableorder, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s),excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas,without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating tothese terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas.Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive reliefin any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2015, Texas Instruments Incorporated

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and otherchanges to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latestissue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current andcomplete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of salesupplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s termsand conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessaryto support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarilyperformed.TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products andapplications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, orother intellectual property right relating to any combination, machine, or process in which TI components or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of thethird party, or a license from TI under the patents or other intellectual property of TI.Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alterationand is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altereddocumentation. Information of third parties may be subject to additional restrictions.Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or servicevoids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirementsconcerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or supportthat may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards whichanticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might causeharm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the useof any TI components in safety-critical applications.In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is tohelp enable customers to design and create their own end-product solutions that meet applicable functional safety standards andrequirements. Nonetheless, such components are subject to these terms.No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the partieshave executed a special agreement specifically governing such use.Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use inmilitary/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI componentswhich have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal andregulatory requirements in connection with such use.TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use ofnon-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

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