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Transient Analysis CK ChengUC San DiegoJan. 25, 2007

OutlineResearch DirectionsSimulation test case resultsOverview of SimulationCommercial PackageAlternating direction implicit (ADI) MethodGeneral Operator Splitting MethodDistributed ComputingConclusions and Future Works

Research DirectionsSimulation: SPICE, STANetwork on Chip: topology and wire styles, Power, and Clock NetworksData Path Components: adders, shifters, multipliers, divisionPackaging: passive distortion compensation

6x6 Bump Simulation ResultsThe Circuit:184K Capacitors, 17K Current Sources, 120K Inductors and 246K Resistors. 306K NodesAccuracy:Waveform and measurement results match Fujitsus with less than 0.002% error.Runtime / Memory Comparison:

6x6 Bump Simulation ResultsMeasurement results and waveform(Red curve is UCSD result)

703KR Simulation ResultsThe Circuit:514K Capacitors, 76K Current Sources, 370K Inductors and 703K Resistors. 1.3M NodesAccuracy:Measurement results match Fujitsus with less than 0.02% error.Runtime / Memory Comparison:

703KR Simulation Results Measurement results and waveform(UCSD results only. Fujitsu waveform is not available for comparison)

Further Speed-upsReduce iteration count by 50% for pure linear circuits (like 6x6 bump and 703KR)2x speed upMore effective time step controlDVDT, breakpoint, truncation error. 1.5 - 3x speed upUse Multigrid solver1.5 - 2x speed up for medium circuits (6x6 bump)2x 10x speed up for large circuits (703KR)Parallel simulation4 or more processors on linux cluster32 to hundreds of processors on supercomputer.Overall speed-up6x - 60x speed up without parallel simulation12x - 1000x speed up with parallel simulation

Performance and capacity predictionCases 10x-100x larger than 703KR.

Overview of SimulationOur researchFast speed with SPICE accuracyNonlinear devicesEfficient matrix solversEffective integration methodsTime step controls according to different integration methodsDistributed computing

Overview of SimulationMatrix SolverLU DecompositionIterative ApproachIntegrationTime Step ControlADINonlinear DevicesTwo Stage Newton RaphsonDistributed ComputingCommercial Implementation

Overview of SimulationIntegrationTime Step ControlADI (two-way partitioning)Operator Splitting (multi-way)Distributed ComputingMPIPartitioningThree Ph.D. Students

Commercial Package: Fastrack DesignFounded in January 2001Headquartered in San JosePrivately funded, cash-flow positiveTwo Business UnitsDesign ServicesTechnology Products

Analog Designs

Digital Blocks

Memory Blocks100% accurate Spice simulation

mSPICE-ParallelIndustrys first practical parallel Spice simulation solutionIncreases capacity furtherDramatically improves throughputUses Matrix Level PartitioningNo loss of accuracyClient-Server configurationMinimal memory requirement for client nodes

Client-Server ConfigurationServer distributes sub-matrices to clientsClients communicate partial solutionsMinimal memory requirements for clients

Experimental Results

ADI: Previous Works1999, Namiki and Ito the alternating direction implicit (ADI) is used to simulate a 2D TE wave. 2001, Zheng etc. extend to 3D problem2001 & 2003, Lee and ChenADI is used to transmission line modeled power grid

The alternation is among different geometric directions, so the simulated geometric structure is constrained.

Alternating Direction Implicit (ADI)ADI Integration MethodTwo way partition of the circuitOne partition is used for each backward integration Unconditional stable (A-stable: independent of time step size)Time step size according to local truncation error.

Alternating Direction Implicit (ADI)

ADI method formulationCircuit partition algorithmLocal truncation error estimationStability discussionExperimental results

SPICE FormulationEquations for RLC circuits

where C: capacitance matrix L: inductance matrix R: resistance matrix G: conductance matrix E: incidence matrix

ADI FormulationTransient simulationSplit the resistors and inductors branches into two parts G = G1 + G2 E = E1 + E2 R = R1 + R2Alternate Backward and Forward integration on each partition

ADI Formulation (Cont.)Equations of ADI method

the size of left-hand-side matrix remains unchangedthe number of non-zero elements is decreaseddirect solving methods can be efficient

Experiments of non-zero fill-insA small ASIC DesignSpice matrix : Dimension: 10,286 The number of non-zero elements: 46,655 The number of non-zero fill-ins: 90,960A large I/O DesignSpice matrix : Dimension: 615,436 The number of non-zero elements: 2,126,246

Sub-matrix1Sub-matrix2Total # non-zero fill-ins# non-zero elements# non-zero fill-ins# non-zero elements# non-zero fill-insCase 138,5722,61842,02010,04012,658Case 21,176,20812,421,534950,03814,772,06827,193,602

Local Truncation Error (LTE)Time step control using LTEIn circuit transient analysis, the next time step can be estimated from the local truncation error at the present time pointLTE is defined as the difference between the calculated solution and the exact solution

To ensure the consistency, the local truncation error should not exceed the error tolerance, thus the time step can be estimated using

Local Truncation Error (Cont.)LTE of ADI method(1) equations

let , , and

then

Local Truncation Error (Cont.)LTE of ADI method(2) Estimate exact solution we characterize the input as a simple ramp over the interval (tn, tn+1), the exact analytic solution with time step tn:

Local Truncation Error (Cont.)LTE of ADI method(3) Estimate ADI solution

Local Truncation Error (Cont.)LTE of ADI method(3) Estimate ADI solution

Local Truncation Error (Cont.)LTE of ADI method(4) LTE estimation

Local Truncation Error (Cont.)LTE of ADI method(5) Time step control

Local Truncation Error (Cont.)LTE of ADI method(5) Time step control

Stability DiscussionThe stability is concerned with whether the accumulated error grows or decays as time evolves through a series of time steps.One-step integration approximations, the error is accumulated by a factor of

If the final steady state error vector is smaller than the initial, then the integration method is stable.In ADI integration method:

It can be proved to be unconditional stable

Experimental Results

Voltage drop of Circuit3 (power mesh with sinks)

Signal in 1k_cell (ASIC design)

General Operator SplittingGeneral operator splitting methodMultiple way partitionsEach partition is considered separately in each time step simulation No geometry constrainsLocal truncation error is used to dynamically control time step size

General Operator Splitting

Fundamental theoryOperator splitting formulationLocal truncation error estimationStability discussionExperimental results

Fundamental theoryIn circuit transient simulation, the integration approximation is actually the approximation of the exponential operatorThe exponential operators can be approximated in any order using a general scheme of fractal decompositionThe decomposition of exponential operators corresponds to the circuit multi-way partition

New integration approximation in transient simulation

Fundamental theoryApproximation of exponential operatorGeneral circuit equation and solution

If we characterize the input as a simple ramp over the interval (tn, tn+1), the exact analytic solution with time step tn

Exponential operator approximationForward EulerBackward EulerTrapezoidal

Fundamental theoryDecomposition of exponential operators (Masuo Suzuki, 1991, Physics)FunctionFirst order:Second order:Third order:

(2m-1)th and (2m)th order:

Fundamental theoryDecomposition of exponential operators

General Operator Splitting Formulation Transient simulation:Apply the second order approximation

In each time step, every partition is calculated separately and trapezoidal integration is used for every partitionThe size of left-hand-side matrix may be changedThe number of non-zero elements is definitely decreasedCan be easily extended to multi-way partitions

General Operator Splitting Formulation Equations

Local Truncation Error (Cont.)LTE of general operator splitting methodEstimate solution

Local Truncation Error (Cont.)LTE of general operator splitting methodEstimate solution

Local Truncation Error (Cont.)LTE of general operator splitting methodLTE estimation

Local Truncation Error (Cont.)LTE of general operator splitting methodLTE estimation

Local Truncation Error (Cont.)LTE of general operator splitting methodLTE estimation

Stability DiscussionThe trapezoidal integration method is unconditional stable for stable system.

In our operator splitting method, trapezoidal method is used for all the sub-systems

still unconditional stable

Experimental Results

Circuit1Cuicuit2Circuit3#Nodes10,00040,00090,000#Transistors000Period10ns10ns10nsSPICE3CPU time (sec)77.8485.33,061.1#steps115115114GOSCPU time (sec)164.71011.63435.9#steps102102102Comparison2.1x2x1.1x

Voltage drop of Circuit3 (power mesh with sinks)

ConclusionsWe investigate alternating direction implicit and general ope