TPS7B68-Q1 500-mA 40-V high-voltage ultralow quiescent

MCU

Supply

OUTIN

TPS7B6850-Q1

PGADJEN

DELAY

WDO

WRS

ROSC

WD

PG

WD_EN

WTS

FSEL

Battery

MCU I/O

GND

Digital I/O MCU

I/O

MCU

Reset

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS7B68-Q1SLVSD43C –MAY 2015–REVISED FEBRUARY 2019

TPS7B68-Q1 500-mA 40-V high-voltage ultralow quiescent-current watchdog LDO

1

1 Features1• Qualified for automotive applications• AEC-Q100 qualified with the following results:

– Device temperature grade 1: –40°C to +125°Cambient operating temperature range

– Device HBM ESD classification level 2– Device CDM ESD classification level C4B

• Maximum output current: 500 mA• 4-V to 40-V wide VIN input-voltage range with up

to 45-V transients• Fixed 3.3-V and 5-V outputs• Maximum dropout voltage: 600 mV at 500 mA• Stable with output capacitor in wide-range of

capacitance (4.7 µF to 500 µF) and ESR (0.001 Ωto 20 Ω)

• Low quiescent current (I(Q)):– < 4 µA when EN is low (shutdown mode)– 19 µA typical at light loads with WD_EN high

(watchdog disabled)• Configurable for window watchdog or standard

watchdog• Open-to-closed window ratio configurable as 1:1

or 8:1• Fully adjustable watchdog period (from 10 ms to

500 ms)• 10% accurate watchdog period• Dedicated WD_EN pin to control watchdog ON-

OFF• Fully adjustable power-good threshold and power-

good delay period• Low Input-voltage tracking to UVLO• Integrated fault protection:

– Overload current-limit protection– Thermal shutdown

• 28-Pin HTSSOP package

2 Applications• Automotive MCU power supply• Body control modules (BCM)• Body comfort modules• EV and HEV battery management systems (BMS)• Electronic gear shifter• Transmission control unit (TCU)• Electrical power steering (EPS)

3 DescriptionIn automotive microcontroller or microprocessorpower-supply applications, the watchdog is used tomonitor the microcontroller working status to preventsoftware runaway. The watchdog must beindependent of the microcontroller in a reliablesystem.

The TPS7B68-Q1 is a 500-mA watchdog LDOdesigned for an operating voltage up to 40 V, withtypical quiescent current of only 19 µA at light load.The device integrates a programmable function forselecting a window or standard watchdog, with anexternal resistor to set the watchdog time within 10%accuracy.

The PG pin on the TPS7B68-Q1 indicates when theoutput voltage is stable and in regulation. The power-good delay period and power-good threshold can beadjusted by external components. The device alsofeatures an integrated short-circuit and overcurrentprotection. The combination of such features makesthis device particularly flexible and suitable to supplymicrocontroller systems in automotive applications.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)TPS7B68-Q1 HTSSOP (28) 9.70 mm × 4.40 mm

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

Typical Application Schematic

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 46 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 56.2 ESD Ratings.............................................................. 66.3 Recommended Operating Conditions....................... 66.4 Thermal Information .................................................. 66.5 Electrical Characteristics........................................... 76.6 Switching Characteristics .......................................... 96.7 Typical Characteristics ............................................ 10

7 Detailed Description ............................................ 147.1 Overview ................................................................. 147.2 Functional Block Diagram ....................................... 147.3 Feature Description................................................. 14

7.4 Device Functional Modes........................................ 218 Application and Implementation ........................ 22

8.1 Application Information............................................ 228.2 Typical Application ................................................. 22

9 Power Supply Recommendations ...................... 2510 Layout................................................................... 25

10.1 Layout Guidelines ................................................. 2510.2 Layout Example .................................................... 25

11 Device and Documentation Support ................. 2611.1 Documentation Support ........................................ 2611.2 Receiving Notification of Documentation Updates 2611.3 Community Resources.......................................... 2611.4 Trademarks ........................................................... 2611.5 Electrostatic Discharge Caution............................ 2611.6 Glossary ................................................................ 26

12 Mechanical, Packaging, and OrderableInformation ........................................................... 26

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (September 2017) to Revision C Page

• Changed watchdog accuracy from 9% to 10% throughout document ................................................................................... 1• Changed Device Information table ........................................................................................................................................ 1• Changed test conditions of VOUT parameter ........................................................................................................................... 7• Added second row to VOUT parameter ................................................................................................................................... 7• Changed V(dropout) parameter maximum specifications from 600 mV to 800 mV at 500 mA and changed 260 mV to

325 mV at 200 mA.................................................................................................................................................................. 7• Added footnote indicating dropout is not tested for the 3.3-V option at 200 mA.................................................................... 7• Changed first row test conditions of I(LIM) parameter: changed VIN = 5.6 V to 40 V to VIN = 5.6 V and added voltage

option ...................................................................................................................................................................................... 7• Added second row to I(LIM) parameter for the 3.3-V option..................................................................................................... 7• Changed t(DEGLITCH) parameter minimum specification from 100 µs to 55 µs ........................................................................ 9• Changed t(DLY_FIX) parameter specifications: deleted minimum specification and changed maximum specification

from 550 µs to 900 µs ........................................................................................................................................................... 9• Changed t(WD_TOL) parameter: changes test conditions, changed minim specification from –9% to –10%, and

changed maximum specification from 9% to 10%.................................................................................................................. 9• Changed Several Typical Periods of Watchdog Window table to reflect change in watchdog duration accuracy from

9% to 10% ............................................................................................................................................................................ 17

Changes from Revision A (December 2016) to Revision B Page

• Changed V(PG_TH) symbol to V(PG_TH) rising and V(PGADJ_TH) symbol to V(PGADJ_TH) falling in Electrical Characteristics table ......... 8• Added V(PGADJ_HYST) parameter to Electrical Characteristics table ......................................................................................... 8• Changed Adjustable Power-Good Threshold section: updated symbols and changed Equation 1 .................................... 15• Changed parameter symbols in Power Up and Conditions for Activation of Power Good figure and added footnote ........ 16• Changed parameter symbols in Window Watchdog Operation figure and added footnote ................................................. 20• Changed parameter symbols in Standard Watchdog Operation figure and added footnote ............................................... 21


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Changes from Original (June 2016) to Revision A Page

• Changed the status of the TPS7B6850-Q1 from Product Preview to Production Data ......................................................... 1


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Not to scale

Thermal

Pad

1IN 28 OUT

2NC 27 NC

3NC 26 NC

4EN 25 PGADJ

5FSEL 24 PG

6WTS 23 NC

7NC 22 NC

8GND 21 GND

9NC 20 NC

10NC 19 NC

11ROSC 18 WRS

12DELAY 17 NC

13WD 16 WD_EN

14NC 15 WDO

4




(1) I = input, O = output, G = ground.

5 Pin Configuration and Functions

PWP PowerPAD™ Package28-Pin HTSSOP With Exposed Thermal Pad

Top View

NC - No internal connection

Pin FunctionsPIN

TYPE (1) DESCRIPTIONNAME NO.

DELAY 12 O Power-good delay-period adjustment pin. Connect this pin via a capacitor to ground to adjustthe power-good delay time.

EN 4 I Device enable pin. Pull this pin down to low-level voltage to disable the device. Pull this pinup to high-level voltage to enable the device.

FSEL 5 IInternal oscillator-frequency selection pin. Pull this pin down to low-level voltage to select thehigh-frequency oscillator. Pull this pin up to high-level voltage to select the low-frequencyoscillator.

GND 8, 21 G Ground referenceIN 1 I Device input power-supply pin

NC

2, 3, 7, 9, 10,14, 17, 19,20, 22, 23,

26, 27

— Not connected

OUT 28 O Device 3.3-V or 5-V regulated output voltage pin

PG 24 O Power-good pin. Open-drain output pin. Pull this pin up to VOUT or to a reference through aresistor. When the output voltage is not ready, this pin is pulled down to ground.

PGADJ 25 OPower-good threshold-adjustment pin. Connect a resistor divider between the PGADJ andOUT pins to set the power-good threshold. Connect this pin to ground to set the threshold to91.6% of output voltage VOUT.


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5




Pin Functions (continued)PIN

TYPE (1) DESCRIPTIONNAME NO.

ROSC 11 OWatchdog timer adjustment pin. Connect a resistor between the ROSC pin and the GND pinto set the duration of the watchdog monitor. Leaving this pin open or connecting this pin toground results in the watchdog reporting a fault at the watchdog output (WDO).

WD 13 I Watchdog service-signal input pin.

WDO 15 O Watchdog status pin. Open-drain output pin. Pull this pin up to OUT or a reference voltagethrough a resistor. When watchdog fault occurs, this pin is pulled down to a low-level voltage.

WD_EN 16 I Watchdog enable pin. Pull this pin down to a low level to enable the watchdog. Pull this pinup to a high level to disable the watchdog.

WRS 18 IWindow ratio selection pin (only applicable for the window watchdog). Pull this pin down to alow level to set the open:closed window ratio to 1:1. Pull this pin up to high level to set theopen:closed window ratio to 8:1.

WTS 6 O Watchdog type-selection pin. To set the window watchdog, connect this pin to the GND pin.To set the standard watchdog, pull this pin high.

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground.

6 Specifications

6.1 Absolute Maximum Ratingsover operating ambient temperature range (unless otherwise noted) (1) (2)

MIN MAX UNITUnregulated input IN, EN –0.3 45 VInternal oscillator reference voltage ROSC –0.3 7 VPower-good delay-timer output DELAY –0.3 7 VRegulated output OUT –0.3 7 VPower-good output voltage PG –0.3 7 VWatchdog status output voltage WDO –0.3 7 VWatchdog frequency selection, watchdog-type selection FSEL, WTS –0.3 45 VWatchdog enable WD_EN –0.3 7 VWatchdog service signal voltage WD –0.3 7 VWindow ratio selection WRS –0.3 7 VPower good threshold adjustment voltage PGADJ –0.3 7 VOperating junction temperature, TJ –40 150 °CStorage temperature, Tstg –65 150 °C


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6




(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD RatingsVALUE UNIT

V(ESD)Electrostaticdischarge

Human-body model (HBM), per AEC Q100-002 (1) ±2000V

Charged-device model (CDM), per AEC Q100-011All pins ±500Corner pins (1, 14, 15, and 28) ±750

6.3 Recommended Operating Conditionsover operating ambient temperature range (unless otherwise noted)

MIN MAX UNITUnregulated input IN 4 40 V40-V pins EN, FSEL, WTS 0 VIN VRegulated output OUT 0 5.5 VPower good, watchdog status,reference oscillator PG, WDO, ROSC 0 5.5 V

Low voltage pins WD, WD_EN, PGADJ, DELAY, WRS 0 5.5 VOutput current 0 500 mAOperating junction temperature, TJ –40 150 °CAmbient temperature, TA –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)TPS7B68-Q1

UNITPWP (HTSSOP)28 PINS

RθJA Junction-to-ambient thermal resistance 37.8 °C/WRθJC(top) Junction-to-case (top) thermal resistance 18.4 °C/WRθJB Junction-to-board thermal resistance 18.7 °C/WψJT Junction-to-top characterization parameter 0.8 °C/WψJB Junction-to-board characterization parameter 18.5 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 2.4 °C/W


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(1) This test is done with VOUT in regulation, measuring the VIN – VOUT when VOUT drops by 100 mV from the rated output voltage at thespecified load.

(2) Dropout is not measured for VOUT = 3.3 V in this test because VIN must be 4 V or greater for proper operation.(3) Design Information – Not tested, determined by characterization.

6.5 Electrical CharacteristicsVIN = 14 V, COUT ≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSUPPLY VOLTAGE AND CURRENT (IN)VIN Input voltage 4 40 VI(SLEEP) Input sleep current EN = OFF 4 µA

I(Q) Input quiescent current

VIN = 5.6 V to 40 V for fixed 5-VVOUT; VIN = 4 V to 40 V for fixed3.3-V VOUT; EN = ON; watchdogdisabled; IOUT < 1 mA;TJ < 80°C

19 29.6

µAVIN = 5.6 V to 40 V for fixed 5-VVOUT; VIN = 4 V to 40 V for fixed3.3-V VOUT; EN = ON; watchdogenabled; IOUT < 1 mA

28 42

VIN = 5.6 V to 40 V for fixed 5-VVOUT; VIN = 4 V to 40 V for fixed3.3-V VOUT; EN = ON; watchdogenabled; IOUT < 100 mA

78 98

V(UVLO) Undervoltage lockout, falling Ramp VIN down until output isturned off 2.6 V

V(UVLO_HYST)

UVLO hysteresis 0.5 V

ENABLE INPUT, WATCHDOG TYPE SELECTION AND FSEL (EN, WTS, AND FSEL)VIL Low-level input voltage 0.7 VVIH High-level input voltage 2 VVhys Hysteresis 150 mVWATCHDOG ENABLE (WD_EN PIN)

VILLow-level input threshold voltage forwatchdog enable pin Watchdog enabled 0.7 V

VIHHigh-level input threshold voltage forwatchdog enable pin Watchdog disabled 2 V

IWD_ENPulldown current for watchdogenable pin VWD_EN = 5 V 3 µA

REGULATED OUTPUT (OUT)

VOUT Regulated output

VIN = VOUT + 1 V to 40 V,IOUT = 0 to 500 mA –2% 2%

VIN = 5.4 V, IOUT = 250 mATJ = –40°C to 85°C –2% 2%

ΔVOUT(ΔVIN)

Line regulation VIN = 5.6 V to 40 V 10 mV

ΔVOUT(ΔIOUT)

Load regulation IOUT = 1 mA to 500 mA 20 mV

V(dropout) Dropout voltage (VIN – VOUT) (1) IOUT = 500 mA 350 800mV

IOUT = 200 mA (2) 170 325IOUT Output current VOUT in regulation 0 500 mA

I(LIM) Output short-circuit current limit

VOUT shorted to ground, VIN = 5.6 V,TPS7B6850QPWPRQ1 550 690 1000

mAVOUT shorted to ground, VIN = 5.6V,TPS7B6833QPWPRQ1 490 690 1000

PSRR Power supply ripple rejection (3)

IOUT = 100 mA; COUT = 10 µF;frequency (f) = 100 Hz 60

dBIOUT = 100 mA; COUT = 10 µF;frequency (f) = 100 kHz 40


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8




Electrical Characteristics (continued)VIN = 14 V, COUT ≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER GOOD (PG, PGADJ)VOL(PG) PG output, low voltage IOL = 5 mA, PG pulled low 0.4 V

Ilkg(PG) PG pin leakage current PG pulled to VOUT through a 10-kΩresistor 1 µA

V(PG_TH)rising

Default power-good thresholdVOUT powered above the internallyset tolerance, PGADJ pin shorted toground

89.6 91.6 93.6 % of VOUT

V(PG_HYST) Power-good hysteresis VOUT falling below the internally settolerance hysteresis 2 % of VOUT

PGADJV(PGADJ_TH) falling

Switching voltage for the power-good adjust pin VOUT is falling 1.067 1.1 1.133 V

V(PGADJ_HYST)

PGADJ hysteresis 26 mV

POWER-GOOD DELAYI(DLY_CHG) DELAY capacitor charging current 3 5 10 µA

V(DLY_TH)DELAY pin threshold to release PGhigh Voltage at DELAY pin is ramped up 0.95 1 1.05 V

I(DLY_DIS)DELAY capacitor dischargingcurrent VDELAY = 1 V 0.5 mA

CURRENT VOLTAGE REFERENCE (ROSC)VROSC Voltage reference 0.95 1 1.05 VWATCHDOG (WD, WDO, WRS)

VIL

Low-level threshold voltage for thewatchdog input and window-ratioselect

For WD and WRS pins 30 % of VOUT

VIH

High-level threshold voltage for thewatchdog input and window-ratioselect

For WD and WRS pins 70 % of VOUT

V(HYST) Hysteresis 10 % of VOUT

IWD Pulldown current for the WD pin VWDO = 5 V 2 4 µAVOL Watchdog output pulled low IWDO = 5 mA 0.4 V

Ilkg WDO pin leakage current WDO pin pulled to VOUT through10-kΩ resistor 1 µA

OPERATING TEMPERATURE RANGETJ Junction temperature –40 150 °CT(SD) Junction shutdown temperature 175 °CT(HYST) Hysteresis of thermal shutdown 25 °C


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9




6.6 Switching CharacteristicsVI = 14 V, CO ≥ 4.7 µF, 1 mΩ < ESR < 20 Ω, and TJ = –40°C to 150°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITPOWER-GOOD DELAY (DELAY)t(DEGLITCH) Power-good deglitch time 55 180 250 µst(DLY_FIX) Fixed power-good delay No capacitor connect at DELAY pin 248 900 µs

t(DLY) Power-on-reset delay Delay capacitor value:C(DELAY) = 100 nF 20 ms

WATCHDOG (WD, WDO, WRS)

t(WD) Watchdog window durationR(ROSC) = 20 kΩ ±1%, FSEL = LOW 9 10 11

msR(ROSC) = 20 kΩ ±1%, FSEL = HIGH 45 50 55

t(WD_TOL)Tolerance of watchdog windowduration using external resistor

R(ROSC) =20 kΩ ±1% to 50 kΩ ±1% –10% 10%

tp(WD) Watchdog service-signal duration 100 µs

t(WD_HOLD)

Watchdog output resetting time(percentage of settled watchdogwindow duration)

20 % oft(WD)

t(WD_RESET) Watchdog output resetting timeR(ROSC) = 20 kΩ ± 1%, FSEL = LOW 1.8 2 2.2

msR(ROSC) = 20 kΩ ± 1%,FSEL = HIGH 9 10 11


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Output Current (mA)

Dro

pout

Vol

tage

(m

V)

0 50 100 150 200 250 300 350 400 450 5000

100

200

300

400

500

600

D005

-40qC25qC125qC

Ambient Temperature (°C)

Dro

pout

Vol

tage

(m

V)

-40 -25 -10 5 20 35 50 65 80 95 110 1250

50

100

150

200

250

300

D006

Ambient Temperature (qC)

Shu

dow

n C

urre

nt (P

A)

-40 -25 -10 5 20 35 50 65 80 95 110 1250

1

2

3

4

D003Ambient Temperature (°C)

Qui

esce

nt C

urre

nt (P

A)

-40 -25 -10 5 20 35 50 65 80 95 110 1250

5

10

15

20

25

30

35

D004

IOUT = 1 mAIOUT = 100 mA

Output Current (mA)

Qui

esce

nt C

urre

nt (P

A)

0 50 100 150 200 250 300 350 400 450 5000

10

20

30

40

50

60

70

80

90

100

110

120

D001

-40qC25qC125qC

Input Voltage (V)

Qui

esce

nt C

urre

nt (P

A)

0 5 10 15 20 25 30 35 400

50

100

150

200

250

300

350

400

D002

IOUT = 1 mAIOUT = 100 mAIOUT = 200 mA

10




6.7 Typical CharacteristicsVIN = 14 V, VEN ≥ 2 V, TJ = –40°C to +150°C (unless otherwise noted)

Figure 1. Quiescent Current vs Output Current Figure 2. Quiescent Current vs Input Voltage

Figure 3. Shutdown Current vs Ambient Temperature Figure 4. Quiescent Current vs Ambient Temperature

Figure 5. Dropout Voltage vs Output Current

IOUT = 200 mA

Figure 6. Dropout Voltage vs Ambient Temperature


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Input Voltage (V)

Line

Reg

ulat

ion

(%)

0 5 10 15 20 25 30 35 40-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

D011

-40qC25qC125qC

Frequency (Hz)

PS

RR

(dB

)

0

20

40

60

80

100

120

10 100 1k 10k 100k 1M 10M

D012


Cur

rent

Lim

it (m

A)

-40 -25 -10 5 20 35 50 65 80 95 110 125500

600

700

800

900

D009Output Current (mA)

Load

Reg

ulat

ion

(%)

0 100 200 300 400 500-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

D010

-40qC25qC125qC


Out

put V

olta

ge (

V)

-40 -25 -10 5 20 35 50 65 80 95 110 1254.94

4.97

5

5.03

5.06

D007Input Voltage (V)

Out

put V

olta

ge (

V)

0 5 10 15 20 25 30 35 400

1

2

3

4

5

6

D008

-40qC25qC125qC

11




Typical Characteristics (continued)VIN = 14 V, VEN ≥ 2 V, TJ = –40°C to +150°C (unless otherwise noted)

VOUT = 5 V

Figure 7. Output Voltage vs Ambient Temperature

VOUT = 5 V

Figure 8. Output Voltage vs Input Voltage

VIN = 5.6 V

Figure 9. Output Current Limit (ILIM) vs AmbientTemperature

Figure 10. Load Regulation

Figure 11. Line Regulation

COUT = 10 μF IOUT = 1 mA TA = 25°C

Figure 12. PSRR vs Frequency


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V (5 V/div)IN

V (1 V/div)OUT

V (50 mV/div)OUT(AC)

I (200 mA/div)OUT

V (5 V/div)IN

V (1 V/div)OUT


I (200 mA/div)OUT

VOUT (1 V/div)

VIN (10 V/div)

VOUT(AC) (100 mV/div)

IOUT (10 mA/div)

V (10 V/div)IN

V (1 V/div)OUT


I (10 mA/div)OUT

Frequency (Hz)

PS

RR

(dB

)

0

20

40

60

80

100

120

10 100 1k 10k 100k 1M 10M

D013 ESR (W)

Outp

ut C

apacitance

(µF

)

1

4.7

10

100

500

1k

0.001 0.01 0.1 1 10 20

D014

table RegionS

Unstable Region

table RegionUns

12





COUT = 10 μF IOUT = 100 mA TA = 25°C

Figure 13. PSRR vs Frequency Figure 14. ESR Stability vs Output Capacitance

VIN = 6 V to 40 V VOUT = 5 V COUT = 10 µFIOUT = 1 mA

Figure 15. Line Transient








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V (5 V/div)IN

V (1 V/div)OUT

I (200 mA/div)OUT


V (5 V/div)IN

V (1 V/div)OUT

I (200 mA/div)OUT


13





VOUT = 5 V COUT = 10 µF IOUT = 1 mA to 200 mA

Figure 19. Load Transient

VOUT = 5 V COUT = 10 µF IOUT = 200 mA to 1 mA

Figure 20. Load Transient


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IN

FSEL

Vref

OvercurrentProtection

OUT

DELAY

EN

PG

V(PG_REF )

PGADJ

WDO

ROSC

WD

WD_EN

VREG

WTS

RegulatorControl

ThermalShutdown

UndervoltageLockout

Band Gap

Power-Good

Control With

Delay

WatchdogOscillator

CurrentRegulator

Timer

WatchdogFault Control

VBAT

WRS

ErrorAmp

Amp

GND

MCU I/O

Digital I/O

14




7 Detailed Description

7.1 OverviewThe TPS7B68-Q1 is a 500-mA, 40-V monolithic low-dropout linear voltage regulator with integrated watchdogand adjustable power-good threshold functionality. This voltage regulator consumes only 19-µA quiescent currentin light-load applications. Because of the adjustable power-good delay (also called power-on-reset delay) and theadjustable power-good threshold, this device is well-suited as power supplies for microprocessors andmicrocontrollers in automotive applications.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Device Enable (EN)The EN pin is a high-voltage-tolerant pin. High input activates the devices and turns the regulators ON. Connectthis input pin to an external microcontroller or a digital control circuit to enable and disable the devices, orconnect to the IN pin for self-bias applications.


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DELAY(DLY)

C 1 Vt

5 A

´=

m

V(PG_REF)

PGADJ

Power-Good

Control

Amp

PG

OUT

DELAY

VREGAdjustable Power-

Good Threshold

R1

R2

PG _ ADJ falling PGADJ_ TH falling

PG _ ADJ risng PGADJ_ TH falling

R1 R2V V

R2R1 R2

V V 26 mV typR2

u

ª º u¬ ¼

15




Feature Description (continued)7.3.2 Adjustable Power-Good Threshold (PG, PGADJ)The PG pin is an open-drain output with an external pullup resistor to the regulated supply, and the PGADJ pin isa power-good threshold adjustment pin. Connecting the PGADJ pin to GND sets the power-good threshold valueto the default, V(PG_TH) rising. When VOUT exceeds the default power-good threshold, the PG output turns high afterthe power-good delay period has expired. When VOUT falls below V(PG_TH) rising – V(PG_HYST), the PG output turnslow after a short deglitch time.

The power-good threshold is also adjustable from 1.1 V to 5 V with external resistor divider between PGADJ andOUT. The threshold can be calculated using Equation 1:

where• V(PG_ADJ) rising, V(PG_ADJ) falling is the adjustable power-good threshold• V(PGADJ_TH) falling is the internal comparator reference voltage of the PGADJ pin, 1.1 V typical, 3% accuracy

specified under all conditions (1)

By setting the power-good threshold V(PG_ADJ) rising, when VOUT exceeds this threshold, the PG output turns highafter the power-good delay period has expired. When VOUT falls below V(PG_ADJ) falling, the PG output turns lowafter a short deglitch time.

Figure 21. Adjustable Power Good Threshold

7.3.3 Adjustable Power-Good Delay Timer (DELAY)The power-good delay period is a function of the value set by an external capacitor on the DELAY pin beforeturning the PG pin high. Connecting an external capacitor from this pin to GND sets the power-good delayperiod. The constant current charges an external capacitor until the voltage exceeds a threshold to trip aninternal comparator, and Equation 2 determines the power-good delay period:

where• t(DLY) is the adjustable power-good delay period• CDELAY is the value of the power-good delay capacitor (2)


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VIN

PG

V(PG_TH) falling

(PG_ADJ) fallingV

V(PG_TH) rising

V(PG_ADJ) rising

t < t(DEGLITCH)

t(DEGLITCH) t(DEGLITCH)

DELAY

t(DLY )

Input Voltage Drop UndervoltagePower Up Power Down

V(UVLO)

V(PG_HYST)

VOUT

t(DLY )

V(DLY _TH)

16




Feature Description (continued)

NOTE: V(PG_TH) falling = V(PG_TH) rising – V(PG_HYST).

Figure 22. Power Up and Conditions for Activation of Power Good

If the DELAY pin is open, the default delay time is t(DLY_FIX).

7.3.4 Undervoltage ShutdownThis device has an integrated undervoltage lockout (UVLO) circuit to shut down the output if the input voltagefalls below an internal UVLO threshold, V(UVLO). This ensures that the regulator does not latch into an unknownstate during low input-voltage conditions. If the input voltage has a negative transient which drops below theUVLO threshold and recovers, the regulator shuts down and powers up with a normal power-up sequence whenthe input voltage is above the required levels.

7.3.5 Current LimitThis device features current-limit protection to keep the device in a safe operating area when an overload oroutput short-to-ground condition occurs. This protects the device from excessive power dissipation. For example,during a short-circuit condition on the output, fault protection limits the current through the pass element to I(LIM)to protect the device from excessive power dissipation.

7.3.6 Thermal ShutdownThis device incorporates a thermal shutdown (TSD) circuit as a protection from overheating. For continuousnormal operation, the junction temperature should not exceed the thermal shutdown trip point. The junctiontemperature exceeding the TSD trip point causes the output to turn off. When the junction temperature fallsbelow the T(SD) – T(HYST), the output turns on again.

7.3.7 Integrated WatchdogThis device has an integrated watchdog with fault (WDO) output option. Both window watchdog and standardwatchdog are available in one device. The watchdog operation, service fault conditions, and differences betweenwindow watchdog and standard watchdog are described as follows.


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17




Feature Description (continued)7.3.7.1 Window Watchdog (WTS, ROSC, FSEL and WRS)This device works in the window watchdog mode when the watchdog type selection (WTS) pin is connected to ato low voltage level. The user can set the duration of the watchdog window by connecting an external resistor(RROSC) to ground at the ROSC pin and setting the voltage level at the FSEL pin. The current through the RROSCresistor sets the clock frequency of the internal oscillator. The user can adjust the duration of the watchdogwindow (the watchdog timer period) by changing the resistor value. A high voltage level at the FSEL pin sets thewatchdog window duration to 5 times as long as that of a low voltage level with same external componentconfiguration.

The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillatorfrequency, as shown by the following equations:

FSEL low t(WD) = RROSC × 0.5 × 10-6 (3)

FSEL high t(WD) = RROSC × 2.5 × 10-6 (4)

Watchdog initialization t(WD_INI) = 8 × t(WD) (5)

Open and closed windows t(WD) = t(OW) + t(CW) (6)

WRS low t(OW) = t(CW) = 50% × t(WD) (7)

WRS high t(OW) = 8 × t(CW) = (8 / 9) × t(WD) (8)

where:• t(WD) is the duration of the watchdog window• RROSC is the resistor connected at the ROSC pin• t(WD_INI) is the duration of the watchdog initialization• t(OW) is the duration of the open watchdog window• t(CW) is the duration of the closed watchdog window

For all the foregoing items, the unit of resistance is Ω and the unit of time is s.

Table 1 illustrates several periods of watchdog window with typical conditions.

Table 1. Several Typical Periods of Watchdog WindowFSEL R(ROSC) (kΩ) I(ROSC) (µA) t(WD) (ms) WATCHDOG PERIOD

TOLERANCE

High

200 5 500 15%100 10 250

10%50 20 12540 25 10025 40 62.520 50 50

Low

100 10 50

10%50 20 2540 25 2025 40 12.520 50 10

As shown in Figure 23, each watchdog window consists of an open window and a closed window. While thewindow ratio selection (WRS) pin is low, each open window (t(OW)) and closed window (t(CW)) having a widthapproximately 50% of the watchdog window (t(WD)). While the WRS pin is high, the ratio between open windowand closed window is about 8:1. However, there is an exception to this; the first open window after watchdoginitialization (t(WD_INI)) is eight times the duration of the watchdog window. The watchdog must receive the servicesignal (by software, external microcontroller, and so forth) during this initialization open window.


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(WD _HOLD) (WD)t 20% t= ´

t(WD_INI) t(WD)

8 t´ (WD)

CW

WRS = Low

WRS = High

Event Causing

Watchdog Initialization

8 t´ (WD)

Open WindowAfter Watchdog Initialization

(Must Be Serviced to Prevent Fault)

Open WindowAfter Watchdog Initialization

(Must Be Serviced to Prevent Fault)

Closed Window(Must Not Be Serviced

to Prevent Fault)

Closed Window(Must Not Be Serviced

to Prevent Fault)

Open Window(Must Be Servicedto Prevent Fault)

Open Window(Must Be Servicedto Prevent Fault)

t = ½ t(CW) (WD)´ t = ½ t(OW) (WD)´

t = 8 / 9 t(OW) (WD)´

t = 1 / 9 t(CW) (WD)´

18




A watchdog fault occurs when servicing the watchdog during a closed window, or not servicing during an openwindow.

Figure 23. Watchdog Initialization, Open Window and Closed Window

7.3.7.2 Standard Watchdog (WTS, ROSC and FSEL)This device works in the standard watchdog mode when the watchdog type selection (WTS) pin is connected toa high voltage level. The same as in window watchdog mode, the user can set the duration of the watchdogwindow by adjusting the external resistor (RROSC) value at the ROSC pin and setting the voltage level at theFSEL pin. The current through the RROSC resistor sets the clock frequency of the internal oscillator. The user canadjust the duration of the watchdog window (the watchdog timer period) by changing the resistor value. A highvoltage level at the FSEL pin sets the watchdog window duration to 5 times as long as that of a low voltage levelwith same external component configuration.

The duration of the watchdog window and the duration of the fault output are multiples of the internal oscillatorfrequency as shown by the following equations:

FSEL low t(WD) = RROSC × 0.5 × 10-6 (9)

FSEL high t(WD) = RROSC × 2.5 × 10-6 (10)

Watchdog initialization t(WD_INI) = 8 × t(WD) (11)

where:• t(WD) is the duration of the watchdog window• RROSC is the resistor connected at the ROSC pin• t(WD_INI) is the duration of the watchdog initialization

For all the foregoing items, the unit of resistance is Ω and the unit of time is s

Compared with window watchdog, there is no closed window in standard watchdog mode. The standardwatchdog receives a service signal at any time within the watchdog window. The watchdog fault occurs when notservicing watchdog during the watchdog window.

7.3.7.3 Watchdog Service Signal and Watchdog Fault Outputs (WD and WDO)The correct watchdog service signal (WD) must stay high for at least 100 µs. The WDO pin is the fault outputterminal and is tied high through a pullup resistor to a regulated output supply. When a watchdog fault occurs,the device momentarily pulls WDO low for a duration of t(WD_HOLD).

(12)


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19




7.3.7.4 ROSC Status Detection (ROSC)When a watchdog function is enabled, if the ROSC pin is shorted to GND or open, the watchdog output (WDO)pin remains low, indicating a fault status. If watchdog function is disabled, ROSC pin status detection does notwork.

7.3.7.5 Watchdog Enable (PG and WD_EN)When PG (power good) is high, an external microcontroller or a digital circuit can apply a high or low logic signalto the WD_EN pin to disable or enable the watchdog. A low input to this pin turns the watchdog on, and a highinput turns the watchdog off. If PG is low, the watchdog is disabled and the watchdog-fault output (WDO) pinstays in the high-impedance state.

7.3.7.6 Watchdog InitializationOn power up and during normal operation, the watchdog initializes under the conditions shown in Table 2.

Table 2. Conditions for Watchdog InitializationEDGE WHAT CAUSES THE WATCHDOG TO INITIALIZE

↑ Rising edge of PG (power good) while the watchdog is in the enabled state, for example,during soft power up

↓ Falling edge of WD_EN while PG is already high, for example, when the microprocessorenables the watchdog after the device is powered up

↑ Rising edge of WDO while PG is already high and the watchdog is in the enabled state, forexample, right after a closed window is serviced

7.3.7.7 Window Watchdog Operation (WTS = Low)The window watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is withincertain ranges. A watchdog low-voltage fault is reported when the frequency of the watchdog service signal is outof the setting range. Figure 24 shows the window watchdog initialization and operation for the TPS7B68-Q1(WRS is low). After the output voltage is in regulation and PG is high, the window watchdog becomes enabledwhen an external signal pulls WD_EN (the watchdog enable pin) low. This causes the watchdog to initialize andwait for a service signal during the first initialization window for 8 times the duration of t(WD). A service signalapplied to the WD pin during the initialization open window resets the watchdog counter and a closed windowstarts. To prevent a fault condition from occurring, watchdog service must not occur during the closed window.Watchdog service must occur during the following open window to prevent a fault condition from occurring. Thefault output (WDO), externally pulled up to VOUT (typical), stays high as long as the watchdog receives a properservice signal and there is no other fault condition.


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t(DLY)

VIN

VOUT

DELAY

PG

WD_EN

WDO

WD

WatchdogWindow Status

NAOW

WD InitializationCW CW

OWWD Initial-

izationCW

OWWD Ini-

tializationNA

OW

WD

Initialization

N

A

OW

WD

Initial...

<8 t(WD)

OW

WD Initialization

Fault 1

OW

Fault 2 Fault 3

t(DEGLITCH)

OW

t / 2(WD)

<t

/2

(WD

)

<8 t(WD) t(WD) / 2 t(WD) / 2 <8 t(WD) 8 t(WD) <8 t(WD)

20% t´ (WD)20% t´ (WD) 20% t´ (WD)

FLT

FLT

FLT

V(DLY_TH)

V(PG_TH) rising

V(PG_ADJ) rising

V

V(PG_TH) falling

(PG_ADJ) falling

)

t(DLY)

Normal Operation

<t

/2

(WD

)

20




NOTE: V(PG_TH) rising = V(PG_TH) falling + V(PG_HYST).

Figure 24. Window Watchdog Operation

Three different fault conditions occur in Figure 24:• Fault 1: The watchdog service signal is received during the closed window. The WDO is triggered one time,

receiving a WD rising edge during the closed window.• Fault 2: The watchdog service signal is not received during the open window. WDO is triggered after the

maximum open-window duration t(WD) / 2.• Fault 3: The watchdog service signal is not received during the WD initialization. WDO is triggered after the

maximum initialization window duration 8 × t(WD).

7.3.7.8 Standard Watchdog Operation (WTS = High)The standard watchdog is able to monitor whether the frequency of the watchdog service signal (WD) is lowerthan a certain value. A watchdog low-voltage fault is reported when the frequency of the watchdog service signalis lower than the set value.

Figure 25 shows the standard watchdog initialization and operation for the TPS7B68-Q1. Similar to the windowwatchdog, after output the voltage is in regulation and PG asserts high, the standard watchdog becomes enabledwhen an external signal pulls WD_EN low. This causes the standard watchdog to initialize and wait for a servicesignal during the first initialization window for 8 times the duration of t(WD). A service signal applied to the WD pinduring the first open window resets the watchdog counter and another open window starts. To prevent a faultcondition from occurring, watchdog service must occur during the every open window to prevent a fault conditionfrom occurring. The fault output (WDO), externally pulled up to VOUT (typical), stays high as long as the watchdogreceives proper service and there is not fault condition.


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Fault 1 Fault 2

VIN

VOUT

DELAY

PG

WD_EN

WDO

WD

WatchdogWindow Status

NAOW

WD Initialization

OWWD Ini-

tializationNA

OW

WD

Initialization

N

A

OW

WD

Initial...

OW

WD InitializationOW

FLT

FLT

OWOWOWOWOWOW

V(PG_TH) rising

V(PG_ADJ) rising

V

V(PG_TH) falling

(PG_ADJ) fallingV(DLY_TH)

t(DLY)

t(DLY)

t(DEGLITCH)

Normal Operation

<8 t(WD) <8 t(WD) 8 t(WD) <8 t(WD)<t(WD) <t(WD)

<t (

WD

)

<t(WD) <t(WD) <t(WD) <t(WD)

20% t´ (WD) 20% t´ (WD)

21




NOTE: V(PG_TH) rising = V(PG_TH) falling + V(PG_HYST).

Figure 25. Standard Watchdog Operation

Two different fault conditions occur in Figure 25:• Fault 1: The watchdog service signal is not received during the open window. WDO is triggered after the

maximum open-window duration t(WD) / 2.• Fault 2: The watchdog service signal is not received during the WD initialization. WDO is triggered after the

maximum initialization window duration 8 × t(WD).

7.4 Device Functional Modes

7.4.1 Operation With Input Voltage Lower Than 4 VThe device normally operates with input voltages above 4 V. The device can also operate at lower inputvoltages; the maximum UVLO voltage is 2.6 V. At input voltages below the actual UVLO voltage, the device doesnot operate.

7.4.2 Operation With Input Voltage Higher Than 4 VWhen the input voltage is greater than 4 V, if the input voltage is higher than the output set value plus the devicedropout voltage, then the output voltage is equal to the set value. Otherwise, the output voltage is equal to theinput voltage minus the dropout voltage.


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MCU

Supply

OUTIN TPS7B6833-Q1

or

TPS7B6850-Q1

PGADJ

EN

DELAY

WDO

WRS

ROSC

WD

PG

WD_EN

WTS

FSEL

MCU

Reset

MCU

I/O

Battery

Digital

I/O

MCU

I/O

GND

22




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe TPS7B68-Q1 device is a 500-mA low-dropout watchdog linear regulator with ultralow quiescent current. ThePSpice transient model is available for download on the product folder and can be used to evaluate the basicfunction of the device.

8.2 Typical ApplicationFigure 26 shows a typical application circuit for the TPS7B68-Q1. Different values of external components can beused, depending on the end application. An application may require a larger output capacitor during fast loadsteps to prevent a large drop on the output voltage. TI recommends using a low-ESR ceramic capacitor with adielectric of type X7R.

Figure 26. TPS7B68-Q1 Typical Application Schematic


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23




Typical Application (continued)8.2.1 Design RequirementsFor this design example, use the parameters listed in Table 3.

Table 3. Design ParametersDESIGN PARAMETER EXAMPLE VALUES

Input voltage range 4 V to 40 V for TPS7B6833-Q15.6 V to 40 V for TPS7B6850-Q1

Input capacitor range 10 μF to 22 μFOutput voltage 3.3 V, 5 VOutput current rating 500 mA maximumOutput capacitor range 4.7 μF to 500 μFPower-good threshold Adjustable or fixedPower-good delay capacitor 100 pF to 100 nFWatchdog type Standard watchdog or window watchdogWatchdog window periods 10 ms to 500 ms

8.2.2 Detailed Design ProcedureTo begin the design process, determine the following:• Input voltage range• Output voltage• Output current• Power-good threshold• Power-good delay capacitor• Watchdog type• Watchdog window period

8.2.2.1 Input CapacitorWhen using a TPS7B68-Q1 device, TI recommends adding a 10-μF to 22-μF capacitor with a 0.1 μF ceramicbypass capacitor in parallel at the input to keep the input voltage stable. The voltage rating must be greater thanthe maximum input voltage.

8.2.2.2 Output CapacitorEnsuring the stability of the TPS7B68-Q1 requires an output capacitor with a value in the range from 4.7 μF to500 μF and with an ESR range from 0.001 Ω to 20 Ω. TI recommends selecting a ceramic capacitor with lowESR to improve the load transient response.

8.2.2.3 Power-Good ThresholdThe power-good threshold is set by connecting PGADJ to GND or to a resistor divider from OUT to GND. TheAdjustable Power-Good Threshold (PG, PGADJ) section provides the method for setup the power-goodthreshold.

8.2.2.4 Power-Good Delay PeriodThe power-good delay period is set by an external capacitor (CDELAY) to ground, with a typical capacitor valuefrom 100 pF to 100 nF. Calculate the correct capacitance for the application using Equation 2.

8.2.2.5 Watchdog SetupThe Integrated Watchdog section discusses the watchdog type selection and watchdog window-period setupmethod.


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VIN (5 V/div)

VOUT (2 V/div)

VPG (2 V/div)

I (10 mA/div)OUT

WD Signal (5 V/div)

VOUT (5 V/div)

I (10 mA/div)OUT

WDO Signal (5 V/div)

24




8.2.3 Application Curves

Figure 27. TPS7B6850-Q1 Power-Up Waveform Figure 28. TPS7B6850-Q1 Watchdog Fault (HighFrequency Watchdog Service Signal)


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IN 1

NC

NC

EN

FSEL

WTS

NC

GND

NC

NC

ROSC

DELAY

WD

NC

OUT

NC

NC

PGADJ

PG

NC

NC

GND

NC

NC

WRS

NC

WD_EN

WDO

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ThermalPad

25




9 Power Supply RecommendationsThe device is designed to operate from an input-voltage supply range from 4 V to 40 V. This input supply mustbe well regulated. If the input supply is located more than a few inches from the TPS7B68-Q1 device, TIrecommends adding a capacitor with a value of ≥10 μF with a 0.1 μF ceramic bypass capacitor in parallel at theinput.

10 Layout

10.1 Layout GuidelinesFor LDO power supplies, especially high-voltage and high-current ones, layout is an important step. If layout isnot carefully designed, the regulator could not deliver enough output current because of thermal limitation. Toimprove the thermal performance of the device and maximize the current output at high ambient temperature, TIrecommends spreading the thermal pad as much as possible and put enough thermal vias on the thermal pad.Figure 29 shows an example layout.

10.2 Layout Example

Figure 29. Layout Recommendation


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26




11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related DocumentationFor related documentation see the following:

Texas Instruments, TPS7B68-Q1 Evaluation module user's guide

11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

11.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.4 TrademarksPowerPAD, E2E are trademarks of Texas Instruments.All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge CautionThis integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the most-current data available for the designated devices. This data is subject to change without notice and withoutrevision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.


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http://www.ti.com/lit/pdf/SLVUAV0

http://www.ti.com/corp/docs/legal/termsofuse.shtml

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http://support.ti.com/

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS7B6833QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 7B6833Q

TPS7B6850QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 7B6850Q

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS7B6833QPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

TPS7B6850QPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS7B6833QPWPRQ1 HTSSOP PWP 28 2000 350.0 350.0 43.0

TPS7B6850QPWPRQ1 HTSSOP PWP 28 2000 350.0 350.0 43.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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GENERIC PACKAGE VIEW

This image is a representation of the package family, actual package may vary.Refer to the product data sheet for package details.

TSSOP - 1.2 mm max heightTMPowerPADPWP 28SMALL OUTLINE PACKAGE4.4 x 9.7, 0.65 mm pitch

4224765/B

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PACKAGE OUTLINE

C

26X 0.65

2X8.45

28X 0.300.19

TYP6.66.2

0.150.05

0.25GAGE PLANE

-80

1.2 MAX

2X 0.95 MAXNOTE 5

2X 0.2 MAXNOTE 5

5.184.48

3.12.4

B 4.54.3

A

NOTE 3

9.89.6

0.750.50

(0.15) TYP

PowerPAD TSSOP - 1.2 mm max heightPWP0028CSMALL OUTLINE PACKAGE

4223582/A 03/2017

1

1415

28

0.1 C A B

PIN 1 INDEXAREA

SEE DETAIL A

0.1 C

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153.5. Features may differ or may not be present.

SEATINGPLANE

TM

PowerPAD is a trademark of Texas Instruments.

A 20DETAIL ATYPICAL

SCALE 2.000

THERMALPAD

1

14 15

28

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EXAMPLE BOARD LAYOUT

0.05 MAXALL AROUND

0.05 MINALL AROUND

28X (1.5)

28X (0.45)

26X (0.65)

(5.8)

(R0.05) TYP

(3.4)NOTE 9

(9.7)NOTE 9

(1.2) TYP

(0.6)

(1.2) TYP

( 0.2) TYPVIA

(3.1)

(5.18)


4223582/A 03/2017

NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement.10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

TM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE: 8X

SYMM

SYMM

1

14 15

28

METAL COVEREDBY SOLDER MASK

SOLDER MASKDEFINED PAD

SEE DETAILS

15.000

METALSOLDER MASKOPENING

METAL UNDERSOLDER MASK

SOLDER MASKOPENING

EXPOSED METALEXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASKDEFINED

(PREFERRED)

SOLDER MASKDEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

28X (1.5)

28X (0.45)

26X (0.65)

(5.8)

(R0.05) TYP

(5.18)BASED ON

0.125 THICKSTENCIL

(3.1)BASED ON

0.125 THICKSTENCIL


4223582/A 03/2017

2.62 X 4.380.1752.83 X 4.730.15

3.10 X 5.18 (SHOWN)0.1253.47 X 5.790.1

SOLDER STENCILOPENING

STENCILTHICKNESS

NOTES: (continued) 11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 12. Board assembly site may have different recommendations for stencil design.

TM

SOLDER PASTE EXAMPLEBASED ON 0.125 mm THICK STENCIL

SCALE: 8X

SYMM

SYMM

1

14 15

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METAL COVEREDBY SOLDER MASK

SEE TABLE FORDIFFERENT OPENINGSFOR OTHER STENCILTHICKNESSES

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