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©Synopsys 2013 1
Top Tips for Successful
Low Power Verification
©Synopsys 2013 2
The Challenge
• While simple in concept, UPF is verbose with many
opportunities for errors in specification:
– List of elements for protection strategies
Several thousands of pins
– Explicit connection of macro cell supplies
(Hundreds of macros) * (2 to 5 supply pins each)
– PST complexity is ~2(number of supplies)
Can quickly reach hundreds of thousands of states
• Total complexity is greater than the sum of power and
design intent
– Power behaviour can interfere with or modify design behaviour
©Synopsys 2013 3
Traditional vs. Low Power Verification Methodology
Design
Spec
Specification
Power
Spec
Verify
Design
Intent
Verification Plan
Verify
Power
Intent
Design
Intent
RTL
Power
Intent
UPF
Simulation
+
Static
Checks
• MV Static checks – Power structure/strategy
checks
• Voltage-aware Testbench – Power control – Assertions and monitors – Coverage
• Voltage-aware Debug – State visualization – UPF/strategy viewing – Power scope viewing – View power state
corruption
©Synopsys 2013 5
Functional
Verification
Static Verification
Verify at All Stages of the Flow
MV-Aware
Simulation
Implementation
UPF
RTL
UPF’
Gate
UPF”
Gate
Gate
(PG)
Synthesis
Physical
Implementation
Sign-Off
Analysis
Static Timing &
Power Analysis
Rail Analysis
MV Static
Checking
UPF-Enabled
Equiv Checking
©Synopsys 2013 6
Plan for Success
1. Analyse the power specification
2. What are the power domains?
3. What type of power elements need to be verified?
4. Identify potential failure mechanisms and how they will
be detected?
5. Consider how design intent interacts with power intent.
©Synopsys 2013 7
Testing Best Practices
• Clearly understand the power intent defined
• Ensure static MV checking is clean, and PST is golden
• Include power verification as a component in your verification planning
• Start simple, then build up to complete LP testing
©Synopsys 2013 8
Need for Power State Table Validation
• PST describes all valid combinations of
voltage values
• This information is used by implementation
tools to determine protection needs
• It is also used by static checkers, and
considered as GOLDEN!
• Only simulation (and proper testbench) can
validate the PST!
©Synopsys 2013 9
SV / CRT / LP Assertions
• More complex testbench may be used
– Randomize some of the Power Control
– Inject functional interrupts
– Create some user defined assertions
– Collect LP specific coverage data
©Synopsys 2013 10
Low Power Verification is a Challenge
• Adds another dimension of complexity to the verification task
– Verifying design and power intent both separately and how they interact
– PST Verification is important
• Incorporate low power into verification planning
• Consider both the correctness and completeness of the power intent
– Statically and Simulation
©Synopsys 2013 11
©Synopsys 2013 12
UPF Verification – Sample of User Papers • Architecting Power Awareness in a Constrained Random OVM Testbench
• Low-Power Verification using Power State Table Coverage
• TB4-A Challenges with Design and Verification of State Retention in a Complex Low-
Power SoC
• Using Formal Equivalence Verification Tool Efficiently on a UPF Design
• Can You Tell Your ISO from LS? – A Methodology for Low Power Debug
• Benefits of Using MVSIMV-NLP for Low Power Verification
• Signoff Static Low Power Verification on Large Design using MVRC
• Method for Reusable Low Power Mode Entry/Exit Verification Applied on Freescale
S12 uC
• UPF Power State Table Verification Methodology using MVSIM
• Low Power Verification with MVRC on a Hierarchical UPF Design
• Power Intent Specification Creation and Verification for Multi-Rail Cells using
LEDA/MVSIM
• Multi-Rail Hard Macro Modeling for Accurate Power Aware Simulation using MVSIM
• MVRC Usage on a Complex Design from the RTL to the Low Power Signoff
UPF Tutorials are also available
©Synopsys 2013 13
Thank You