Advances in Low-Power VerificationVerification

Janick BergeronSynopsys Fellowy p y

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The Era Of The ConsumerHouseholds are the Semiconductor Industry’s #1 CustomerHouseholds are the Semiconductor Industry s #1 Customer

A very different profile of energy usage

2Source: J.-H. Huang, SIA 2004

than before

What do consumers want?

High Performance, Multi-media experienceANDAND

Lowest Active Power,Zero Idle Power

This is for the System not just for eachThis is for the System, not just for each individual IC

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Most Systems are amenable to Energy Efficient DesignEfficient Design

Lowest Active Power Principle:Apply the Lowest Possible VDD to each functional block

t h i t t f tiat each instant of time

• Systems/ICs don’t have the same performance needs all the timetime

– Operating at worst case design corner all the time is wastage

• Systems/ICs don’t need all the functions to be running all the• Systems/ICs don t need all the functions to be running all the time

– Operating all the devices all the time is wasteful

Zero Idle Power Principle:Turn on a block only when needed

Turn it off once it is not needed

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Turn it off once it is not needed

What can IC designers do?

• Lowest Active PowerClock Gating Device Sizing (old)– Clock Gating, Device Sizing (old)

– Multi-VDD (Spatial Voltage Control)DVFS T l V lt C t l)– DVFS Temporal Voltage Control)

• Zero Idle Power– Multi-Vt (old)– Power Gating/Retention– Low VDD Standby, Back BiasWe still have to deal with the System

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yHW and SW need to work together

Enter, the PMU

CPUSoftware

SOCBlock

Power switchesIsolation cellsLevel ShiftersSave/restores

PMUVRPower switchesI l ti ll

POR Logic

ButtonPress

Isolation cellsLevel ShiftersSave/restores

Battery/Always On

Logic

OTPPinStraps

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Power Management Units will aggressively Control Voltage

We are no longer testing ASICs on the tester SOCs need to work in SystemSOCs need to work in System

Design Design

Verification Verification of Firmware especially

Tape-Out

S t /B d l l b ild

Power Management

Tape-OutSystem/Board level builds

Fi t tiFirmware testing

Conventional Design-Debug Flow

SOC development flow

7

g

Power Management increases verification complexity enormouslycomplexity enormously

Tx/Rx inCPU in Display inDisplay in Tx/Rx inNormalMode

CPU in Normal Mode

Display in Normal Mode

1.0VV1 Display in Standby

Tx/Rx inStandby

Display in HP Mode

CPU in HP ModeCPU in Standby

Display in OFF Mode

with Power Switches

0.8VV2 Level Shifters Isolation Cells

Audio in NormalMode

Video in Normal Mode1.2VV3

PMUAudio in

OFF Mode with

Power Switches

Video in OFF Mode

withPower Switches

Phone Call PDA StandbyMultiple power states, transitions and

sequences must be verifiedVerification must now understand voltage

valuesCorrect implementation of LP specific design

elements must happen

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Phone Call PDA Standbysequences must be verified valueselements must happen

Mode State Space

Phone Mode

PDAMode

Stand-By

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Power State Space

Stdby

Normal HP

Off

Normal HP

Stdby

Normal

Stdby OffStdby

Normal NormalNormal

HP HP

Stdby Off

Normal Normal

Stdby Off

Normal Normal

Off

Normal

Off

Normal

Off Off

Normal Normal

Standby Mode

PhoneMode

PDAMode

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Mode Mode Mode

Power State Space

Stdby

Normal HP

Off

Normal HP

Stdby

Normal

Stdby

Normal NormalNormal

HP HP

Stdby Off

Normal NormalNormal Normal

Off

Normal

Off

Normal

Off Off

Normal Normal

PhoneMode

PDAMode

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ModeMode

Power State Transitions

High Perf. High Perf.High Perf. High Perf.

Normal VDD=3.3V Normal VDD=3.3VVDD=3.3V VDD=3.3V

RestoreSave RestoreSaveRestore Restore

VDD=1.5VVDD=0.7V VDD=1.5VVDD=0.7VVDD=1.5V VDD=1.5V

Stand-By Stand-ByStand-By Stand-By

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Power Management brings new bug types!types!

– Isolation/Level Shifting Bugs– Control Sequencing bugs– Retention scheme/control errors– Retention selection errors– Electrical Problems like memory corruptionElectrical Problems like memory corruption– Power Sequencing/Voltage Scheduling errors– Hardware-Software deadlock

Power Gating collapse/dysfunction– Power Gating collapse/dysfunction– Power On Reset/bring up problems– Thermal runaway/ Overheating– …

Th t t diti l f ti l b !

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These are not traditional functional bugs!

Multi-VDD stretches boolean logic

ATraditional Boolean Analysis

V1

V3

Voltage-aware Boolean Analysis

AA

BO

V1 V2 V3 A B O

V1

V2 BO

A B O

0 0 0

… … …

V1 V2 V3 A B O0 0 0

… … …Impacts Simulation, Static

Analysis, Equivalence 1 1 1

… … …

1 1 1models

Unlearn Boolean Analysis you were taught in college!

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Voltage Aware Booleans?5.0 V

Voltage Aware Booleans?0 0

1 1 11

0.7 V 1.0 V

1 X X1

1.5 V0.7 V

1 1 11 1 X X1

0.8 V

1 1

Traditional simulators are not voltage aware

Voltage-aware simulators are electrically accurate

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RTL lacks many power semanticsmodule sio(din, dv, txd, txe, clk, rstn);

input [7:0] din;input dv; No Voutput txd, txe;input clk, rstn;

reg [2:0] idx;reg txd txe;

No VDDNo Vin

No Save/Restorecontrol signals

No Vout

reg txd, txe;always @ (posedge clk or negedge rstn)begin

if (!rstn) beginidx <= 0; No shutdown

Clock gating!

txe <= 1’b0;endelse if (dv) begin

txe <= 1’b1;txd <= din[idx]; No retentiontxd din[idx];idx <= idx + 1;

endelse idx <= 0;

endd d l

No retention

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endmodule

We have a fundamental semantics problem

• Spatial partitions for SOC blocks need to

problem

be specified• Temporal variations in voltage need

description• Interface definitions for each block• Shutdown, Back Bias, Standby behaviors

are not factored into traditional booleanmodels

• And then there is retention!

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Retention stretches language semantics• Retention : A balloon latch is used to retain state when power is

turned offW it l k ti f h td h d d l ith• Wait, we lack semantics for shutdown, how do we deal with this?

always @ (posedge clk ornegedge reset n or

always @ (posedge clk ornegedge reset_n)

if (!reset_n) q <= 0;else q <= d;

negedge reset_n orposedge save orposedge restore)

if (!vdd) q <= 1’bx;i ! 0else q <= d; else if (!reset_n) q <= 0;

else if (save) q_s <= q;else if (restore) q <= q_s;else q <= d;

Need to simulate and verify this!

Retention is a huge verification h ll

q ;

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challenge

Power-Aware Model

Required forfor

Static Analysis

PMUAnalysis,

Simulation,Timing

!

Timing Analysis, Formal !Formal

Analysis, etc

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etc..

But wait…

• Is it enough to provide the design tools?g p g– What about coverage, assertions, debug?

• Successful Verification takes rigorousSuccessful Verification takes rigorous methodology– How do we build a low power verification– How do we build a low power verification

methodology?– How do we migrate existing methodology?How do we migrate existing methodology?

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Verification Engineers need help/training

• Digesting technology shift and bug types• Evolving coding styles for low power

– RTL and UPF• Formulating/migrating test plans• Formulating/migrating test plans• Writing constrained-random tests for low-power• Measuring coverage• Measuring coverage• Writing and monitoring assertions• DebugDebug• Static Verification• Post Layout Netlist Verification

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y

Verification must now perform additional taskstasks

– Verify connection, placement, type of isolation/level shifting– Include new power intent files such as UPF

Formulate test plan for architecture correctly– Formulate test plan for architecture correctly– Reach good power state coverage– Verify design works in all states, transitions and sequences– Address firmware control of power managementAddress firmware control of power management– Address power-on reset issues– Address verification at each stage of design, not just RTL

• Verify netlist at each handoff• Verify Power Switch and rail connectivity

– Migrate existing testbenches, assertions, monitors to be low power aware

– Think about exhaustive constrained random and– Think about exhaustive constrained random and asynchronous logic testing

B ill ith t i th d l !

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Bugs will escape without a rigorous methodology!Synopsys Confidential

VMM – The technology of rigorous, reusable Verificationreusable Verification

Clear Guidelines Base Classes

463 Rules510 Recommendations383 Suggestions

Data modelsTransactorsVerification Environments383 Suggestions Verification Environments

Compliance Consistency

Utilities

Message Service

Pre-Defined Functions

AssertionsgNotification ServiceTransaction-Level Interface

Random GeneratorsApplication Packages

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Scalability Productivity

VMM - Components

Random GeneratorTests

ConstraintsDirected Stimulus

GeneratorTransaction-LevelInterface

Random Generator

Scoreboard

Tests

Tx Scoreboard

ScoreboardApplication

Transactor

DUT RxMasterRegisterAbstractionCfg

TransactorAbstraction

PerformanceHigh-LevelA li i

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AnalyzerApplications

VMM: Widely used since 2005

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VMM-LP: Industry’s First Verification Methodology for Low-PowerMethodology for Low Power

VMM - LP

Broad participation by LP experts to contribute and review

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VMM-LP Extends The Proven VMM MethodologyMethodology • VMM-LP Base Classes comprehend power shutdown, wakeup,

and retention semanticsand retention semantics

• Power State Manager.– Abstracts the power state machine(s)

Id tifi t t t ( )– Identifies current power state(s)– Notifications of transitions start/end– Can generate random power state transitions

• Power-aware Components

– Customization of power-on reset and power-up sequences

Partial timeline rollbacks– Partial timeline rollbacks

– HW/SW interaction to verify power management firmware

• Source code under Apache 2.0

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Source code under Apache 2.0

Low-Power DUT

PWRMGMT

LPDUT

BFMRTLDUT

BFM

CPU

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RAL C APII / T i i R

UnmodifiedInterrupt / Transition Requests

Low-PowerTests

VCSSV

Cosim APIFirmwareC Code

C

DPI

C

Register AbstractionralgenPure C API

DPI

RTL DUTSpecgcc

.o Embedded

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SW

VMM-LP Addresses The New Challenge

A

• Impact of LP verification

Bugs related to low power techniquesAwareness • Bugs related to low power techniques

• Documented examples from real designs

Verification

• LP perspective into planning

• LP-related assertions and coverage

• Modeling of LP devices such as VRM

LP b l d i f t t

Reuse• LP-aware base classes and infrastructure

• LP-aware methodology applications

• Best-practice rules and guidelines

Source code for

base class library

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library

Automated Assertion Technology is needed for power managementneeded for power management

• Assertions needed deep in the design/IP but SOC integrationdesign/IP , but SOC integration (power intent) changes the assertion

• Writing assertions manually is painful and error prone

Multi-voltage design

• Automated assertions is a reality today Needs Protocol specification RTL

LiVoltageI l d

Power St t

RTL A ti

Gate Level A ti

Example

– Can be used to check properties as well

Lines Islands States Assertions Assertions

6099 4 8 685 1891

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What about Standards?Adv. Verification

Automated Assertions

Universal formatInteroperable

Industry Std toolsAutomatic,

AssertionsFormal Property

Checks

P t l

InternalScripts

,Optimized Impl.

On/Off sim

Tcl BasedStructural

ProtocolBasedPowerIntent

Not PortableNot Verifiable

Proprietary formats

StructuralPower Intent

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Unified Power Format (UPF) Language

Open format for defining power intentpower intentUsed throughout flowAccellera UPF1.0 Industry-standardUPF proposed as IEEE-P1801Interoperable with multi-vendor supportIndustry-wide support

S ifi ti

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Specification

The Eclypse Low Power Solution

Des

ign

Inte

nt

DesignWare IP

Innovator

wer

Aw

are

erifi

catio

n VCS with MVSIM

MVRC

C

R S

The Perfect Alignment

Aw

are

enta

tion

Pow Ve

Design Compiler

HSIMRTL

U

SERVICES

Low Power Solution

oftechnology, IP, methodology,

services and industry t d d f

Pow

er A

Impl

eme

re

IC Compiler

DFT/DFM

Formality + MVRC

UPF

standards for Low Power Design

L P M th d lP

ower

Aw

arS

igno

ff

PrimeRail

Formality + MVRC

PrimeTime PX

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Low Power Methodology

Eclypse Low Power Education ProgramsComing SoonComing Soon…

• Advanced Verification with UPF– Hands-on workshop

We can work with A d i t• Low Power Curriculum

– Developed with Taiwan’s National Chip

Academia to develop Low

P C i lp p

Implementation Center (CIC)Power Curriculum

• Low Power Methodology Manual– Being translated into Chinese & Japanese

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Protocol Standards will emerge• ACPI, USB, PCI, PCIe have Power Management Specs• No SOC Power Management interface standard exists

Standards like PMBus are emerging and evolving– Standards like PMBus are emerging and evolving– A common Power Management Protocol/Interface will increase

interoperability of SOC IP

Main system

CPU

PMUsubsystemLocal

PMU

Hierarchical Power Management is on the riseIncreased Static(Formal) verification

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Increased Static(Formal) verification

The Great Unanswered Question

Th Chi kArchitecture The Chip works, but does it actually

Selection and Optimization has but does it actually

savep

always been the Holy Grail of EDA!save

power/energy?y

power/energy?

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Conclusions

Low power design impacts every stage of design and verificationdesign and verification

Verification of low power techniques is challenging and requires new verification technology and methodologytechnology and methodology

Synopsys is committed to delivering theSynopsys is committed to delivering the best low power design and verification solution in the market

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Predictable Success

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