United States Patent [191 Suzuki et a1.

llllllllllllllllllllllllllllllllllllllllllllllllllllIllllllllllllllllllllll USOO5123012A

Patent Number:

Date of Patent: 5,123,012

Jun. 16, 1992 [11]

[45]

[54] TIME DIVISION SWITCHING APPARATUS

[75] Inventors: Takamasa Suzuki; Takeshi Shimpuku; Takane Kakuno, all of Kanagawa, Japan

[73] Assignee: Mitsubishi Denki Kabushiki Kaisha, Tokyo, Japan

[21] Appl. No.: 532,711 [22] Filed: Jun. 4, 1990

[30] Foreign Application Priority Data Jun. 6, 1989 [JP] Japan ................................ .. 1-143291

Jul. 12, 1989 [JP] Japan ................................ .. l-318l32

Aug. 25, 1989 [JP] Japan ................................ .. 1-219839

[51] Int. Cl.5 ....... .. H04J 3/02 [52] US. 01. ................ ., .. 370/66; 370/68

[58] Field of Search ............................ .. 370/66, 67, 68

[56] References Cited U.S. PATENT DOCUMENTS

4,574,375 3/1986 Kemp et al. ........................ .. 370/67

Primary Examiner-Benedict V. Safourek Assistant Examiner-—Melvin Marcelo Attorney, Agent, or Firm--Rothwell, Figg, Ernst & Kurz

[57] ABSTRACT A time division switching apparatus for interchanging data between an input highway and an output highway includes a number of buffer memories each receiving the same data from the input highway in parallel, a control memory for controlling the addresses of the buffer memories into which the data is written, and for controlling the addresses of the buffer memories from which data is written, at speci?c time positions. The apparatus may include demultiplexing/multiplexing circuitry for converting serial data to parallel data for storing in the buffer memories and parallel data from the buffer memories to serial data to be sent to the out put highway. Data be interchanged according to spe ci?c data bit units or time slot units, wherein each time slot de?nes a speci?c number of data bits.

4,941,141 7/1990 Hayano .... .. 25 Claims, 18 Drawing Sheets

TIME SWITCH 1913 150 2? 210 111, 230 113, ~’ A, RIEETIPLEXING 8/ B BUFFE/ / ’ 15408 a) 1

cmcurr I H’ MEMOQY / SELECTOR ,' ' 1

200 { MULTIPLEXING 160 1 240b cmcun

114 190 ~22011,5 ? 1' ROL CONT COUNTER MEMORY 1

s “+9

TIME SWITCH

"401D

E l

g 2405 a i

“19

TIME SWITCH

180 i .e1o1h

1103

US. Patent June 16, 1992 Sheet 1 of 18 5,123,012

FIG. I (PRIOR ART)

150 III“ ‘I60 / > BUFFER / \

MEMORY I

190 H 170A “I 115 200 180/ I COUNTER N114 agmggL

- I100 _ '

F I G. 4 (PRIOR ART) 160/

100) 150/ TIME DIVISION

SWITCHING APPARATUS

A B a A

TRANSMISSION DEVICE

TRANSMISSION DEVICE

H081 I1082

US. Patent June 16, 1992 ~ Sheet 2 of 18 5,123,012

FIG. 2 (PRIOR ART)

180

170

[.llllll ll DATA ON INPUT HIGHWAY 150

FIG. 5 (PRIOR ART)

180

170

X X WA X X WA D

vi WA m X MIWM R vA X X X VwOL vw. D vB

X n TA R X X WA

T U P MW

0 0 N1. m m on

SW" mm DH

US. Patent

ll

June 16, 1992

Sheet 3 of 18 F IG. 5 1092

(PRIOR ART) 1603

- _._1—> gw?gr'l‘l’rlém EILEEQE-H psob APPARATUS 1601 5

H00 160n

F

F l 6- 6 (PRIOR ART)

8 X310)?

June 16, 1992 Sheet 6 of 18 5,123,012

F IG. 9

US. Patent

180

H W H e

l e

.1..-s-.,h.--.%.-1 ..... i Lax ...... -x

I 6 1 2 %

n T 9

I

.... iii ........ N we 0 m I g H m H n Mv|mw A BIIIIH llvm 1 s

H: llllm?l?lx ||||| lixlLllliVA |||||VLi IQU m f w w

US. Patent June 16, 1992 Sheet 9 of 18 5,123,012

AIQNPI

US. Patent June 16, 1992 Sheet 12 of 18 5,123,012

SOP) w.

A" \ ‘A V . cOmF

Alilulul 10:26 m2; comp "

n “

0-20 _ u _

2.0-‘?

10:26 m2; n \ A

ncwp 00m?

JVmmQEWQ mmhznoo BE A \ \ ~ A

mm:2 . av: @02 OFF

83 \ \ mONP

iv E052 _

A \ "653mm \ mwtam " \

\ l

@0923! $32 82 N2: ~09

US. Patent June 16, 1992 Sheet 13 of 18 5,123,012

F I G. 16

in"

170

180

Y PNAJSTW X X XMXMX X HIGHWAY 150a DATA ON INPUT HIGH

.KX AY 15Gb W

DATA ON X INPUT HIGHWAY 150n

110a

US. Patent June 16, 1992 Sheet 14 of 18 5,123,012

FIG.17

170

180

1102

120a

X XBNTLANX 7

Y X 1 )(BULANX DATA ON )( OUTPUT HIGHWAY 160a

US. Patent June 16, 1992 Sheet 15 of 18 5,123,012

'NPUT DEMULTI H'G‘HWA§ \ PLEXING N2

150 cIRcuIT

COUNTER ~114 822,

/~111a 1,18 F [2 ID 35:55‘, J‘ REGIsTER _

'f‘

/ SIELECTOR\ 7a 1131a \ I - REGISTER \g‘:

—~- 1 115a Z 2g CONTROL ) 12a 5% MEMORY

jab 111D 11b I

BUFFER '7 _> ‘:7 :{> MEMORY :[> REGISTER _

MULTI lh T :> PLEXING -—,—>

/§EI_EcToR\ 7b cIRcuIT / I— - -I

REGIsTER >23 9) 160 9 "'5

CONTROL 2b 5'!‘ I? _ MEMoRY -

I l l

I IIIII', 11h;

;; a‘é?ggy i) REGIsTER “3h 'I‘

SELECTOR

\ J—

REGIsTER

couTRoI. 112“ MEMORY

5,123,012 1

TIME DIVISION SWITCHING APPARATUS

BACKGROUND OF THE INVENTION

1. Field of the Invention The present invention relates to a time division

switching apparatus, and particularly to an improve ment in a time division switching apparatus which col lectively performs, for example, the interchange of a bit unit and that of a time slot unit, and especially carries out the interchange of digital data.

2. Description of the Prior Art FIG. 1 shows the construction of a time division

switching apparatus which performs a digital data ex change illustrated, for example, in FIG. 1.33 on page 43 of the technical magazine entitled “Simple Digital Data Exchange (Y asashii Digital Koukan)” published by Ohm Co., Ltd. In the same drawing, there are shown a time division switching apparatus 100, a counter 114, a control memory 115, a buffer memory 111, an input highway 150, an output highway 160, a reference pulse 170, a clock 180, a value 190 to be counted, which is used as an address to be inputted to each of the buffer memory 111 and the control memory 115, and an output 200 from the control memory 115, i.e., a control mem ory output. FIG. 2 is a timing chart for describing the operation

for writing data received from the input highway 150, i.e., on the input highway 150 into the buffer memory 111 provided in the time division switching apparatus 100 shown in FIG. 1. FIG. 3 is a timing chart for de scribing the operation for reading data from the buffer memory 111 to the output highway 160.

Referring to FIGS. 2 and 3, symbols t1, t2, . . . indicate time positions. A description will next be made on the operation of this apparatus. In FIG. 1, the counter 114 is reset by the reference pulse 170 which is periodically repeated. The counter 114 also serves to produce the counted value 190 in step-by-step operation based on the clock 180 until it is reset by the following reference pulse 170 so as to supply the same to the buffer memory 111 and the control memory 115. Then, the buffer mem ory 111 serves to write data on the input highway 150 into an address designated by the counted value 190, and the control memory 115 supplies the data, which have been written into the address designated by the counted value 190, as a control memory output 200, to the buffer memory 111. Further, the buffer memory 111 serves to read out data from an address designated by the control memory output 200 so as to supply the read data to the output highway 160. A description will now be made on the operation

timing referred to above. Referring to FIG. 2, data of A, B, C, D and E on the input highway 150 are written into a buffer memory in which #0, #1, #2, . . . constitut ing the counted value 190 as output values from the counter 114 are taken as addresses. Referring to FIG. 3, the counted value 190 from the counter 114 corre sponds to #0 at the time position t1. Then, the control memory 115 produces the count value #1, which has been written into an address #0, thereof, as the output 200. The buffer memory 111 produces data, which have been written into address #1, in response to the control memory output 200 as an address. Since data B have been written into an address #1 in the buffer memory 111, as shown in FIG. 2, the data B are outputted at the time position t1 in FIG. 3 where the reference pulse 170 shown in FIG. 3 is a pulse at a position delayed from the

2 reference pulse 170 shown in FIG. 3 by one cycle. Simi larly, the buffer memory 111 outputs data A, which have been written into an address #0, thereof, at the time position 12. Similarly, any one of data is also out putted at the time positions t3, t4 and t5 by performing the same operation as referred to above. FIG. 4 is a diagram illustrative of the connection of

transmission devices 1081, 1082 to an input highway 150 0 and an output highway 160 respectively. A description

15

25

30

35

45

55

65

15%, . .

will now be made to the data exchange with reference to FIG. 4.

In FIG. 4, for example, the transmission device 1081 serves to output data A to the input highway 150 at the time position t1 shown in FIGS. 2 and 3, and receive data from the output highway 160 at the same time position, while the transmission device 1082 serves to output data B to the input highway 150 at the time position t2, and receive data from the output highway 160 at the same time position. When the time division switching apparatus 100 operates to execute the ex change of data at such time positions as shown in FIGS. 2 and 3, the transmission device 1081 serves to receive the data B outputted from the transmission device 1082 whereas the transmission device 1082 serves to receive the data A outputted from the transmission device 1081. Thus, the exchange between the data A and B is made, so that the data exchange is performed between the transmission devices 1081 and 1082.

Since the conventional time division switching appa ratus is constructed as described above, necessary mea sures such as an increase in the operation frequency of the time division switching apparatus should be taken depending on an increase in the quantity of data to be exchanged within a given period of time or reduction in the capacity of data units such as a frame unit, an octet unit, a bit unit, etc. In addition, since the buffer memory and the control memory provided in the time division switching apparatus each make use of memory circuits, the limit of the operation frequency of each memory circuit is lower than that of the operation frequency of another circuit. Thus, a restriction is imposed on the quantity of data to be exchanged and the data units owing to the limit of the operation frequency of each of the buffer memory and the control memory.

Further, when a plurality of input highways and output highways are employed in the apparatus, such a circuit construction as shown in FIG. 5 is usually taken.

In other words, a multiplexer 1091 serves to convert data on each of input highways 1500, 150b, . . . , 150n into data represented in a multiplex form so as to apply the resultant data to a high-speed highway 1501. Then, the time division switching apparatus 100 serves to convert the data on the high-speed highway 1501 on a time-sharing basis into a desired data so as to apply the result to a high-speed highway 1601. A demultiplexer 1092 serves to separate data on the high-speed highway 1601 into individual data so as to supply the same to corresponding output highways 160a, 160b, . . . 160n. At this time, the data transfer frequency of each of the input highways 1500, 150b, . . . , 15011 is equal to that of each of the output highways 1600, 160b, . . . , 160n. The data transfer frequency of each of both the high-speed input highway 1501 and the high-speed output highway 1601 is equal to the sum of the input highways 150a,

. , 150n or the output highways 1600, 160b, . . .

, 160n. -