TI Allegro ADW User Training Slides

TI Confidential – NDA Restrictions

Texas Instruments Allegro/ADW User Training


Version 07162013

Class Overview

• The following slides are intended for the TI ATE PCB ADW user training class.

• This class is designed for new TI test engineers without any previous CAD tool

experience, and will be mostly lab exercises based with minimal instructor feedback.

• This training assumes that users have already installed the TI Cadence ADW ESD

software package via the ESD website.

• Users should have copied training files from Y:\training_projects to C:\training_projects

• The materials covered in this class will take the users through the Texas Instruments ATE

PCB design flow

– Request of documentation and revision numbers

– Component request

– Schematic capture

– Packaging and sending to vendor for layout

– Placement and layout review

– How and where to request help if needed


Version 07162013

Class Overview

• Breakdown of sections and class schedule

– Day 1: Introduction to ADW and Cadence SPB tools

• Overview of TI ATE PCB Infrastructure

• How to create a new project from TI ATE PCB template

• How to add components from the TI library

• Basics of schematic creation

• Chapters 1-4

– Day 2: Advanced schematic creation and sample project

• Implement design rules and checking

• Schematic page management

• Creating a TI multi-site board from scratch and send to a vendor

• Chapters 5-7

– Day 3: TI ADW flow and PCB routing review

• Run through all TI ADW flow buttons and functionalities

• Review a sample TI PCB with Allegro Viewer Plus

• Chapter 8

• Last minute review and quiz


Version 07162013

Chapter 1: TI ATE PCB Design Flow

• This chapter is intended to familiarize users with the TTPEG TCI PCB

design flow.

• ADW stands for Allegro Design Workbench, and is the Cadence flow

manager TI currently uses for PCB schematic capture and layout.

• TI ATE PCB group in TTPEG-TCI has defined all current flows for ATE

PCB development in the TI Cadence environment.

• Most of the sections’ materials are covered in later chapters, so this

chapter is mostly used to supply reference material links to users


Version 07162013

1.1 TI ATE Board Development Process

• TI ATE Board Development Process Overview

– Detailed documentation and instruction can be found at

http://www1.msp.sc.ti.com/test/proc/%5Ctest%5Cdesign%5CTMGPCBFLO

WWebsite.ppt

http://www1.msp.sc.ti.com/test/proc/test/design/TMGPCBFLOWWebsite.ppt




Version 07162013

1.2 ADW Flow Manager Use Model • ADW Flow Manager Use Model

– Detailed documentation can be found at

https://tisps.itg.ti.com/sites/Make_PCB/TISHARE/Cadence_Documentation/TI%20AT

E%20Tools%20Overview.docx

https://tisps.itg.ti.com/sites/Make_PCB/TISHARE/Cadence_Documentation/TI ATE Tools Overview.docx

https://tisps.itg.ti.com/sites/Make_PCB/TISHARE/Cadence_Documentation/TI ATE Tools Overview.docx


Version 07162013

1.3 Project Setup

• Because the TI Cadence ADW ESD installer automatically sets the

directory paths of all templates and libraries, users are encouraged to

not modify any default settings of the original install.

• 1.3.1 Where to find Schematic Template

– Schematic templates are existing board designs which users should start

their boards from, and already contain critical tester information such as

electrical connectivity and mechanical design.

– Schematic Templates should be will be explained in next chapters

– Additional templates can be requested at the ATE PCB sharepoint @

https://tisps.itg.ti.com/sites/Make_PCB, and clicking the template request

button

• 1.3.2 Project Directory Structure

– All ADW projects should be placed under C:\ADW_Projects by default install

– Users are encourage to not modify or change the default install settings

https://tisps.itg.ti.com/sites/Make_PCB



Version 07162013

1.3 Project Setup

• 1.3.3 Library Organization

– All library organization is currently maintained by TTPEG TCI, and will not

be available for user modification

– Additional library parts can be requested at the ATE PCB sharepoint @

https://tisps.itg.ti.com/sites/Make_PCB, and clicking the library request

button



Version 07162013

1.3 Project Setup

• 1.3.4 Project Settings

– The current TI supported version of ADW (via ESD) is 16.5-S029

– The current TI supported version of SPB (via ESD) is 16.5-S040

– If the users’ versions does not match the supported versions, re-install software from

ESD

– All project settings are automatically set during ESD install, and users are

encouraged to keep all settings to the installation default


Version 07162013

1.3 Project Setup

• 1.3.5 Help Resources

– For any issues specific to use of Cadence tools, users should issue a

support ticket at the Cadence support website @

http://support.cadence.com.

– Detailed instructions on how to file a Cadence ticket (COS) can be found at

https://tisps.itg.ti.com/sites/Make_PCB/TRAINING_IN/ADW_Training_Extra

s/Cadence_Case_Managment_TI_r2.ppt

– For any TI specific flow issues or feedback, users can fill out a feedback

form on the PCB sharepoint @ https://tisps.itg.ti.com/sites/Make_PCB, then

click on the ATE Feedback button

http://support.cadence.com/

https://tisps.itg.ti.com/sites/Make_PCB/TRAINING_IN/ADW_Training_Extras/Cadence_Case_Managment_TI_r2.ppt






Version 07162013

Chapter 2: Starting ADW

• This chapter will familiarize the users with starting a new project from a

TI PCB template.

– 2.1 How to start ADW

– 2.2 How to define/select templates based on testers

• Note: Certain templates are assumed for the lab, but in normal circumstances

users should already have determined tester configuration before starting ADW

– 2.3 Where to fill out information for BOM and border data

• Note: Outside of the lab, users should already have defined EDGE number,

revision, ECR, and preferred layout vendor before starting ADW. If uncertain,

refer to the information in section 1.1 for reference.

– 2.4 Reviewing settings for the project

• Note: This step is optional, and the ESD installer has already chosen the optimal

locations for project files. Users are encourage to keep all default settings as per

the ESD install.

– Please be patient. After all information has been entered, ADW may require

several minutes to start.


Version 07162013

Chapter 2

Please begin section 2.1 – 2.4 lab exercises now


Version 07162013

Chapter 3: Design Preparation

• Before starting a schematic, users must prepare their design:

– Selection of appropriate components for the schematic

– Possible re-use of reference designs and updating components on the

reference design to match the updated library

• All TI ATE PCB libraries are set up from the Y: drive during the ESD

install, and does not require any user modification to use.


Version 07162013

Chapter 3

• Breakdown

– 3.1 Accessing Libraries

• This section teaches the users how to access the TI PCB libraries from ADW

Component browser

• From the component browser, users can determine which components they need

by sorting by component properties such as component value, supplier,

temperature, availability, and more. Manufacturer datasheet links are also

available via the DATASHEET property.

– 3.2 Component Status Color Designations

• The colors green, yellow, and red indicates the level of risk the component’s

availability, TI rated performance, or vendor preference.

– 3.3 Component Selection: Shopping Carts

• Shopping Carts are used to save frequently used components to the local project

instead of querying the library through the network to place every component.

This section will demonstrate how to access the shopping cart and add

components to it from the library.


Version 07162013

Chapter 3

– 3.4 Saving a Shopping Cart as a Shopping List

• This section will show users how to save a shopping cart to use for other designs.

– 3.5 Library Revision Manager

• This section will illustrate how ADW manages library component revisions. All

updating should be fairly simple through ADW, as if a component is not up to date,

the LRM will automatically pop-up and prompt updating.

– 3.6 Library Request Process

• All library request should be through the TI PCB Sharepoint at

https://tisps.itg.ti.com/sites/Make_PCB. Please refer to section 1.3.3 above for

details.

– 3.7 Reusing Design Content: Import Design

• This section illustrates how users can import pages of a reference schematic to

the current schematic.




Version 07162013

Chapter 3

Please begin section 3.1 -3.7 lab exercises now


Version 07162013

Chapter 4: Schematic Capture in HDL

• This chapter contains the main lab exercises for day 1 of training, and

contains instructions on how to navigate the schematic capture tool

Allegro Design Entry HDL.

– Section 4.2 will demonstrate some basic usage of the HDL tool such as

zooming and color changing.

– Sections 4.3-4.5 will demonstrate how to add components, assign reference

designators, and navigate through component attributes.

• Please note that in section 4.4.2, users may need to reference Appendix 1: HDL

Parts Manager, to resolve a packaging error.

– Section 4.6 demonstrates the copying of components and circuits from

within a schematic.

– Section 4.7 demonstrates pin number assignments.


Version 07162013

Chapter 4

– Section 4.8 demonstrates how to pick different symbols from components

with more than a single PACK_TYPE

– Sections 4.9-4.11 demonstrates adding special symbols such as plumbing

bodies and page borders

• Please pay special attention to sections 4.10.1 and 4.10.2, as these sections

covers important information when using the TI ADW flow (as illustrated in lab 7)

– Sections 4.12-4.13 deals with wiring of the schematic.

– Section 4.14 mentions additional TI tools that will be further demonstrated in

chapter 7.

– Section 4.15 demonstrates how to add text and images on the schematic.

– Section 4.16 demonstrates how to save the project.


Version 07162013

Chapter 4

Please begin the chapter 4 lab exercises starting on section 4.1 now


Version 07162013

Chapter 5: Design Rules in HDL

• This chapter begins day 2 of the TI ADW training.

• This chapter will demonstrate the use of the Allegro Constraint

Manager to implement design rule checks. The lab will add both

electrical and physical rules to the design to enable automatic checks.

• Although optional, correctly implemented design rules can often save

the test engineer time when communicating routing needs to the layout

vendors.

• Please begin section 5.1 – 5.4 lab exercises with the last saved project

from chapter 4.


Version 07162013

Chapter 6: Design Changes in HDL

• This chapter covers how to systematically modify schematics in HDL:

– 6.1 Search and Replace Tools

• This section covers how to search and replace text and properties in HDL

– Additional TI custom tools for search and replace is not covered in this section.

For more instruction on the custom tool, please see Appendix 3 of the manual

– 6.2 Page Management

• This section describes who to add or delete a page from a schematic. Please

note that once deleted, a page cannot be recovered by undo

– 6.3 Move Circuitry from one page to another

• This section will cover the methods for moving circuits within a schematic

• Please note that this is different than schematic import, as we assume that all

components within our schematic is already updated to the most current version of

our library


Version 07162013

Chapter 6

Please begin section 6.1 – 6.3 lab exercises now


Version 07162013

Chapter 7: Practical Project

• This chapter contains the main lab for day 2 of the user training, and

walks the user through the creation of an ETS-364 schematic using the

TI ATE PCB flow.

• Additionally, this chapter highlights the use of custom TI tools

(dalTools), which provides more efficiency and accuracy to the

schematic creation process.

• Please follow the instructions in the lab exactly. Skipping steps in this

lab may cause issues further into the lab.

– Sections 7.1 – 7.3 uses skills demonstrated in previous chapters to create a

single site schematic circuit.

– Sections 7.4 - 7.6 creates a quad site schematic from the single site circuit.

– Sections 7.7 – 7.11 checks, packages, and simulates sending the schematic

to a vendor per the TI ATE PCB flow.


Version 07162013

Chapter 7

Please begin the chapter 7 lab starting from section 7.1 now


Version 07162013

Chapter 8: ADW FlowManager

• This chapter begins day 3 of the TI ADW training.

• This chapter walks the users through every button on the TI ATE PCB ADW flow. While

most of the buttons are self-explanatory or used in previous sections in chapter 7, users

should use this section as a reference to understand the functionality of steps within the

flow.

• Please pay special attention to section 8.16.2 Allegro Viewer Plus, as this section

describes the basic use of the viewer tool in the TI ADW suite. Users will need to

understand how to cross-probe between the schematic and layout in order to review and

approve incoming placement and layout from the vendors.

• In section 8.16.2, users should use the project in C:\training_projects\training4_16\ folder

to practice cross-probing. Open a new project using ADW and browse to this folder and

select the appropriate CPM file to start.

• Additional advanced training in Allegro Viewer Plus can be found on Appendix 2 of the

training manual.

• Please read through chapter 8 now starting from section 8.1.


Version 07162013

End of Training

• This will conclude the TI ADW training.

• Please take the quiz to claim credit for this class.


Version 07162013

Additional Help

• For all Cadence tool specific inquiries, please contact Cadence support

directly by issuing a COS ticket at http://support.cadence.com. Users

should still issue a COS ticket if unsure the problem is a Cadence or TI

specific.

• For TI PCB flow, template, library, or installation questions or issues,

please fill out feedback form on the PCB Sharepoint at

https://tisps.itg.ti.com/sites/Make_PCB/Lists/Cadence%20Feedback/Ne

wForm.aspx. Please make sure to fill out the appropriate Category for

timely support.

• For all other inquiries, please contact Mike Korson ([email protected])

directly.

http://support.cadence.com/

https://tisps.itg.ti.com/sites/Make_PCB/Lists/Cadence Feedback/NewForm.aspx



mailto:[email protected]

Documents

TI Allegro ADW User Training Slides