Thermal Resistance - Theory and Practice

8/14/2019 Thermal Resistance - Theory and Practice

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S p e c i a l S u b j e c t B o o k J a n u a r y 2 0 0 0

S M D P a c k a g e s

N e v e r s t o p t h i n k i n g

T h e r m a l R e s i s t a n c e

T h e o r y a n d P r a c t i c e

h t t p : / / w w w . i n f i n e o n . c o m


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Edition January 2000

Published by

Infineon Technologies AG,

St.-Martin-Strasse 53,D-81541 Mnchen

Infineon Technologies AG 1999

All Rights Reserved.

Attention please!

The information herein is given to describe

certain components and shall not be

considered as warranted characteristics.

Terms of delivery and rights to technical

change reserved.

We hereby disclaim any and all warranties,

including but not limited to warranties of

non-infringement, regarding circuits,

descriptions and charts stated herein.

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manufacturer.

Information

For further information on technology,

delivery terms and conditions and prices

please contact your nearest Infineon

Technologies Office in Germany or our

Infineon Technologies Representatives

worldwide (see address list).

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For information on the types in question

please contact your nearest Infineon

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Life support devices or systems are

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3/363

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SMD-Package Properties for Power Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Using a Printed Circuit Board as a Heat Sink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Static Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Dynamic Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Finite Element Method (FEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Determining the Static Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Measuring theRthj-a in the Real Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Determining the Dynamic Heat Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Package and Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Thermal Resistance - Theory and Practice

Contents

Infineon Technologies AG


4/36Infineon Technologies AG4


Power-SMD applications or

whats the size of the heat sink ?

More and more frequently,

modern SMD-component users

(Surface Mounted Devices) ask

the question, Whats the size of

the heat sink ?

The reason: The trend from

through-hole packages to

low-cost SMD-applications is

marked by the improvement of

chip technologies.

Silicon instead of heat sink is

therefore possible in many cases.

The printed circuit board (PCB)

itself becomes the heat sink. As

many applications today use

PCBs assembled with SMD-

technology, the emphasis is onPower-ICs in SMD packages

mounted on single-sided PCBs

laminated on one side.

Pricing pressure demands simple

processes and lowest-cost

solutions. This report describes a

solution.

Introduction


5/36Infineon Technologies AG 5

1.27

1.4

5-0.2

1 78.75 -0.2

14 8

1.7

5max.

0.2

6 0.2

0.35 x 45

-0.24

0.1

-0.1

0.4 +0.8

Index Marking

P-DSO-14-4P-TO252-3-1

1)

+0.150.35 2)0.2 14x

1)

0.1

9

+0

.06

8max.

L

PackageFootprint / Dimensions

Dimensions in mm

e

1.27P-DSO-14-4

A

5.69

L

1.31

B

0.65

BA

e

5.4 0.1

-0.106.5

All metal surfaces thin plated,except area of cut.

+0.15

A

0.5

9.96

.22

-0.2

10.1

0.1

5

0.8

0.15

0.1

maxper side 0.75

2.28

4.57

+0.08-0.040.9

2.3 -0.10+0.05

B

min

0.5

1

0.11

+0.08-0.040.5

0...0.15

BA0.25 M 0.1

3x

(4.1

7)

5.8

6.4

2.2

10.6

5.76

1.2

Figure 1 Heat Sink - vs. Thermal Enhanced Package Types

SMD-Package Properties forPower Applications

There are two basic groups of

packages:

Heat Sink packages are the first

group.The heat sink (chip carrier -

lead frame) is soldered directly to

the PCB. The thermal resistance

of this packages between chip

and heat sink is calledRthj-c(junction-case) and has low

values.

Thermal Enhanced Leadframes

constitute the second group of

packages. Metal bridges are

connected between the chip

carrier (lead frame) and the pins.

From the outside, this package

looks identical to standard

components because the plastic

molding compound conceals

these details. Figure 1 shows

both types of packages with the

examples P-TO252-3-1 (D-Pack)

and P-DSO-14-4 (3 center pins

each per side of the cooling path).

The internal structure is described

in more detail in this report and

can be seen in Figure 11.




Using a printed circuit boardas a heat sink ?How do I calculate that ?How big does my heat sinkneed to be ?Which size do we need ?

In earlier fabrications, a solid heat

sink was either screwed or

clamped to the power package. It

was easy to calculate the thermal

resistance from the geometry of

the heat sink.

In SMD-technology, this

calculation is much more difficult

because the heat path must be

evaluated: chip (junction) - lead

frame - case or pin - footprint -

PCB materials (basic material,

thickness of the laminate) - PCBvolume - surroundings.

As the layout of the PCB is a main

contributor to the result, a new

technique must be applied. The

Appendix proivdes thermal data for

all packages listed in Table 1.

Let us start with some

theoretical considerations:

Static Properties

To facilitate discussion of the

static properties of a Power IC

(PIC), the internal structure of a

PIC and its method of mounting

on a PCB or heat sink is

illustrated in Figure 2. The PIC

consists of a chip mounted on a

chip carrier or lead frame, and

held by solder or bonding

adhesive. The lead frame consists

of a high-conductivity material

such as copper, and can have a

Table 1 The Most Important

SMD-Packages

Package Heat Sink / Pin

P-DSO-8-1

P-DSO-14-4 Pin 3-5; 10-12

P-DSO-16-1

P-DSO-20-1

P-DSO-20-6 Pin 4-7; 14-17

P-DSO-24-3 Pin 5-8; 17-20

P-DSO-28-6 Pin 6-9; 20-23

P-DSO-20-10 Tab

P-DSO-36-10 Tab

P-TO252-3-1 (D-Pack)

SCT-595-5-1 Pin 2; 5

SOT-223-4-2 Tab or Pin 4

P-TO263-5-1 Tab

Tab



thickness of several millimeters.

The associated static equivalent

circuit is shown in Figure 3. The

following analogies with electrical

quantities have been used:

C The power dissipation PVoccurring close to the chip

surface is symbolized by a

current source.

C The thermal resistances are

represented by ohmic

resistors. The resistance

network is essentially a serial

connection to the ambient

temperature. As a first

approximation, the parallel-

connected thermal resistance

of the molding (broken lines)

can be neglected in power

packages.

C The ambient temperature is

represented by a voltage

source.

In accordance with the analogy,

the thermal current PV = Q/tcan

now be calculated from the

thermic Ohms law

V=I R as Tj - Ta = PV Rthj-a.

For the purpose of discussing the

application as a whole, thefunction PV = (Ta) is of practical

interest. One obtains:

PV = - Ta/Rthj-a + Tj/Rthj-a.

This is a descending straight line

of gradient -1 /Rthj-a with its zero

at Tj.

Figure 2 Internal Structure of

a PIC and Method ofMounting on

a Heat Sink

Chip (Die)

Molding compound

(Molding)

Heat sink or PCB

(Heat sink)

Chip adhesive / Lot

(Die bond)

Chip carrier(Leadframe)

Solder

=PV Tj TaTc

Diebond

Die Lead-frame

Solder Heatsink

Rth

Molding

Rth Rth

Rthj-c

Rthj-a

Rth

Application

Rth Rth Rth

Figure 3 Static Equivalent

Circuit for the

Structure

shown in Figure 2




In Figure 4, this function is

shown for the P-DSO-14-4 Pack-

age (Thermal Enhanced Power

Package) mounted on the

standard application board. From

this function, the user can derive

the permissible power dissipation

directly for any ambient

temperature. At Ta = 85 C, for

example, the permissible

dissipation is approxi-mately

0.7 W. The exact value can be

calculated from the equation

PV = (Tj - Tamax) /Rthj-a =

65 K / 92 K/W = 0.7 W.

It should be noted that in the data

sheets of the PICs the power

dissipation is given as a function

of the package (case) tempera-

tureT

C, because the application-specific thermal resistances are

not known to the manufacturer.

This function, like the previous

one, is a descending straight line.

The slope now has the value

1 /Rthj-c. The zero remains at Tj.

As an example, this function is

presented in Figure 5 for the

P-TO252-3-1 Package.

The new P-TO252-3-1 package

has a thermal resistance of max.4 K/W and is unique in the small

size of its base area when com-

pared with packages of equivalent

performance (PCB board area). At

approximately 30 C, the permis-

sible power dissipation is 30 W.

Higher power dissipation is

prevented by intervention of the

chip-internal current limiters. For

this reason, the value for power

dissipation at lower temperatures

remains constant. Figure 5 Permissible Power Dissipation of

the P-TO252-3-1 as a Function of

the Package (Case) Temperature

Figure 4 Permissible Power Dissipation of the

P-DSO-14-4 Package Mounted on aPCB with 300 mm Cooling Area, as

a Function of Ambient Temperature

0 TC

PV

W

C150100500

10

Rthj-c = 4 K/W20

30

Ta

Tj

PV

W

W 1.63 W

150 C100500

0.54

0

1.08

1.63

PV = 1 W

T= 92 C

Parameter: Tjmax = 150 C

Rthj-a = 92 K/W

Tamax = 85 C

Tj

Tamax

Rthj-a

PVO =150

92=



Dynamic Properties

As mentioned earlier, the thermal

behavior of PICs changes when

dynamic phenomena are

considered (pulse power

operation). This behavior can be

described in terms of thermal

capacity Cth, which is directly

proportional to the relevant

volume V(in cm), to the density

(in g/cm) of the material and to

a proportionality factor of the

specific heat c in Ws/g K.

The applicable equation is:

Cth = c V= m c

This means: The thermal capacity

of a body of mass m = V

corresponds to the quantity of heat

needed to heat the body by 1 C.

To calculate the temperature

change Tit is necessary to use

the quantity-of-charge equation

for a capacitance C.

The equation is:

V C=I t= Q

By analogy, the quantity-of-heat

equation is:

T Cth = P t= Q

This means: Just as the current

I= Q/trepresents a transport of

charge per unit of time, the

power dissipation P represents

the transport of thermal energy

per unit of time. Consequently:

T=

The equivalent circuit of the

P-TO263-7-3 power package, with

the thermal capacities added, is

shown in Figure 6. The thermal

capacities calculated from the

material and the volume are

shown in parallel with the thermal

resistances.

When calculating the components

of a network it is necessary to

know the thickness d, the cross-

sectional areaA and the thermal

conductivityL in W/m K, in order

to obtain the appropriate thermal

resistanceRth. The formula is:

Rth = ]K

W[d

L AP t

Cth

Figure 6 Thermal Equivalent

Circuit of the

P-TO263-7-3 Package

(Simplified)

3 mWs/K 300 mWs/K

0.24 K/W0.48 K/W

Heat sink

RthD RthHS

HS = 70 msD = 1.5 ms

CthDPVTcase

Die

CthHS=




A

8max.

BA0.25 M

0.1 Typical

9.8 0.15

0.210

8.51)

81)

(15)

0.2

9.2

5

0.3

1

0...0.157x0.6 0.1

0.11.27

4.4 Footprint

B

0.50.1

0.3

2.7

4.7

0.5

0.05

1)

0.1

All metal surfaces tin plated, except area of cut.

0.3

1.3

2.4

6x1.27

8.4

2

10.8

9.4

16.15

4.6

0.4

7

0.8

To calculate the thermal capacity

Cth, it is necessary to know the

volume V= d A, the specific

weight in g/cm3 and the speci-

fic thermal capacity c in Ws/g K.

The thermal capacity Cth is

calculated from:

Cth = m c (Ws/T).

The package dimensions are

shown in Figure 7.

Table 2 lists all the important

parametric data of the

P-TO263-7-3 package.

Figure 7 Outline Drawing of the P-TO263-7-3 Power Package

Table 2 Parametric Data of the P-TO263-7-3

AHSArea (effective area of 64 mm)

dHSThickness

LCuThermal conductivity of cooper

RthHSThermal resistance of heat slug

CuSpecific weight of cooper

mHSMass of heat slug

cCuSpec, thermal capacity of Cu

CthHSThermal capacity of heat slug

HSThermal time constant of heat slug

Symbol

14

1.27

384

0.24

8.93

0.8

0.385

310

70

Value

mm

mm

W/mKK/W

g/cm

g

Ws/gKmWs/K

ms

DimensionParameters for the Heat Slug

ADArea

dDThickness

LSiThermal conductivity of silicon

RthDThermal resistance of chip

SiSpecific weight of silicon

mDMass of chip

cSiSpec, thermal capacity of Si

CthDThermal capacity of chip

DThermal time constant of chip

Symbol

5

360

150

0.48

2.33

4.2

approx. 0.7

approx. 3

approx. 1.5

Value

mm

m

W/mKK/W

g/cm

mg

Ws/gKmWs/K

ms

DimensionParameters for the Chip



The die bond and molding

components have been omitted

from this discussion because they

do not significantly influence the

calculation ofRthj-c.

For reference, these data are

listed here:

C RthDB = 0.01 to 0.1 K/W;

C

CthDB = 0.1 to 0.5 mWs/K;

C DB = 1 to 50 ms;

C RthM = 100 K/W;

C CthM = 0.64 Ws/K and

C M = 64 s.

(Die Bond = index: DB;

molding = index: M)

The time constance of the die

bond is smaller than that of the

chip by two orders of magnitude

and can, thus, be neglected.

The thermal resistanceRthM of

the molding is even three orders

of magnitude bigger than that of

the chip and that of the heat slug,

and, being in parallel, can be

neglected also.

Pulse operation and the associat-

ed chip temperature responses

also deserve examination.

In accordance with the analogy to

electrical systems, the chip tem-

perature response can be viewed

like a voltage increase across an

RC section which is being fed by

a current pulse generator.

The following relationship applies:

V(t) =R I (1 - et/R C)

and for the increase in tempera-

ture:

T(t) =Rth P (1 - et/Rth Cth)

This heating-up and cooling-down

process is presented qualitatively

in Figure 8 (valid for tp >> 2 ms

only).

The chip temperature goes up

and down between Tmin and Tmax.

The variation depends on the

magnitude of the power pulse

and its duty cycle.

Figure 8 Chip Temperature Tjvs. Time, for Periodic

Pulse Operation

t

PV

Tj

t

Tmax

Tmin

Tavg

T

tp




This junction temperature

transients can be represented in

the form of a function if the

dynamic thermal impedance

Zth = (Tmax - Tmin) /PVis shown versus pulse width tp for

different duty cycles (duty cycle =

DC = tp/T) (Figure 9).

A special case of this representa-

tion is the dynamic thermal

impedance in single-pulse

operation (DC = 0). Figure 10

shows the thermal impedance in

single-pulse operation for the

medium-power package

P-DSO-14-4 for three different

cooling areas on the PCB.

This function clearly shows the

regions of dominance of the

various time constants of the

chip, the lead frame, and the

PCB.

The chip time constant tD lies in

the millisecond range, whereas

the lead frame dominates in the

range of several 100 ms and the

PCB in the 100-second range.

single pulse

0.50

D =

0.20

0.10

0.05

0.02

0.01

10 -4-710

Zthj-c

10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 s 10 0

-310

-210

-110

010

K/W

tp

Figure 9 Dynamic Thermal

ImpedanceZthj-c of a

P-TO263-7-3 Package

10-3

0

20

40

60

80

100

120

10-2

10-1

100

101

102

103

600 mm2

300 mm2

FootprintZthj-a

K/W

tp

s

Figure 10 Thermal Impedance of the

P-DSO-14-4 Package for

Single-Pulse Operation



Finite Element Method (FEM)

The steps of the Finite Element

Method (FEM) are explained

below and one example is

provided per group.

The geometric data of the

package is entered into the FEM

model to calculate the thermal

resistance. This avoids time-

consuming measurements.

Figure 11 shows an implemented

model.

Figure 11

P-TO252-3-1 P-DSO-14-4

FEM Model of Heat Sink and

Thermal Enhanced Package




Figure 12

The temperatures of the

individual components (chip, die-

pad, molding compound, and

leadframe) can be viewed

individually or in combination

(Figure 12).

Chip with two active areas (dice only) Mold compound without cooling

tab,chip and lead frame

P-TO252-3-1 without mold compound

with PV = 3 W for determining theRthj-c

Chip and lead frame of the

SOT223-4-2 package on a PCBwith heat sink

Lead frame of the SCT595-5-1 on a

PCB with heat sink

SOT223-4-2 on a PCB with 6 cm

heat sink;Rthj-a ~ 70 K/W is calculated

at PV = 0.5 W

FEM Analysis Possibilities



Three different PCBs have been

created for each package model.

They differ in the size of the

copper laminated area A (heat

sink) which is linked to the heat

dissipating parts of the case (die-

pad in the P-TO252-3-1 or center

pins in the P-DSO-14) (Figure 13).

1 1

P-DSO-14-4

1

1 2 36 cm 3 cm Footprint only

P-DSO-14-4P-DSO-14-4

Application-Board for Rth Measurement Rth-P-DSO-14-4 LP 1.0

Application-Board for Rth Measurement Rth-P-TO252-3-1 LP 1.1

-16-1

a

a/20.375

a

a/2

0.375

0.6

7

P-TO252-3-1

1I Q

1

P-TO252-3-1

I Q

P-TO252-3-1

1I Q

1 2 3Footprint only6 cm 3 cm

a

a/2

a

a/2

Figure 13 PCB-Layout for FEM-SimulationP-DSO-14-4 and P-TO252-3-1




Determining the Static HeatResistance

The FEM simulation calculates

the thermal static resistanceRthj-a(junction-ambient) and theRthj-c(junction-case) for packages with

enhanced die-pad orRthj-pin(junction to a defined pin) for

thermal enhanced P-DSO

packages without die-pad. This

value depends only slightly on the

active chip area. It is sufficient to

simulate just one medium-sized

chip (>2 mm).

If the static thermal resistance

Rthj-a is applied versus the PCB

heat sink area, a very important

function is obtained for the

application of the component. By

estimating the heat sink area in a

real application, the user can

easily determine the expected

Rthj-a, especially as the simulated

values are calculated in still air.

Therefore, they represent the

worst case. In real applications

the values for the heat resistance

are much lower. At an air stream

of 500 lin ft/min (linear feet per

minute) theRthj-a of the

P-DSO-14-4 for example is up to

15 % lower (Figure 15).

Rthj-pin = 31.7 K/W

040

A

Rthj-a

50

60

70

80

90

100

K/W120

100 200 300 400 500 600mm2 0 100 200 300 400 500 mm2 600

A

40

Rthj-a

60

80

100

120

K/W160

Rthj-c = 1.8 K/W

P-DSO-14-4 P-TO252-3-1

112

92

78

143.9

78

54.7

Figure 14 Thermal Resistance Junction to AmbientRthj-a vs.

PCB Heat Sink AreaA at zero airflow

0

Airspeed Airspeed

Rthj-a

60

70

80

90

100

110

K/W120

100 200 300 400 600m/min m/min0 50 100 150 20040

60

80

100

120

140

160Rthj-a

K/W

P-DSO-14-4 P-TO252-3-1

Footprint onlyA = 300 mm 2

A = 600 mm 2

Footprint onlyA = 300 mm 2

A = 600 mm 2

Figure 15 Thermal Resistance Junction to AmbientRthj-a vs.

Airspeed for the P-DSO-14-4 and P-TO252-3-1 Packages



Measuring theRthj-a in aReal Application:

Using the measurement described

below the real thermal resistance

can be determined.

To determine the actualRthj-a the

temperature difference between

chip temperature Tj and ambient

temperature Ta is required. The

equationRthj-a = applies.

The power loss PV and the ambient

temperature Ta can be determined

easily in a temperature chamber or

calculated.

To measure the chip temperature

(Tj) requires a little trick:

A temperature sensor is required

on the chip which can also be read

during operation. In many products

a substrate diode can be used at

an output (Status, Reset, etc.) to

measure the chip temperature.

To do this, the forward voltage VF

of the diode is measured at load

independent current as a

calibration curve. Due to the

characteristic temperature behavior

of the forward voltage - it has a

negative temperature coefficient of

approx. -2 mV/K - the relevant chip

temperature can be determined.

The calibration curve is measured

in the temperature chamber with

airflow. The power loss should be

kept as low as possible to ensure

the chip temperature remains

equal to the ambient temperature.

For the voltage regulator

TLE 4269 GM (P-DSO-14-4 Package)

a calibration curve (measured at

the diode at the reset output, pin 7).

RO is illustrated in Figure 16.

Figure 17 shows the

corresponding measuring circuit.

Tj - Ta

PV

Figure 16 Calibration Curve TLE 4269 GM forIRO = -500 A

(current drawn from Pin 7; RO)

00

100

200

300

400

500

600

700

T

VF

50 100 150

mV

C




TheRthj-a of any application can be

determined by measuring the

forward voltage of an output with

substrate diode during operation

(Figure 17).

When the switch S1 is closed and

the output voltage VQ = 5 V, the

output current is A.

The power loss PV = (VI - VQ) IQ

in the chip of the voltage

regulator is now 1 W. Now,

change the ambient temperature

Ta and measure the respective

forward voltage VF of the diode.

The appropriate Tj for every VF

value can be read from the

calibration curve VF = (Tj).

The exact heat resistance of the

real application is calculated with

this values in the formula

Rthj-a =

Parameters such as air flow can

be changed without affecting the

measuring accuracy.

Tj - TaPV

5

35

Figure 17 Measuring Circuit

with TLE 4269GM

RF100 k

TROSubstratdiodeof TRO

TLE 4269 GM

TPower

P-DSO-14-4

VI = 12 V CI10 F

I

VF ~ 0.7 V

IF ~ 500 A

+

RL35

S1

CQ22 F

Q913

7

3-5; 10-12

RO

VB50 V

RPU20 k

1. Measurement of function VF = f(Ta):S1 open; we get IQ = 0 mA

andP

V =VI*II ~ 0 mW Ta ~ Tj

2. Measurement of thermal resistance junction to ambient Rthj-a:S1 closed; we get IQ = VQ/RQ

andP

V = (VI -

VQ) *

IQ ~ 1 WTj then can be found by measuring VF at given Ta from function VF vs. Ta

then we get Rthj-a = (Ta - Tj) / 1 W

PVTa

Tj

= Power losses= Ambient temperature= Junction temperature



Determining the DynamicHeat Resistance

The FEM analysis is used also for

dynamic processes.

As described above, the dynamic

thermal impedance is defined as

the ratio of the temperature

difference T= Tj - Ta (chip tem-

perature - start temperature) after

the time tp to the power loss.

If a transient FEM simulation is

performed, it is easy to obtain the

graphZthj-a = (tp) (dynamic

thermal impedance as a function

of the pulse width tp).

For the P-TO252-3-1 (D-Pack) and

the P-DSO-14-4 the thermal

impedances for the above-

mentioned PCB configurations are

specified (Figure 18).

The peak temperatures can be

calculated easily from these

curves:

P-TO252-3-1 (D-Pack)

3 cm heat sink

Power loss PV = 10 W

Pulse width tp = 200 ms

Ambient temperature

Ta = 85 C.

From the middle curve (Figure 18),

theZthj-a of approximately 3.5 K/W

at tp = 200 ms gives a tempera-

ture rise T= PV x Zthj-a of 35 K

and finally a peak temperature

Tjmax of 85 C+35 C = 120 C.

Figure 18 Thermal Impedance

Junction to Ambient

Zthj-a vs. Single

Pulse Timetp

0

Zthj-a

10-3

10-2

10-1

100

101

102

103

120

K/W

60

40

80

20

100

tp

s

Footprint300 mm2

600 mm2

P-DSO-14-4 P-TO252-3-1

Zthj-a

600 mm2300 mm2

160

K/W

120

100

80

60

40

20

0

Footprint

tp

10-3

10-2

10-1

100

101

102

103

s




For each case listed in Table 1,

a Package and Thermal

Information data sheet is

provided in the appendix.Each

data sheet shows the footprint

and case dimensions. The various

versions of the PCBs used for the

simulation are shown. It showsthe heat distribution diagrams and

the result diagrams of the FEM

simulation. The left side shows

the diagram of the static thermal

resistanceRthj-a depending on the

PCB heat sink areaA. It includes

the related thermal resistance

Rthj-c (junction-case) orRthj-pin.

On the right side is the diagram

for the dynamic heat resistance

Zthj-a, with three graphs for the

various PCB heat sinks depending

on the single pulse duration tp.

This information is a valuable aid

for SMD Power applications. It is

intentionally limited to PCBslaminated on one side because it

represents the cost optimum. For

double sided PCBs or multilayers

a simple attempt with

conductance cross sections can

be made to determine the change

in the PCB thermal resistance

(compare thermal data sheet of

P-DSO-20-10 with P-DSO-36-10 in

the appendix).

The PCBs are usually installed in

closed plastic cases. The most

favorable heat path then usually

forms at plug contacts to the

cables because a supply wire

with an adequate cross section isideal as a heat conductor.

The future of chip placement

requires mechatronic solutions

where the PCB can be replaced

by chip-connector-supply wire

configurations.

Summary



P-DSO-8-1 22

P-DSO-14-4 23

P-DSO-16-1 24

P-DSO-20-1 25

P-DSO-20-6 26

P-DSO-24-3 27

P-DSO-28-6 28

P-DSO-20-10 29

P-DSO-36-10 30

SCT595-5-1 31

SOT223-4-2 32

P-TO252-3-1 33

P-TO263-5-1 34

Package and Thermal Information

Appendix


22/36

Infineon Technologies AG22

1 1 1

1 2 3

P-DSO-8-1

6 cm 3 cm Footprint only

P-DSO-8-1 P-DSO-8-1a/2

a

0.3

75

0.6

7

0.6

7

0.3

75

a

a/2

FR4; 80x80x1.5 mm; 35 Cu, 5 SnA = 600 mm; a = 17.32 mm


FR4; 80x80x1.5 mm; 35 Cu, 5 SnFootprint only

1.27

0.2

1.7

5max.

-0.1

1 45 -0.2

8 5

4 -0.2

6 0.2

0.1

9+

0.0

6

0.10.4

+0.8

0.35 x 45

Index Marking

1)

+0.150.35 2)0.2 8x

1)-0.2

1.4

5

8

max.

L

Package

Reflow soldering

e

1.27P-DSO-8-1

A

5.69

L

1.31

B

0.65

BA

e

Dimensions in mm

0100

A

Rthj-a

100 200 300 400 500 600mm2

tp

0

Zthj-a

10-3

10-2

10-1

100

101

102

103

s

K/WK/W

110

120

130

140

150

160

170

190

20

40

6080

100

120

140

160

200

600 mm2300 mm2Footprint

164

185

142

Rthj-pin2 = 71.8 K/W

Footprint/Dimensions

PC-Board

Finite Element Method

Diagrams

P-DSO-8-1


A = 600 mm; Ta = 298 K; Tmax = 369 K

FEM Simulation (chip area 2 mm; Pv = 0.5 W; zero airflow)

Application-Boards forRth - Measurement

Thermal Resistance Junction to Ambient Rthj-a vs.PCB Heat Sink AreaA (zero airflow)

Thermal Impedance Junction to AmbientZthj-a vs.Single Pulse Time tp (zero airflow)

A = 300 mm; Ta = 298 K; Tmax = 380 K Footprint only; Ta = 298 K; Tmax = 390 K


23/36


1 1

P-DSO-14-4

1

1 2 36 cm 3 cm Footprint only

P-DSO-14-4P-DSO-14-4




-16-1

a

a/20.375

a

a/2

0.375

0.6

7

1.27

1.4

5-0.2

1 78.75 -0.2

14 8

1.7

5max.

0.2

6 0.2

0.35 x 45

-0.24

0.1

-0.1

0.4GND GND

+0.8

Index Marking

1)

+0.150.35 2)0.2 14x

1)

0.1

9

+0

.06

8m

ax.

L

Package e

1.27P-DSO-14-4

A

5.69

L

1.31

B

0.65

BA

e

Reflow soldering

Dimensions in mm

0

Zthj-a

120

K/W

60

40

80

20

100

Footprint300 mm2

600 mm2

Rthj-pin4 = 31.7 K/W112

92

78

40

Rthj-a

50

60

70

80

90

100

K/W120

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s



P-DSO-14-4

PC-Board


Diagrams


A = 600 mm; Ta = 298.1 K; Tmax = 377.7 K

FEM Simulation (chip area 2 mm; Pv = 1 W; zero airflow)




Footprint only; Ta = 298 K; Tmax = 410.1 KA = 300 mm; Ta = 298 K; Tmax = 389.8 K


24/36


P-DSO-14-4

1

3Footprint only


-16-1

L

Package

Reflow soldering

e

1.27P-DSO-16-1

A

5.69

L

1.31

B

0.65

BA

e

1.27

1.4

5-0.2

1 810 -0.2

16 9

1.7

5max.

0.2

6 0.2

0.35 x 45

-0.24

0.1

-0.1

0.4 +0.8

Index Marking

1)

+0.150.35 2)0.2 16x

1)

0.1

9+

0.0

6

8m

ax.

Dimensions in mm


40

Rthj-a

0

Zthj-a Footprint

50

60

70

80

90

100

110

K/W

130121

20

4060

80

100

K/W

140

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s



PC-Board


Diagrams

P-DSO-16-1

Footprint only; Ta = 298 K; Tmax = 419.1 K


Application-Board forRth - Measurement




25/36



1

3Footprint only

P-DSO-20-1

-24-3-28-6

-20-6

L

Package e

1.27P-DSO-20-1

A

9.73

L

1.67

B

0.65

B

A

e

Reflow soldering1 10

1120

Index Marking

2.6

5max.

0.1

0.2-0.1

2.4

5-0.2

+0.150.35

1.27

2)

0.2 20x

-0.27.61)

0.35 x 45

0.2

3

+0.8

10.30.4

12.8 -0.21)

+0

.09

0.38

max.

Dimensions in mm


40

Rthj-a

50

60

70

80

90

100

K/W

120

0

Zthj-a

20

40

60

80

K/W

120

Footprint

109

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s




P-DSO-20-1

PC-Board


Diagrams

Footprint only; Ta = 298 K; Tmax = 407 K


Application-Board forRth - Measurement




26/36




1 1 1

1 3

a/2

a

6 cm Footprint only

P-DSO-20-6-24-3-28-6

23 cm

P-DSO-20-1

-24-3-28-6

-20-6-28-6-24-3P-DSO-20-6

a/2

0.3

a0.375 0.375

0.3

GND GND

L

Package e

1.27P-DSO-20-6

A

9.73

L

1.67

B

0.65

B

A

e


1120

Index Marking

2.6

5max.

0.1

0.2-0.1

2.4

5-0.2

+0.150.35

1.27

2)

0.2 20x

-0.27.61)

0.35 x 45

0.2

3

+0.8

10.30.4

12.8 -0.21)

+0

.09

0.38

max.

Dimensions in mm


40

Rthj-a

0

Zthj-a

20

40

60

80

K/W

120

50

60

70

80

90

K/W

110

100

74


0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s



PC-Board


Diagrams

P-DSO-20-6

A = 600 mm; Ta = 298 K; Tmax = 372 K







27/36




1 1 1

1 3

a/2

a

6 cm Footprint only

P-DSO-20-6-24-3-28-6

23 cm

P-DSO-20-1

-24-3-28-6

-20-6-28-6-24-3P-DSO-20-6

a/2

0.3

a0.375 0.375

0.3

L

Package

Reflow soldering

e

1.27P-DSO-24-3

A

9.73

L

1.67

B

0.65

BA

e

15.6 -0.4

24 13

1 12

Index Marking

1)

0.35 +0.150.2 24x

-0.2

2.6

5max.

0.1

0.2-0.1

2.4

5

1)-0.27.6

0.35 x 45

0.2

3+0

.09

10.3

GND GND

0.4+0.8

1.272) 0.3

8

max.

Dimensions in mm

40

Rthj-a

0

Zthj-a

K/W76.4

67.4

60.5

K/W

10

20

30

40

50

60

70

90



45

50

55

60

65

70

75

80

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s


A = 600 mm; Ta = 298 K; Tmax = 358 K





P-DSO-24-3

PC-Board


Diagrams





28/36




1 1 1

1 3

a/2

a

6 cm Footprint only

P-DSO-20-6-24-3-28-6

23 cm

P-DSO-20-1

-24-3-28-6

-20-6-28-6-24-3P-DSO-20-6

a/2

0.3

a0.375 0.375

0.3

L

Package e

1.27P-DSO-28-6

A

9.73

L

1.67

B

0.65

BA

e


1528

18.1-0.4

Index Marking

1)

2.4

5-0.1

0.2

2.6

5max.

-0.2

0.10.2 28x

8max.

+0

.09

0.2

3

7.6 1)-0.2

0.35 x 45

10.3

+0.8

0.30.41.27

+0.150.35 2)

GND GND

Dimensions in mm


40

Rthj-a

0

Zthj-a

10

2030

40

50

K/W

70

45

50

55

60

65K/W


61.4

56

51

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s



PC-Board


Diagrams

P-DSO-28-6

A = 600 mm; Ta = 298 K; Tmax = 349 K





Footprint only; Ta = 298 K; Tmax = 359 KA = 300 mm; Ta = 298 K; Tmax = 354 K


29/36


30/36


P-DSO-36-10 P-DSO-36-10

FR4; 47x50x1.5 mm; 70 CuA = 600 mm; 24.5 x 24.5 mm

FR4; 47x50x1.5 mm; 70 CuA = 300 mm; 16 x 19 mm

L

Package

Reflow soldering

e

0.65P-DSO-36-10

A

13.48

L

1.83

B

0.45

BA

e

+0

.07

-0.0

20.11.1 2.8

1.3 0

.25

36x0.25 M

1)

Heatsink0.95

14.2

+0.1

IndexMarking

15.9

181

0.1+0.130.25

0.65

3.5

max.

0

6.3

11

3.2

5

36 19

0.150.1

0.15

1 x 45

0.3

53

0.15

15.74 0.1

A

A

1)

B

0.25 B

(Heatsink)

GND

Dimensions in mm

Rthj-c = 2 K/W

20

Rthj-a

25

30

35

40

45

50

K/W

60

36.8

28.6

Zthj-a

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s

K/W

0

10

20

30

40

50

60

600 mm2

300 mm2



PC-Board


Diagrams

P-DSO-36-10

A = 600 mm; Ta = 298 K; Tmax = 398 K A = 300 mm; Ta = 298 K; Tmax = 427 K






31/36


1 1 1

1 36 cm Footprint only

23 cm

SCT595

INH QIQI

INH

INH I Q

GND

GND

GND

SCT595 SCT595

a0.375

0.3

a/2

0.375

0.3

a/2

a




Reflow soldering

acc. to+0.2

1.9

0.6 -0.05+0.1

+0.1-0.050.3

B

A

0.25 M B

1.1 max

2.6

max

10max

0.1 max

AM0.20

2.90.2

1.6

0.1DIN 6784

(2.2)

(0.3)

1.2 -0.05+0.1

4

321

5

0.95

-0.06+0.10.15

10max

0.95

1.9

0.5

2.9

1.4

0.8

GND

GND

Dimensions in mm


80

Rthj-a Zthj-a

600 mm2300 mm2

0

100

120

140

160

K/W

200

Footprint

20

40

6080

100

120

140

160

K/W

200

178.7

98.5

87

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s




SCT595-5-1

PC-Board


Diagrams

A = 600 mm; Ta = 298 K; Tmax = 315 K







32/36


1 1 1

1 36 cm Footprint only

23 cm

SOT223SOT223SOT223

III Q GND Q GND Q GND

a/2

a

0.3

a

a/2

0.3




GND

Reflow soldering

0.1

0.2

0.10.7

4

321

6.5

3

acc. to+0.2

DIN 6784

1.6 0.1

15m

ax

0.040.28

70.3

0.2

3.5

0.5

0.1 max

min

BM0.25

B

B

2.3

4.6

AM0.25

3.5

1.4

1.1

1.2

1.4

4.8

Dimensions in mm

60

Rthj-a Zthj-a

0

80

100

120

140

K/W

180

20

40

60

80

100

120

140

K/W

180



164.3

81.268

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s



PC-Board


Diagrams

SOT223-4-2

A = 600 mm; Ta = 298 K; Tmax = 332 K







33/36


P-TO252-3-1

1I Q

1

P-TO252-3-1

I Q

P-TO252-3-1

1I Q


a

a/2

a

a/2




5.4 0.1

1 3

-0.106.5+0.15

A

0.5

9.96

.22

-0.2

10.1

0.1

5

0.8

0.15

0.1

maxper side 0.75

2.28

4.57

+0.08-0.040.9

2.3 -0.10+0.05

B

min

0.5

1

0.11

+0.08-0.040.5

0...0.15

BA0.25 M 0.1

3x

(4.

17)

Reflow soldering

5.8

6.4

2.2

10.6

5.76

1.2

GND

Dimensions in mm

Rthj-c = 1.8 K/W

40

Rthj-a Zthj-a

600 mm2300 mm2

160

K/W

120

100

80

60

40

20

0

60

80

100

120

K/W

160

Footprint

143.9

78

54.7

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s




P-TO252-3-1

PC-Board


Diagrams

A = 600 mm; Ta = 298 K; Tmax = 353 K





Footprint only; Ta = 298 K; Tmax = 442 KA = 300 mm; Ta = 298 K; Tmax = 376 K


34/36


P-TO263-5-1

1 1 1


P-TO263-5-1 P-TO263-5-1a/2

a

a/2

a




Reflow soldering

A

8max.BA0.25 M 0.1

0.210

8.51)

81)

(15)

0.2

9.2

5

0.3

1

5x0.80.1

1 5

0.11.27

B

0.50.1

0.3

2.7

4.7

0.5

0.05GND

4x1.7

0.14.4

0.10.1

2.4 0.1

B

7.91

.10.6

10.8

9.4

16.15

4.6

Dimensions in mm

Rthj-c = 1.3 K/WRthj-a

0

Zthj-a

600 mm2

300 mm2Footprint

K/W

40

45

5055

60

65

70

75

85 90K/W

20

10

70

40

30

60

50

35

78.4

52.4

39

0A

100 200 300 400 500 600mm2

tp

10-3

10-2

10-1

100

101

102

103

s



PC-Board


Diagrams

P-TO263-5-1

A = 600 mm; Ta = 298 K; Tmax = 417 K







35/36


36/36

Qualitt hat fr uns eineumfassende Bedeutung.Wir wollen allen IhrenAnsprchen in derbestmglichen Weisegerecht werden. Es gehtuns also nicht nur um dieProduktqualitt unsereAnstrengungengelten gleichermaen derLieferqualitt und Logistik,

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Geisteshaltung unsererMitarbeiter. Total Qualityim Denken und Handelngegenber Kollegen,Lieferanten und Ihnen,unserem Kunden. UnsereLeitlinie ist, jede Aufgabemit Null Fehlern zulsen in offenerSichtweise auch ber deneigenen Arbeitsplatzhinaus und uns stndigzu verbessern.Unternehmensweitorientieren wir uns dabeiauch an top (TimeOptimized Processes), umIhnen durch grereSchnelligkeit denentscheidendenWettbewerbsvorsprungzu verschaffen.Geben Sie uns die Chance,

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Documents

Thermal Resistance - Theory and Practice