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The pixel module of the new Inner Tracking System of ALICE at LHC
Benedetto Di Ruzza for the ALICE Collaboration
14th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD16)Siena, 5 October 2016
Department of Physics and Astronomy “Galileo Galilei”, University of Padova & INFN
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Outline
● Alice ITS Upgrade design motivations.● Alice ITS Upgrade elements overview.● ITS Upgrade Structure overview:
Alpide Chip,Inner and Outer Barrel (OB) Modules and Staves.
● The OB Modules test set-up for electrical characterization.● Some prototypes results.● Project Timeline.
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ALICE: A Large Ion Collider Experiment
Barrel Solenoid Field: 0.5 TMuon Arm Dipole Field: 3 T
Present ITS:2 Layers Silicon Strip Detector (SSD)2 Layers Silicon Drift Detector (SDD)2 Layers Silico Pixel Detector (SPD)
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ALICE Physics Objectives
One of the key decay channel to study:OPEN CHARM
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● Improve impact parameter resolution by a factor ~3 in r and φ,~5 in z at pT=500MeV/c.
- increase granularity: 6 layers ➔7 pixel layers
- get closer to IP: from present 39mm ➔ 22mm for innermost layer.
- reduce material budget: present ~1.14% X0 /layer ➔
~0.3% X0 (inner layers), ~0.8% X0 (middle and outer layers).
- reduce pixel size:
from present 50x425μm2 ➔30x30μm2
● Improve readout rate: - increase readout rate of Pb-Pb from present
1kHz up to 100 kHz and 400kHz for pp.
● Fast insertion and removal:- possibility to replace non-functioning detector
modules during yearly shutdown.
ITS Upgrade Design Objectives
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ITS Upgrade Overview:
7 layers:
● 2 Outer Barrel Layers
● 2 Middle Barrel Layers
● 3 Inner Barrel Layers
12.5 Gigapixels~ 10 m2 active surface
ITS Upgrade Coverage Requirements η coverage: |η| ≤ 1.22 r coverage: 22 – 400 mm z coverage: Inner Layers L = 290 mm
Middle Layers L = 900 mm Outer Layers L = 1500 mm
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Layer # 6 5 4 3 2 1 0n. of Chip 9408 8232 3360 2688 180 144 108n. of Modules 672 588 240 192 20 16 12n. of Staves 48 42 30 24 20 16 12
192 staves: 90 (OL) 54 (ML), 48 (IL)
ITS Upgrade Overview:
Staves are composed by two type of modules:● Inner Barrel:
modules of 9 Chips● Outer Barrel (Outer Layers and Middle Layers):
Modules of 14 Chips
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Building blocks
OB/MB Module 7+7 chips
ALPIDE Chip:1024x512 pixels (30x15 mm2)
OB staves: 7+7 modulesMB staves: 4+4 modules
MAPS Pixel (30x30μm2)
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Building blocks
OB/MB Module 7+7 chips
ALPIDE Chip:1024x512 pixels (30x15 mm2)
OB staves: 7+7 modulesMB staves: 4+4 modules
MAPS Pixel (30x30μm2)
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The ALPIDE Chip
Chip realized with MAPS Technologies:
Digital Readout
Pixel Structure1024 x 512 Pixels
3 mm dead area
12 mm
30 mm
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ALPIDE Chip Design requirements
Pixel Chip Requirements
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Staves And Modules
One Inner Barrel (IB) STAVE = One Inner Barrel Module Inner Barrel Module: 9 chip, all of them with the readout connectedwith external DAQ.
One Outer Barrel (OB)Stave = 14 Outer Barrel Module (OB-HIC)Outer Barrel Module: two rows of 7+7 chips.In every row only one chip is connected with the external DAQ (Master), the other 6 (Slaves) chips are connected only to a master.
OB MODULE
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Chip Connections inside Modules
Inner Barrel Module External Lines:
One Control LineOne Clock LineNine Serial Data lines
Outer Barrel Module External Lines:
One + One Control LineOne + One Clock LineOne + One Serial Data lines
Two Masters every module
Hit Density ~ 150 hit/cm2
Hit Density ~ 1 hit/cm2
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Module Assembling Procedure
● Every chip will be aligned with a automatic machine within a space precision of about 5 μm, ● then the FPC will be glued on top of them,● after that the connection betweenChip pads and FPC will be realized with wire bonding.
Assembly Table
Chip Tray
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Module wire bonding procedure
FlexiblePrinted Circuit
Glue Chip Pads
FPC - Chip wire bonding detail
Flexible Printed Circuit (FPC)
Holes for wire bonding
Glue (Ecobond 45)
Assembly Table
FPC
Glue
Silicon
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Module ready for characterization
Control, Clock and Serial Data Lines
POWER Lines:Analog, Digital and Ground
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OB Module test set-up
Communication Board(MOSAIC Board)
Module under test(FPC side)
Test software (MATE package)
Data cables
Power Cables
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Outer Barrel modules Status
OB Modules Prototypes So far a series of OB modules prototypes was built using the Prototype ALPIDE (pALPIDE) Version 3 chip:6 modules and 1 OB stave (with 2 modules)
These prototypes were used to define the building procedure for modules and staves
The pALPIDE chip contains a self-injection charge feature that allow to test the read-out chain of every single pixel. This feature, handled by the MATE framework, is used● to check the inter-modules interconnections (wire bonding integrity)● to map dead pixels● to perform the full module readout rates characterization
Next steps:Pre-series production is starting (~20 units) with final ALPIDE chips in Oct – Dec 2016
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Some prototype results:fast test of global module status
Unconnected/Shorted chips
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Some prototype results:single chip details
With this setup in ~30 minutes is possible to perform the full module electrical characterization and the full map of bad pixel.
Broken lines / bad pixels map
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Some prototype results:average thresholds and noise
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ITS Upgrade Project Timeline
LS2
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Conclusions
The ALICE ITS upgrade program requires, between the other things, the mass production of ~ 1700 Outer Barrel modules. A procedure was defined in order to do a fast electrical characterization of the produced modules.
This procedure will be implemented in the production of the next final version of the modules.
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References
ALICE ITS upgrade TDR:https://cds.cern.ch/record/1625842?ln=en
The upgrade of the ALICE ITS by Stefania Beole, VERTEX 2016
https://indico.cern.ch/event/452781/contributions/2297487/attachments/1343570/2024447/VERTEX2016_beole.pdf
MOSAIC Board description by Giuseppe De Robertis, MPGD 2015 Conferece, Trieste 12-15 October 2015https://agenda.infn.it/getFile.py/access?contribId=86&sessionId=8&resId=1&materialId=paper&confId=8839
