The Modular Multilevel DC Converters for MVDC and HVDC

The Modular Multilevel DC Converters for

MVDC and HVDC Applications

Xin Xiang

Department of Electrical and Electronic Engineering

Imperial College London

This dissertation is submitted for the degree of

Doctor of Philosophy

Jan. 2019

Declaration

I hereby declare that except where specific reference is made to the work of others, the contents

of this dissertation are original and have not been submitted in whole or in part for consideration

for any other degree or qualification in this, or any other University. This dissertation is the

result of my own work and includes nothing which is the outcome of work done in

collaboration, except where specifically indicated in the text. The work within was conducted

from October 2014 to October 2018 under the supervision of Professor Timothy C Green at

Imperial College London.

The copyright of this thesis rests with the author and is made available under a Creative

Commons Attribution Non-Commercial No Derivatives licence. Researchers are free to copy,

distribute or transmit the thesis on the condition that they attribute it, that they do not use it for

commercial purposes and that they do not alter, transform or build upon it. For any reuse or

redistribution, researchers must make clear to others the licence terms of this work.

Xin Xiang

Jan. 2019

Acknowledgements

I would like to express the deepest gratitude to my supervisor Prof. Timothy C. Green for the

excellent guidance, invaluable insights and fantastic opportunities over the past four years,

which greatly broadened my horizon and knowledge.

Special thanks to Dr. Yunjie Gu for the numerous discussion and inspiration in my whole

Master and Ph.D. research career. Special thanks to Dr. Xiaotian Zhang for the valuable support

and advice on the lab-scale converter prototypes.

Thanks to the engineers and researchers from State Grid and Alstom Grid for providing me

with their industrial view and suggestion on this work.

Special thanks to my viva examiners, Prof. Jon C. Clare and Prof. Paul D. Mitcheson, for giving

me excellent advice on this thesis, and I really enjoyed the productive and fruitful discussion.

Thanks to all of my friends and colleagues at the Control and Power Research Group in

Imperial College, in particular Dr. Adria Junyent-Ferre, Dr. Michael Merlin, Dr. Thomas Luth,

Dr. Paul Judge, Dr. Geraint Chaffey, Mr. James Wylie, Mr. Thiago Mendonca, Mr. Yu Sang,

Mr. Joan Marc Rodriguez-Bernuz, Mr. Juilecio Santos-Laranjeira, Mr. Yitong Li, Mr. Sohail

Mian, Mr. Caspar Collins, Dr. Richard Silversides, Dr. Philip Clemow, Dr. Nathaniel Bottrell,

Dr. Alwyn Elliot, Dr. Javier Pereda-Torres, Dr. Caitrona Sheridan, Dr. Claudia Spallarossa,

Miss Linnea Luuppala, Dr. Tony Beddard, Dr. Yousef Pipelzadeh and Dr. Mark Collins in the

Maurice Hancock Smart Energy Laboratory.

Thanks to all of my other friends in both UK and China for making these four years so

enjoyable and unforgettable.

Finally, I would like to express my utmost thanks to my beloved parents for their immense

support and encourage over these four years.

Abstract

A dc structure for an electrical power system is seen to have important advantages over an ac

structure for the purpose of renewable energy integration and for expansion of transmission

and distribution networks. There is also much interest and strong motivation to interconnect

the existing point-to-point dc links to form multi-terminal and multi-voltage dc networks,

which can make full use of the benefits of a dc scheme across various voltage levels and also

increase the flexibility and ease the integration of both centralized and distributed renewable

energy.

This thesis investigates both high step-ratio dc-dc conversion to interface dc systems with

different voltage levels and low step-ratio dc-dc conversion to interconnect dc systems with

similar but not identical voltages (still within the same voltage level). The research work explores

the possibility of combining the relatively recent modular multilevel converter (MMC)

technology with the classic dc-dc circuits and from this proposes several modular multilevel

dc converters, and their associated modulation methods and control schemes to operate them,

which inherit the major advantages of both MMC technologies and classic dc-dc circuits. They

facilitate low-cost, high-compactness, high-efficiency and high-reliability conversion for the

medium voltage level and high voltage level dc network interconnection.

For medium voltage level cases, this thesis extends the classic LLC dc-dc circuit by introducing

MMC-like stack of sub-modules (SMs) in place of the half-bridge or full-bridge inverter in the

original configuration. Two families of resonant modular multilevel dc converters (RMMCs)

are proposed covering high step-ratio and low step-ratio conversion respectively. A phase-shift

modulation scheme is further proposed for these RMMCs that creates an inherent feature of

balancing SM capacitor voltages, provides a high effective operating frequency for reducing

system footprint and offers a wide operating range for flexible conversion.

For high voltage level cases requiring a high step-ratio conversion, a modular multilevel dc-

ac-dc converter based on the single-active-bridge or dual-active-bridge structure is explored.

The operating mode developed for this converter employs a near-square-wave ac current in

order to decrease both the volt-ampere rating requirement for semiconductor devices and the

energy storage requirement for SM capacitors. For low step-ratio cases, a single-stage modular

multilevel dc-dc converter based on a buck-boost structure is examined, and an analysis method

is created to support the choice of the circulating current frequency for minimum current

stresses and reactive power losses.

Theoretical analysis of and operating principles for all of these proposed modular multilevel

dc converters, together with their associated modulation methods and control schemes, are

verified by both time-domain simulation at full-scale and experimental tests on down-scaled

prototypes. The results demonstrate that these medium voltage and high voltage dc-dc

converters are good candidates for the interconnection of dc links at different voltages and

thereby make a contribution to future multi-terminal and multi-voltage dc networks.

Contents

Contents ........................................................................................................................................................ ix

List of Figures ............................................................................................................................................. xiii

List of Tables ............................................................................................................................................. xvii

Abbreviations .............................................................................................................................................. xix

Nomenclature .............................................................................................................................................. xxi

Chapter 1 Introduction ............................................................................................................................ 1

1.1 Background .................................................................................................................................... 1

1.2 Multiple Voltage Power System .................................................................................................... 2

1.2.1 High Voltage Transmission System ....................................................................................... 3

1.2.2 Low Voltage Distribution System ......................................................................................... 5

1.2.3 Medium Voltage Collection and Distribution System ........................................................... 7

1.3 Multi-terminal and Multi-Voltage DC Networks ......................................................................... 10

1.4 Motivations and Challenges for DC-DC Converters ................................................................... 14

1.5 Research Questions ...................................................................................................................... 16

1.6 Thesis Outline .............................................................................................................................. 17

1.7 Author’s Publications Based on This Work ................................................................................. 19

1.7.1 Journal Papers ...................................................................................................................... 19

1.7.2 Conference Papers ............................................................................................................... 20

1.7.3 Role of Main Co-Authors .................................................................................................... 21

Chapter 2 Literature Review and Technology Current Status .............................................................. 23

2.1 DC-DC Converters in the Low Voltage Level ............................................................................. 23

2.1.1 Non-isolated Circuits ........................................................................................................... 23

2.1.2 Isolated Circuits ................................................................................................................... 25

2.2 DC-DC Converters in the Medium Voltage Level ....................................................................... 27

2.2.1 Cascaded Configuration ....................................................................................................... 27

2.2.2 Switching Capacitor Configuration ..................................................................................... 27

2.2.3 Multilevel Configuration ..................................................................................................... 28

2.2.4 Modular Configuration ........................................................................................................ 29

2.2.5 Resonant Configuration ....................................................................................................... 31

2.3 DC-DC Converters in the High Voltage Level ............................................................................ 32

2.3.1 Front-to-Front Configuration ............................................................................................... 38

2.3.2 Direct-Chain-Link Configuration ........................................................................................ 40

2.4 Chapter Summary......................................................................................................................... 41

Chapter 3 High Step-ratio Resonant Modular Multilevel DC Converter for MVDC Applications ..... 43

3.1 Topology Derivation and Description .......................................................................................... 44

3.2 Operating Principle and Flexible Phase-shift Modulation ........................................................... 45

3.2.1 Basic Operation with Highest Step-ratio Conversion .......................................................... 48

3.2.2 General Operation with Flexible Modulation ...................................................................... 50

3.3 Circuit Performance Analysis ...................................................................................................... 55

3.3.1 SM Stack Rating .................................................................................................................. 56

3.3.2 Wide Step-ratio Range in Operation .................................................................................... 66

3.3.3 Inherent Voltage-balancing Capability ................................................................................ 67

3.3.4 DC Fault Management ......................................................................................................... 69

3.3.5 Challenges and Limitations.................................................................................................. 70

3.4 Variety of Configurations ............................................................................................................ 71

3.4.1 Bipolar and Monopolar Configurations ............................................................................... 71

3.4.2 Modular Configurations ....................................................................................................... 73

3.5 Derivative Topologies .................................................................................................................. 79

3.6 Medium Voltage Application Examples ...................................................................................... 81

3.6.1 Simulation Results for Single Circuit .................................................................................. 81

3.6.2 Simulation Results for Further Configurations .................................................................... 90

3.7 Experiment Results Analysis ....................................................................................................... 96

3.7.1 Highest Ratio Conversion .................................................................................................... 97

3.7.2 Flexible Modulation ............................................................................................................. 98

3.7.3 Inherent Voltage-balancing Capability .............................................................................. 102

3.7.4 Linearity of Step-ratio Values ............................................................................................ 104

3.8 Chapter Summary....................................................................................................................... 104

Chapter 4 Low Step-ratio Resonant Modular Multilevel DC Converter for MVDC Applications .... 107

4.1 Evolution from High-step Ratio RMMC ................................................................................... 108

4.2 Operating Principle and Modulation Scheme ............................................................................ 110

4.2.1 Basic Operation with Lowest Step-ratio Conversion ......................................................... 112

4.2.2 General Operation with Flexible Modulation .................................................................... 114

4.3 SM Stack Rating ........................................................................................................................ 116

4.3.1 Stack Semiconductor Volt-ampere Rating ......................................................................... 118

4.3.2 Stack Capacitive Energy Storage ....................................................................................... 121

4.4 Variety of Configurations .......................................................................................................... 124

4.5 Medium Voltage Application Examples .................................................................................... 126

4.5.1 Simulation Results for Single Circuit ................................................................................ 126

4.5.2 Simulation Results for Further Configurations .................................................................. 133

4.6 Experimental Results Analysis................................................................................................... 135

4.6.1 Lowest Ratio Conversion ................................................................................................... 135

4.6.2 Flexible Modulation ........................................................................................................... 137

4.6.3 Inherent Voltage-balancing Capability .............................................................................. 139

4.6.4 Linearity of Step-ratio Values ............................................................................................ 141

4.7 Chapter Summary....................................................................................................................... 141

Chapter 5 High Step-ratio Modular Multilevel DC-AC-DC Converter for HVDC Applications ...... 143

5.1 Topology Derivation and Description ........................................................................................ 144

5.2 Operating Principle and Near-square-wave Modulation ............................................................ 145

5.3 Energy Management and Control Solution ................................................................................ 152

5.4 Circuit Performance Analysis .................................................................................................... 156

5.4.1 SM Stack Rating ................................................................................................................ 156

5.4.2 DC Link Capacitor Sizing .................................................................................................. 161

5.4.3 Wide Step-Ratio Range in Operation ................................................................................ 162

5.4.4 Soft-Switching Operation .................................................................................................. 163

5.4.5 Challenges and Limitations................................................................................................ 164

5.5 Assessment of Simulation Analysis ........................................................................................... 165

5.5.1 Near-square-wave and Soft-switching ............................................................................... 167

5.5.2 Energy Management and Voltage Balancing ..................................................................... 170

5.5.3 Reversal Power Flow Operation ........................................................................................ 171


5.6.1 Near-square-wave and Soft-switching ............................................................................... 173

5.6.2 Energy Management and Voltage Balancing ..................................................................... 174

5.6.3 CSM Operation and VSM Operation ................................................................................. 176

5.7 Chapter Summary....................................................................................................................... 177

Chapter 6 Low Step-ratio Modular Multilevel DC-DC Converter for HVDC Applications.............. 179

6.1 Circuit Operation and Current Loop Analysis ........................................................................... 180

6.2 Equivalent Circuit and Choice of Frequency ............................................................................. 183

6.2.1 Equivalent circuit of DC Component ................................................................................ 184

6.2.2 Equivalent circuit of AC Component ................................................................................ 185

6.2.3 Choice of Circulating Current Frequency .......................................................................... 186

6.3 Further Application for Derivative Topologies .......................................................................... 191

6.4 Assessment of Simulation Analysis ........................................................................................... 196

6.4.1 Symmetrical Conversion .................................................................................................... 197

6.4.2 Asymmetrical Conversion ................................................................................................. 199

6.4.3 Bipolar Conversion ............................................................................................................ 201


6.6 Appendix .................................................................................................................................... 207

6.6.1 General Analysis for Buck-Boost Configuration ............................................................... 207

6.6.2 Asymmetrical Voltage Conversion for Buck-Boost Configuration ................................... 207

6.6.3 General Analysis for Buck Configuration ......................................................................... 208

6.7 Chapter Summary....................................................................................................................... 208

Chapter 7 Conclusion ......................................................................................................................... 211

7.1 Resonant Modular Multilevel DC Converters for MVDC Applications .................................... 211

7.2 Non-Resonant Modular Multilevel DC Converters for HVDC Applications ............................ 213

7.3 Future Work ............................................................................................................................... 215

Reference .................................................................................................................................................... 219

Appendix ......................................................................................................................................................... 1

A.1 Resonate Modular Multilevel DC Converter Prototypes .................................................................. 1

A.2 Non-Resonate Modular Multilevel DC Converter Prototypes ......................................................... 2

List of Figures

Figure 1.1. Change in power generation. ........................................................................................................ 2

Figure 1.2. HVAC transmission infrastructure. .............................................................................................. 3

Figure 1.3. HVDC transmission infrastructure. .............................................................................................. 4

Figure 1.4. Cost comparison between HVAC and HVDC. ............................................................................. 5

Figure 1.5. LVAC distribution infrastructure. ................................................................................................ 6

Figure 1.6. LVDC distribution infrastructure. ................................................................................................ 7

Figure 1.7. MVAC collection and distribution infrastructure. ........................................................................ 9

Figure 1.8. MVDC collection and distribution infrastructure. ........................................................................ 9

Figure 1.9. Multi-terminal dc network with identical voltage. ..................................................................... 12

Figure 1.10. Multi-terminal dc network with similar but not identical voltages ........................................... 12

Figure 1.11. Multi-voltage dc network with HVDC and MVDC infrastructures. ........................................ 13

Figure 1.12. Multi-voltage dc network with MVDC and LVDC infrastructures. ......................................... 14

Figure 2.1. Classic buck converter. ............................................................................................................... 24

Figure 2.2. Classic boost converter. .............................................................................................................. 24

Figure 2.3. Classic buck-boost converter. ..................................................................................................... 24

Figure 2.4. Full bridge configuration of single-active-bridge and dual-active-bridge converter. ................. 26

Figure 2.5. Full bridge configuration of LLC resonant converter. ................................................................ 26

Figure 2.6. Cascaded configuration .............................................................................................................. 27

Figure 2.7. Switching capacitor configuration .............................................................................................. 28

Figure 2.8. Multilevel boost converter. ......................................................................................................... 29

Figure 2.9. Multiple module configuration of full-bridge bidirectional DAB and LLC. .............................. 30

Figure 2.10. Resonant dc transformer. .......................................................................................................... 32

Figure 2.11. Half-bridge SM based modular multilevel converter ............................................................... 33

Figure 2.12. Thyristors-based line-commutated converter ........................................................................... 34

Figure 2.13. IGBT-based self-commutated two-level converter................................................................... 34

Figure 2.14. Variations of the basic MMC ................................................................................................... 37

Figure 2.15. Front-to-front based MMCs for dc-ac-dc conversion.. ............................................................. 39

Figure 2.16. Direct-chain-link based MMCs for dc-dc conversion. ............................................................. 41

Figure 3.1. Basic high step-ratio resonant modular multilevel dc converter. ............................................... 45

Figure 3.2. Operation waveforms of the resonant tank. ................................................................................ 47

Figure 3.3. Operation waveforms with 𝑦 = 4, 𝑥 = 5,𝑁 = 5. ....................................................................... 49

Figure 3.4. SM operation waveforms.. ......................................................................................................... 49



Figure 3.7. Comparison for operation required volt-ampere rating. ............................................................. 60

Figure 3.8. Comparison for operation required volt-ampere rating. ............................................................. 60

Figure 3.9. Comparison for stack energy deviation and operation required capacitive energy storage. ....... 65

Figure 3.10. Comparison for stack energy deviation and operation required capacitive energy storage. ..... 65

Figure 3.11. Step-ratio range of the basic high step-ratio RMMC. ............................................................... 66

Figure 3.12. Step-ratio range of the basic high step-ratio RMMC. ............................................................... 67

Figure 3.13. Analysis of inherent voltage-balancing capability. .................................................................. 69

Figure 3.14. Bipolar configuration of the basic high step-ratio RMMC. ...................................................... 72

Figure 3.15. Monopolar configuration of the basic high step-ratio RMMC. ................................................ 73

Figure 3.16. Multi-module configuration of the basic high step-ratio RMMC. ............................................ 74

Figure 3.17. Four-module example of the enhanced multi-module configurations for module transformer

insulation. ...................................................................................................................................................... 76

Figure 3.18. Multi-module configuration of the bipolar high step-ratio RMMC.......................................... 77

Figure 3.19. Multi-module configuration of the monopolar high step-ratio RMMC. ................................... 78

Figure 3.20. Multi-module configuration of the full-bridge high step-ratio RMMC. ................................... 79

Figure 3.21. LLC-based RMMC. .................................................................................................................. 79

Figure 3.22. Buck-based RMMC. ................................................................................................................. 80

Figure 3.23. Buck-Boost-based RMMC. ...................................................................................................... 80

Figure 3.24. Flyback-based RMMC. ............................................................................................................ 80

Figure 3.25. Multi-voltage dc network with MVDC and LVDC infrastructures. ......................................... 82

Figure 3.26. Simulation results for the modulation with 𝑦 = 4 and 𝑥 = 5 of the basic high step-ratio

RMMC. ......................................................................................................................................................... 84


RMMC in reverse power flow. ..................................................................................................................... 86


RMMC. ......................................................................................................................................................... 88


RMMC. ......................................................................................................................................................... 89

Figure 3.30. Simulation results for the bipolar configuration. ...................................................................... 92

Figure 3.31. Simulation results for the monopolar configuration. ................................................................ 93

Figure 3.32. Simulation results for the multi-module configuration. ............................................................ 96

Figure 3.33. Experimental results for the modulation with 𝑦 = 4 and 𝑥 = 5. .............................................. 98

Figure 3.34. Experimental results for the modulation with 𝑦 = 3 and 𝑥 = 4. .............................................. 99

Figure 3.35. Experimental results for the modulation of 𝑦 = 2 and 𝑥 = 3. ............................................... 100

Figure 3.36. Experimental results for the modulation with 𝑦 = 1 and 𝑥 = 5. ............................................ 101

Figure 3.37. Experimental results for the modulation of 𝑦 = 1 and 𝑥 = 4. ............................................... 102

Figure 3.38. Experimental results of average voltages of each SM capacitor during ten 2π cycles under

different modulation cases. ......................................................................................................................... 103

Figure 3.39. Experimental results of high-side voltages versus low-side voltage under different modulation

cases. ........................................................................................................................................................... 104

Figure 4.1. Basic high step-ratio RMMC. ................................................................................................... 108

Figure 4.2. Low step-ratio RMMC. ............................................................................................................ 109

Figure 4.3. Voltage waveforms with 𝑦 = 4, 𝑥 = 5,𝑁 = 5. ........................................................................ 112

Figure 4.4. Current flow with 𝑦 = 4, 𝑥 = 5,𝑁 = 5. ................................................................................... 113

Figure 4.5. Voltage waveforms with 𝑦 = 3, 𝑥 = 5,𝑁 = 5. ........................................................................ 115

Figure 4.6. Current flow with 𝑦 = 3, 𝑥 = 5,𝑁 = 5. ................................................................................... 116

Figure 4.7. Illustration of the power conversion process. ........................................................................... 118

Figure 4.8. Comparison for operation required volt-ampere rating. ........................................................... 120

Figure 4.9. Comparison for stack energy deviation and operation required capacitive energy storage. ..... 123

Figure 4.10. Bipolar configuration of the basic low step-ratio RMMC. ..................................................... 124

Figure 4.11. Full-bridge push-pull configuration of the basic low step-ratio RMMC. ............................... 125

Figure 4.12. Bipolar full-bridge configuration of the basic low step-ratio RMMC. ................................... 126

Figure 4.13. Simulation results for the modulation with 𝑦 = 4 and 𝑥 = 5 of the basic low step-ratio

RMMC ........................................................................................................................................................ 129


RMMC in reverse power flow. ................................................................................................................... 130


RMMC ........................................................................................................................................................ 132

Figure 4.16. Simulation results for the bipolar full-bridge configuration.. ................................................. 134

Figure 4.17. Experimental results for the modulation with 𝑦 = 4 and 𝑥 = 5. ........................................... 137

Figure 4.18. Experimental results for the modulation with 𝑦 = 3 and 𝑥 = 5. ........................................... 139


different modulation cases. ......................................................................................................................... 140

Figure 4.20. Experimental results of high-side voltages versus low-side voltage for different modulation

cases. ........................................................................................................................................................... 141

Figure 5.1. High step-ratio modular multilevel dc-ac-dc converter. ........................................................... 145

Figure 5.2. Voltage and current waveforms in one operation cycle. .......................................................... 146

Figure 5.3. Equivalent circuits and operation analysis. .............................................................................. 149

Figure 5.4. Energy management of dc components. ................................................................................... 154

Figure 5.5. Energy management of ac components. ................................................................................... 154

Figure 5.6. Control scheme for this high step-ratio modular multilevel dc-ac-dc converter. ..................... 155

Figure 5.7. Comparison for operation required volt-ampere rating. ........................................................... 158

Figure 5.8. Comparison for stack energy deviation and operation required capacitive energy storage with

different modulation schemes. .................................................................................................................... 160

Figure 5.9. Comparison for stack energy deviation and operation required capacitive energy storage with

different operation frequencies. .................................................................................................................. 160

Figure 5.10. DC link capacitor energy deviation. ....................................................................................... 162

Figure 5.11. Step-ratio range. ..................................................................................................................... 163

Figure 5.12. Multi-voltage dc network with HVDC and MVDC infrastructures. ...................................... 165

Figure 5.13. Simulation results of the stack voltage and current.. .............................................................. 168

Figure 5.14. Simulation results of the rectifier voltage and current. ........................................................... 169

Figure 5.15. Simulation results of the energy balance.. .............................................................................. 171

Figure 5.16. Simulation results of the stack voltage and current in reverse power flow.. .......................... 172

Figure 5.17. Experimental results of the SM stack, arm inductor and rectifier voltages and currents........ 174

Figure 5.18. Experimental results of the energy balance. ........................................................................... 175

Figure 5.19. Experimental results of different operation schemes .............................................................. 176

Figure 6.1. Current loops in the standard single-phase dc-ac MMC. .......................................................... 181

Figure 6.2. Current loops in the proposed modular multilevel dc-dc conversion. ...................................... 182

Figure 6.3. DC component analysis and comparison. ................................................................................. 184

Figure 6.4. Equivalent circuit analysis of the proposed direct-chain-link negative-output buck-boost

converter.. ................................................................................................................................................... 185

Figure 6.5. AC component analysis and comparison. ................................................................................. 186

Figure 6.6. Current loops in the direct-chain-link positive-output buck-boost converter ........................... 191

Figure 6.7. Equivalent circuit analysis of the direct-chain-link positive-output buck-boost converter.. .... 192

Figure 6.8. Current loops in the direct-chain-link buck converter .............................................................. 193

Figure 6.9. Equivalent circuit analysis of the direct-chain-link buck converter ......................................... 193

Figure 6.10. Application examples for different direct-chain-link dc-dc converters.. ................................ 194

Figure 6.11. Derivative arrangements and topologies ................................................................................ 196

Figure 6.12. Simulation results in the symmetrical conversion.. ................................................................ 199

Figure 6.13. Simulation results in the asymmetrical conversion. ............................................................... 201

Figure 6.14. Simulation results in the bipolar conversion .......................................................................... 202

Figure 6.15. Experimental results of the stack voltages and currents in the symmetrical conversion. ....... 204

Figure 6.16. Experimental results of average voltages of each SM capacitors during ten ac cycles in the

symmetrical conversion. ............................................................................................................................. 204

Figure 6.17. Experimental results of the variation of the step-ratio. ........................................................... 206


asymmetrical conversion period. ................................................................................................................ 206

Figure 6.19. Experimental results of full range operation at various step-ratio conversion. ...................... 206

Figure A.1. High step-ratio RMMC prototype with TI-DXP controller system. ............................................ 1

Figure A.2. Low step-ratio RMMC prototype with TI-DXP controller system. ............................................ 2

Figure A.3. High step-ratio modular multilevel dc-ac-dc converter prototype with OPAL-RT controller

system. ............................................................................................................................................................ 3

Figure A.4. Low step-ratio modular multilevel dc-dc converter prototype with OPAL-RT controller

system. ............................................................................................................................................................ 3

List of Tables

Table 3.1. Simulation parameters of the basic high step-ratio RMMC for application examples ................ 82

Table 3.2. Power device losses analysis for the highest step-ratio conversion case ..................................... 89

Table 3.3. Experimental prototype parameters of the basic high step-ratio RMMC .................................... 97

Table 4.1. Simulation parameters of the basic low step-ratio RMMC for application examples ............... 127

Table 4.2. Power device losses analysis for the lowest step-ratio conversion case .................................... 132

Table 4.3. Experimental prototype parameters of the basic low step-ratio RMMC ................................... 135

Table 5.1. Simulation parameters of the high step-ratio modular multilevel dc-ac-dc converter ............... 166

Table 5.2. Experimental prototype parameters of the high step-ratio dc-ac-dc converter .......................... 172

Table 6.1. Simulation parameters of the low step-ratio direct-chain-link negative-output buck-boost

converter ..................................................................................................................................................... 197

Table 6.2. Experimental prototype parameters of the low step-ratio direct-chain-link negative-output buck-

boost converter. ........................................................................................................................................... 203

Abbreviations

HVAC High Voltage Alternating Current

HVDC High Voltage Direct Current

MVAC Medium Voltage Alternating Current

MVDC Medium Voltage Direct Current

LVAC Low Voltage Alternating Current

LVDC Low Voltage Direct Current

IGBT Insulated-Gate Bipolar Transistor

MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor

SAB Single Active Bridge

DAB Dual Active Bridge

MMC Modular Multilevel Converter

LCC Line-Commutated Converter

CSC Current Source Converter

VSC Voltage Source Converter

AAC Alternate Arm Converter

FTF Front-to-Front

BTB Back-to-Back

DCL Direct-Chain-Link

RMMC Resonant Modular Multilevel DC Converter

CCM Continuous Current Mode

DCM Discontinuous Current Mode

SQW Square Wave

PWM Pulse Width Modulation

NLM Nearest Level Modulation

RMS Root-Means-Square

PI Proportional–integral

ZCS Zero-current-switching

ZVS Zero-voltage-switching

Nomenclature

Common Symbols

𝑃𝑇 Total power throughput

𝑅 Overall step-ratio between high-side voltage and low-side voltage

𝑟𝑆 SM stack modulation ratio

𝑟𝑇 Transformer turns-ratio

𝑣𝐻𝑆,𝐿𝑆 High-side and low-side dc terminal voltages

𝑣𝑆𝑇 SM stack voltage

𝑣𝑆𝑀 Single SM voltage

𝑣𝐶 Single SM capacitor voltage

𝑣𝑃,𝑆 Transformer primary-side and secondary-side voltages

𝑖𝐻𝑆,𝐿𝑆 High-side and low-side dc terminal currents

𝑖𝑆𝑇 SM stack current

𝑖𝑃,𝑆 Transformer primary-side and secondary-side currents

𝑁 SM total number

𝑓𝑠 Switching frequency

𝑇𝑠 Switching cycle

𝛾 Maximum ripple percentage for SM capacitor voltage

𝑆𝑆𝑇 Normalized value of stack semiconductor volt-ampere rating

𝑅𝑆𝑆𝑇 Normalized value of required stack semiconductor volt-ampere rating

𝐸𝑆𝑇 Normalized value of stack capacitive energy storage

𝑅𝐸𝑆𝑇 Normalized value of required stack capacitive energy storage

∆𝐸𝑆𝑇 Single stack energy deviation

𝑋−𝑑𝑐 Subscript for dc component of 𝑋

𝑋−𝑎𝑐 Subscript for ac component of 𝑋

𝑋−𝑚𝑎𝑥 Subscript for maximum value of 𝑋

𝑋−𝑚𝑖𝑛 Subscript for minimum value of 𝑋

𝑋−𝑝𝑡𝑝 Subscript for peak-to-peak value of 𝑋

𝑋∗ Superscript for reference value of 𝑋

𝑋𝑘 Superscript for value of 𝑋 for kth SM in one single stack

𝑋𝑗 Superscript for value of 𝑋 for jth stack

𝑋𝑗𝑘 Superscript for value of 𝑋 for kth SM in jth stack

⌊𝑋⌋ Floor (the largest integer less than or equal to 𝑋)

Symbols for Chapters 3 and Chapter 4

𝑃𝐷𝑇 Power directly transferred between two dc terminals

𝑃𝑆𝑇 Power processed through the SM stack

𝑣𝐶 Average value of all the SM capacitor voltages

𝑣𝑢𝑝,𝑙𝑜𝑤 Upper switch voltage and lower switch voltage of the SM

𝑣𝐿𝑚 Magnetizing inductor voltage

𝑣𝑏 DC bias capacitor voltage

𝑣𝑑𝑖𝑓 Differential capacitor voltage

𝑣𝑆1,𝑆2,𝑆3,𝑆4 Rectifier voltages

𝑖𝑢𝑝,𝑙𝑜𝑤 Upper switch current and lower switch current of the SM

𝑖𝐿𝑚 Magnetizing inductor current

𝑖𝑟 Resonant current

𝑖𝑆1,𝑆2,𝑆3,𝑆4 Rectifier currents

𝑦, 𝑥 Positive stage and negative stage SM number

𝑁𝑆𝑇 Total number of SM stacks

𝑁𝑃 Total pair number of the module circuits

𝑓𝑒 Effective frequency

𝑓𝑝,𝑛 Positive stage and negative stage resonant frequency

𝑇𝑒 Effective cycle

Symbols for Chapter 5

𝑣𝐶𝑇,𝐶𝐵 High-side dc link capacitor voltages

𝑣𝐿𝑇,𝐿𝐵 Top arm and bottom arm inductor voltages

𝑣𝐷1,𝐷2,𝐷3,𝐷4 Rectifier diode voltages

𝑖𝐶𝑇,𝐶𝐵 High-side dc link capacitor currents

𝑖𝐷1,𝐷2,𝐷3,𝐷4 Rectifier diode currents

∆𝑖𝑑𝑐,𝑎𝑐 Extra dc and ac current components for stack energy balancing

𝑛𝑇,𝐵 SM number in top stack and bottom stack

𝑓𝑜 Operation frequency

𝑓𝑟 SM rotation and selection frequency

𝑇𝑜 Operation cycle

𝐷 Duty-cycle of the square-wave current

∆𝐷 Duty-cycle adjustment

𝐶ℎ Control headroom

Symbols for Chapter 6

𝑅 Step-ratio between output voltage and input voltage

𝑣𝑖𝑛 Input dc source voltage

𝑉𝑑𝑐 Amplitude of 𝑣𝑖𝑛

𝑣𝑜𝑢𝑡 Output ac load voltage in dc-ac conversion

𝑣𝑜 Output dc load voltage in dc-dc conversion

𝑣𝑓 Inductive filter voltage

𝑣𝑎𝑐 Voltage across the ac load in dc-ac or voltage across ac filter in dc-dc

𝑉𝑎𝑐 Amplitude of 𝑣𝑎𝑐

𝑣𝑆𝑀𝑇,𝑆𝑀𝐵 Sum of SM capacitor voltages in top stack or bottom stack

𝑖𝑖𝑛 Input dc source current

𝐼𝑑𝑐 Amplitude of 𝑖𝑖𝑛, dc component of the stack current

𝑖𝑜𝑢𝑡 Output ac load current in dc-ac conversion

𝑖𝑜 Output dc load current in dc-dc conversion

𝑖𝑓 Inductive filter current

𝑖𝑎𝑐 Current through the ac load in dc-ac conversion

𝑖𝑎𝑐

2 AC component of the stack current

𝑖𝑐𝑖𝑟 Circulating current

𝑛𝑇,𝐵 SM number in top stack and bottom stack

𝜔 Angular frequency of the ac voltage and ac current

𝑓 Frequency of the ac voltage and ac current

𝑇 Cycle of the ac voltage and ac current

𝜃 Phase difference between the ac voltage and ac current

𝑚𝑑𝑐𝑇,𝑑𝑐𝐵 DC modulation index of top stack and bottom stack

𝑚 AC modulation index of top stack and bottom stack

𝛿𝑇,𝐵 Redundancy ratio for the dc components of stack voltage

Chapter 1 Introduction

1.1 Background

The crucial challenges on climate change and pollution problems with fossil energy are driving

the huge demand for both centralized and distributed renewable energy worldwide, and it is

the electrical power system that always serves as the backbone for renewable energy

generation, transmission and distribution.

The generation capacity and penetration of renewable energy are growing fast in last decade,

and they are expected to keep growing rapidly in the next decades, shown in Figure 1.1 (a) and

Figure 1.1 (b) [1]–[3]. Currently, the largest wind farm power station and photovoltaic (PV)

park power station in the world have already reached 8 GW capacity and 1.5 GW capacity

respectively [4], [5], and the total penetration of wind and PV generation in Europe has

approached 20% of the whole capacity [6]. In the near future, the development of offshore

wind farm generation in Europe is planned to reach 25 GW at 2020 and 70 GW at 2030 [7],

and the penetration of renewable energy has great ambition to overtake the traditional fossil

energy in many countries.

(a)

Utility-scale capacity additions, 2010-2017gigawatts

35

30 nonrenewablerenewable

25

20

15

10

5

02010 2011 2012 2013 2014 2015 2016 2017

29%36%

54%

40%51%

67%62%

49%

7

6

5

4

3

2

1

0Q1

2017 otherrenewables

solar

wind

photovoltaic

Q2 Q3 Q4

Utility-scale renewable capacity additionsgigawatts

2 Introduction

(b)

Figure 1.1. Change in power generation. (a) Renewable energy addition from 2010 to 2017. (b)

Renewable energy prediction in 2035.

The renewable energy generation has many different features and characterisers compared to

the traditional fossil energy generation. For example, the centralized large-scale renewable

energy generation is usually located in offshore areas or remote areas on land, so in both cases

they are far away from the metropolitan load centres [8]–[10]. The large number of distributed

small-scale renewable energy generations require different types of integration technologies

for connection to distribution networks [11], [12]. These new features and characterisers of

renewable energy generation and integration have raised many new challenges for modern

power systems and they are also gradually reshaping the structures of power systems from tops

to their tails.

1.2 Multiple Voltage Power System

Electrical power systems around the world have been evolved nearly 140 years into structures

with multiple voltage levels [13]. The transmission systems for large-scale electrical power

transfer are configured at high voltage level (extra high voltage level) [14] to decrease the

current value through the cables or overhead lines (OHL) for a reduced operational cost, while

the residential small distribution systems are configured at low voltage level [15] to decrease

the insulation and protection equipment cost and also reduced risk of harm for human beings.

1.2 Multiple Voltage Power System 3

City-level or district-level large distribution systems normally serve as an intermediate stage

between the high voltage (extra high voltage) transmission and low voltage distribution, and

some cites also have an intermediate stage between the generation voltage and transmission

voltage. These two intermediate stage systems are usually set at medium voltage level between

(high voltage level and low voltage level) to trade-off the capital cost and operational cost.

1.2.1 High Voltage Transmission System

For the top of power system structure, i.e. the high voltage or extra high voltage transmission

system, the 50/60 Hz ac scheme has long been the dominant form [16], [17] and the dominance

of ac can be traced back to the ability of a transformer [18] to increase the voltage at which

power is transmitted to achieve good efficiency of transmission without a large penalty in cost

or power loss within the transformer itself. The step-up high-voltage transformer increases the

voltage at the sending end and the step-down transformer decreases the voltage at the receiving

end. A simple illustration of high voltage alternating current (HVAC) infrastructure is shown

in Figure 1.2.

Figure 1.2. HVAC transmission infrastructure.

With the breakthrough of power semiconductor and power electronics technologies in recent

decades, high voltage dc (HVDC) transmission has become feasible [19], [20] and the stage is

set for dc and ac electrical power systems to compete again after the famous technical dispute

between Thomas Edison and Nikola Tesla [21], [22]. Compared to HVAC transmission system,

HVDC needs two extra power electronics stations, one at each end of a link, to fulfil the high

voltage ac-dc and dc-ac conversion, shown in Figure 1.3. An HVDC link can be further

classified according to the types of power semiconductors and converter topologies in the ac-

dc and dc-ac stations. The conventional current source converter (CSC) features a current in

the dc line that is constant (in the short term). It is mostly commonly implemented with line-

Step-up Transformer

50/60 Hz

Step-downTransformer

Generator Centre

Load Centre

Sending End Receiving EndHVAC Transmission

4 Introduction

commutated thyristor valves. The voltage source converter (VSC) features a dc voltage that is

constant (in the short term). It has come to prominence more recently and is normally based on

self-commutated insulated gate bipolar transistors (IGBT) valves.

Figure 1.3. HVDC transmission infrastructure.

Compared with HVDC transmission, HVAC is a relatively mature and robust choice for short

and medium distance transmission. However, when the transmission range increases to long

distances, HVAC has to face some severe challenges. In the case of underground and undersea

cables, the capacitance becomes rapidly significant when cable length is large. The consequent

capacitive charging current detracts from the capacity for carrying current for power

transmission and considerably limits the transmission capability. In the case of overhead line

(OHL), the series inductance of the line becomes dominant in long-distance ac transmission,

which results in both phase shift and voltage drops for HVAC transmission. HVDC

transmission would not have the difficulties with transmission distance experienced under ac

since there is no capacitive shunt current or inductive voltage drop in the dc cable or dc OHL.

In addition, HVDC transmission has advantages in system footprint over ac transmission

because in ac transmission the root-mean-square (RMS) value of voltage that sets the ac power

is a factor of √2 less than the peak value whereas a dc system can utilise the peak value

continuously. This is also especially useful in utilising the voltage insulation and way-leave to

its full potential. The argument around the current rating is less clear since the limit is often

thermal and so the RMS current is the limit not the peak value for both ac and dc systems.

HVAC and HVDC transmission systems are the two commercially available schemes to

connect the large-scale centralized renewable energy generation to load centre, and these ac

and dc technologies compete with each other on cost [23], [24], shown in Figure 1.4 (a) and

Figure 1.4 (b). It is well-known that HVAC has the advantage of relatively inexpensive

terminal cost whereas HVDC has expensive power converter stations. On the other hand, the

Step-up Transformer

Step-downTransformerSending End Receiving End

HVDC Transmisson

0 Hz Generator

CentreLoad

Centre

CSC or VSC CSC or VSC


route cost in HVAC rises much more sharply with distance than that in HVDC because of the

different transfer capability limits. Over short distances HVAC is favoured for its lower

terminal costs but beyond some threshold distance, the advantage of lower route costs favours

HVDC. The cross-over distance for the cost of HVAC and HVDC is reported to be in the region

of 80 km for subsea cable transmission systems [25]–[27] and in the region of 700 km for OHL

transmission systems [28], [29]. Further, the threshold cross-over point will move closer to the

original point as the transmission power increases.

Recognizing both the power rating and transmission distance of the large-scale centralized

renewable energy generation are increasing fast and they will keep growing in the future [7],

[10], [30], HVDC transmission is becoming the preferred choice for centralized large-scale

renewable energy integration. Several large power HVDC projects were commissioned in

recent decade, and many of them are under construction or under development now [31]–[34].

In the major trend of renewable energy generation, HVDC transmission is expected to take a

very important proportion in future high voltage transmission structures.

(a) (b)

Figure 1.4. Cost comparison between HVAC and HVDC. (a) Subsea cable transmission for offshore

renewable energy generation. (b) OHL transmission for remote land renewable energy generation.

1.2.2 Low Voltage Distribution System

For the tail of power system structure, i.e. the low voltage distribution system, the 50/60 Hz ac

structure is also the dominant scheme. The distribution system normally serves in an

HVDC

Transmission Distance (km)

Ove

rall

Cos

t

HVAC

80 12040 160 2000 240 Transmission Distance (km)

Ove

rall

Cos

t

500 750250 1000 15000 1250

HVDCHVAC

6 Introduction

unidirectional sense to service consumption across the network from a central bulk supply point

and is largely passive in nature. Thanks to the integration of a large amount of distributed

generation in the last decade, the low voltage distribution system is now developing into a

flexible bidirectional active network for future smart power systems [35], [36], and the low

voltage distribution system is trying to find a more efficient, more cost-effective and more

controllable structure to integrate the distributed renewable energy and residential loads [37]–

[40].

In the low voltage alternating current (LVAC) distribution infrastructure that prevails today,

shown in Figure 1.5, the system needs two conversion steps to integrate the distributed PV,

wind and storage energy into the system and also needs the two-stage conversion to satisfy the

digital, motor, lighting and electrical vehicle (EV) loads. The two-step conversion at both

generation side and load side complicates the distribution system structure and also increases

the capital cost and power losses.

Figure 1.5. LVAC distribution infrastructure.

If the system utilises a low voltage direct current (LVDC) structure, shown in Figure 1.6, it

only needs a single conversion step to connect the distributed renewable generations, energy

ModernBallast

Digital

PV Wind Storage

Motor Lighting EV

LVAC Distribution


storage and different types of loads. Compared with the ac infrastructure, the dc scheme is more

compatible with both the distributed renewable sources and residential loads. It has advantages

of simple structure, low capital cost and high efficiency because it avoids the extra dc-ac and

ac-dc conversion that exist in the ac scheme, and it also have the potential to increase power

quality and provide greater resilience against power surge and irregular loads [41]–[44].

Figure 1.6. LVDC distribution infrastructure.

Thanks to these benefits, LVDC distribution system received much interest from both academic

research and industrial development [45]–[49], and it has been extensively investigated and

prototyped in recent years [50]–[52]. With the rapid development of distributed renewable

energy and new demand for EV charging, LVDC system is expected to be a very important

constitute of future low voltage distribution structures.

1.2.3 Medium Voltage Collection and Distribution System

Between the top and tail of the power system structure, there are medium voltage collection

and distribution systems. One of the most common applications for medium voltage collection

system is to connect the offshore wind farms to HVAC or HVDC transmission system, and the

medium voltage distribution system is usually built in metropolitan load centre. The ac

structure is the almost the universal choice in the traditional power systems, but the fast

development of HVDC transmission and the promising prospect of LVDC distribution provide

PV Wind Storage

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Digital Motor Lighting EV

LVDC Distribution

8 Introduction

an impetus to consider dc schemes in medium voltage level [53]–[55]. The space that can be

provided for medium voltage system in offshore areas and city areas are both very limited, but

the power rating of offshore wind farms and load centre demand are expected to keep

increasing. It requires more compact and more efficiency medium voltage systems to address

this problem, and dc schemes could be a good choice [56]–[60].

The infrastructures of traditional medium voltage alternating current (MVAC) collection and

distribution with HVAC transmission and HVDC transmission are shown in Figure 1.7 (a) and

Figure 1.7 (b) respectively. The MVAC collection system needs a back-to-back conversion for

the generation converters and then uses a 50/60 Hz low frequency transformer to step up the

voltage to medium voltage level. Similarly, the MVAC distribution system uses a 50/60 Hz

low frequency transformer to step down the voltage and then requires a back-to-back or ac-dc

conversion at low voltage level for different type of loads.

The infrastructures of medium voltage direct current (MVDC) collection and distribution

system are shown in Figure 1.8 (a) and Figure 1.8 (b) respectively [61]–[63]. For HVAC

transmission scheme, the MVDC collection system and distribution system only need one

conversion step for generation converters and load converters, and they also remove the bulky

low frequency medium transformers that exist in the MVAC system. However, they require a

high ratio dc-dc converter to step up or step down the voltage and also need a dc-ac or ac-dc

converter to interface the ac transmission system. The efficiency of MVDC system for HVAC

transmission scheme would not have advantages but the system footprint could be reduced

because the medium voltage power electronics converters can be operated with medium or high

switching frequency for high power density and the dc system itself also has the footprint

advantage over ac system as analysed in Section 1.2.1. For HVDC transmission scheme, the

advantages of the MVDC collection system and distribution system become clearer. They

conversion step is decreased at both low voltage level and high voltage level compared to the

traditional MVAC system, which leads to less power losses and higher system efficiency.

Further, the MVDC system not only removes the low frequency MVAC transformers, but

opens up the possibility to replace the low frequency HVAC transformers with high voltage

high step-ratio dc-dc converters. In this manner, the MVDC footprint can be considerately

reduced compared to the MVAC system [64]–[67].


(a) (b)

Figure 1.7. MVAC collection and distribution infrastructure. (a) For HVAC transmission scheme. (b)

For HVDC transmission scheme.

(a) (b)

Figure 1.8. MVDC collection and distribution infrastructure. (a) For HVAC transmission scheme. (b)

For HVDC transmission scheme.

Because of the advantages in power density and power efficiency, and also thanks to the rapid

development of HVDC transmission and LVDC distribution, MVDC collection system and

distribution system have attracted great attention recently and some demonstration projects

have already been commissioned or announced [68]–[72]. The infrastructure of MVDC system

is naturally more compatible with HVDC and LVDC than MVAC counterparts, and the

essential benefits of compact footprint and high efficiency are very attractive for offshore wind

MV Step-up Transformer

LV AC-DC-AC Converter

Wind Turbine Generator

HV Step-up Transformer

HVAC Transmission

MV Step-down Transformer


HV Step-down Transformer

DC or AC LV Distribution

MVAC Collection and Distribution

HV AC-DC Converter

MV Step-up Transformer




HVDC Transmission

HV AC-DC Converter

MV Step-down Transformer




MVAC Collection and Distribution

MV Step-up DC-DC Converter

LV AC-DC Converter


MV Step-down DC-DC Converter


LV DC-AC Converter

MVDC Collection and Distribution


HVAC Transmission


HVDC Transmission

HV Step-up DC-DC Converter

MV Step-up DC-DC Converter

LV AC-DC Converter


HV Step-down DC-DC Converter

MV Step-down DC-DC Converter


LV DC-AC Converter

MVDC Collection and Distribution

10 Introduction

farms and metropolitan load centre applications. Considering these factors, MVDC systems are

expected to become a very important complement of the traditional MVAC scheme in future

medium voltage structures.

1.3 Multi-terminal and Multi-Voltage DC Networks

Combining and summarising the analysis and comparison in Section 1.2.1 to Section 1.2.3, it

can be observed that the large integration of both centralized and distributed renewable energy

has brought a profound impact on traditional power systems and is gradually reshaping their

traditional structures from top to tail. DC infrastructure is seen to have essential advantages

and potentials in various voltage levels of power system and is expected to play an important

role in future smart power systems.

Nowadays, most of the existing dc systems are of a point-to-point configuration and they

transmit large amounts of power in unidirectional way, from large-scale generation to a load

centre, or from a country with cheap energy to a country with expensive energy. To increase

the flexibility and reliability of dc systems, there is a strong motivation to interconnect the

point-to-point dc links to form multi-terminal dc networks as has happened for ac networks.

This allows for greater flexibility in power flow with less equipment compared to multiple

equivalent point-to-point systems and it also allows for greater reliability because redundancy

can be provided through additional cables or OHL.

The conventional CSC-HVDC transmission system has been explored first to form multi-

terminal dc networks [73]. However, the line-commutated converter (LCC) in CSC-HVDC

system requires a strong ac grid to guarantee the correct commutation of the thyristor valves,

which constrains the important applications for weak ac networks, such as offshore wind farms

and remote grids. For related reasons, CSC-HVDC system is not grid-forming and does not

have black start capability. Further, the dc current in the CSC-HVDC system cannot change

direction meaning that it is the dc bus polarity that has to be inverted if the power flow is to be

reversed in the dc link. This affects the choice of insulation materials that can be used, the

possible speed of reversals and may cause some issues for cable or OHL lifespan. It also means

that multi-terminal operation is very constrained, especially for renewable energy integration,

1.3 Multi-terminal and Multi-Voltage DC Networks 11

and only a handful of three-terminal versions exist in practice [73]–[75]. Additionally, the

phase of the generated ac current in CSC-HVDC system is always lagging with respect to the

ac voltage phase. This means the CSC-HVDC system needs a large amount of capacitive

reactive power to be available as compensation in the ac network to which the dc link connects.

VSC-HVDC technology, on the other hand, does not possess the same limitations as CSC-

HVDC since the full-controllable IGBT and self-commutated valves can exercise good control

over the current and accomplish complete four-quadrant (𝑃 + 𝑗𝑄) power conversion. It has the

capability of voltage support and black-start for weak ac grids and the good current control

results in low harmonic distortion that in turn requires only small harmonic filters. Bidirectional

power flow can be realised by changing the dc current direction leading to easier formation of

multi-terminal arrangements and opening up use of insulation materials that would not need to

withstand polarity reversal. Because of these technical considerations, VSC-HVDC has been

regarded as the preferred technology for multi-terminal dc networks. There are several such

projects already brought into operation or in the plan phase, including a 423 MW 160 kV three-

terminal multi-terminal VSC-HVDC project in Nan'ao, China (2013) [76], a 800 MW ±200 kV

five-terminal VSC-HVDC project in Zhoushan, China (2014) [77], a 7.5 GW MW ±500 kV

six-terminal VSC-HVDC project in Zhangbei, China (2021) [78] and the Atlantic Wind

Connection project on the east coast of the USA with up to 12 terminals [79].

In the multi-terminal projects commissioned to date, the interconnected dc links in each

individual project are configured with identical dc voltage because they are constructed at the

same time and they are located in the same area, illustrated in Figure 1.9. For future multi-

terminal dc networks, the system will probably need to interconnect the individually disparate

links which were built in different time periods and located in different areas. Taking the North

Sea as an example, there will be around 15 HVDC links [34],[80]–[83] and very few has same

voltage. Noting that the voltage rating of dc systems are not currently standardized and

technology innovation and the quest for high power transfer have led to many different voltages

being used, the dc link voltages in one multi-terminal dc networks can be different (but still

within the same voltage level) in the coming years, as shown in Figure 1.10, and it will require

several low step-ratio dc-dc converters as the interface in the system for voltage transformation

[84], [85].

12 Introduction

Figure 1.9. Multi-terminal dc network with identical voltage.

Figure 1.10. Multi-terminal dc network with similar but not identical voltages (still within the same

voltage level).

On the basis of Figure 1.10, there is also much interest and great ambition to make one step

further to interconnect dc links of both same voltage level and different voltage levels [86]–

[89], and this is also the last key step to form a whole multiple voltage dc power system, which

can make full use of the benefits of dc scheme from top to tail and further increase the flexibility

and ease the integration for both centralized and distributed renewable energy.

A simple illustration of multi-voltage dc network including HVDC and MVDC infrastructures

[65], [90]–[92] is shown in Figure 1.11. The MVDC collection and distribution systems are

interconnected into the HVDC multi-terminal system by several high step-ratio dc-dc

converters. From the analysis and discussion in Section 1.2.1 and Section 1.2.3, this dc network

AC-DC

AC-DC

DC-AC

DC-AC

HVAC Grid

HVAC Grid

HVAC Grid

HVAC GridMulti-terminal DC Network with Identical Voltage

Low Step-Ratio DC-DC


AC-DC

AC-DC

DC-AC

DC-AC

HVAC Grid

HVAC Grid

HVAC Grid

HVAC Grid

Multi-terminal DC Network with Similar but not Identical Voltages (within the Same Voltage Level)

1.3 Multi-terminal and Multi-Voltage DC Networks 13

might not only possess the low-cost advantages for long distance transmission but also show

good conversion efficiency and reduced system footprint for both offshore wind farms

collection system and metropolitan load centre distribution system. The block of MVDC

distribution in Figure 1.11 can be further decomposed and an illustrative example of multi-

voltage dc network with MVDC and LVDC infrastructures [71], [72], [93]–[95] is shown in

Figure 1.12. This dc network provides two different approaches to interconnect MVDC and

LVDC systems. For relatively large LVDC generation and distribution systems, the LVDC

parts are interconnected to the medium voltage link by one high step-up dc-dc converter (for

the generation network) and one high step-down dc-dc converter (for the load network). For

relatively small LVDC generation and distribution systems, the generator and load are

interconnected at low voltage to form a dc microgrid first and then connected to a medium

voltage link by a high step-ratio dc-dc converter. The medium voltage links for these two

approaches can be different, and they are connected by a low step-ratio dc-dc converter. Based

on the analysis and comparison in Section 1.2.2 and Section 1.2.3, this MVDC and LVDC

distribution network is more compatible with the distributed renewable energy and residential

loads than traditional ac distribution network, which may reduce the capital cost and increase

the overall efficiency.

Figure 1.11. Multi-voltage dc network with HVDC and MVDC infrastructures.



AC-DC

AC-DC

DC-AC

DC-AC

HVAC Grid

HVAC Grid

HVAC Grid

HVAC Grid

MVDC Collection

Multi-voltage DC Network with HVDC and MVDC infrastructures

MVDC Distribution

High Step-Ratio DC-DC

High Step-Ratio DC-DC

14 Introduction

Figure 1.12. Multi-voltage dc network with MVDC and LVDC infrastructures.

1.4 Motivations and Challenges for DC-DC Converters

Multi-voltage dc networks interconnect dc network sub-systems of different voltages and it is

an important step toward forming multiple voltage dc power systems. Dc-dc converters are one

of the most essential equipment in these dc networks. They play an equivalent role to the

transformer in ac systems, that is, they interconnect different voltages but they offer greater

functionality for the system. Besides providing interconnection for dc links or dc systems of

different voltages, dc-dc converters can also interconnect dc links of different configurations

(monopolar, symmetrical monopole and bipolar configuration), different groundings, different

manufactures and different converter topologies (CSC and VSC). Further, dc-dc converters can

also provide some attractive benefits for dc network protection, such as fault current limitation,

fault current interruption and firewall-like separation. In addition, dc-dc converters could also

enhance operation and control of dc networks, including power flow control (important where

the number of dc links exceeds the number of terminals) and voltage drop compensation (for

very long distance transmission).

Nonetheless, there also exists many technical challenges and difficulties for dc-dc converters

PV Wind Battery

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Digital Motor Lighting

High Step-upDC-DC


PV Battery

HVAC Transmission

HVDC Transmission

Large LVDC Distributed Generation Small LVDC Distributed Microgrid

High Step-DownDC-DC

High Step-RatioDC-DC

Large LVDC Load Distribution

Multi-voltage DC Network with MVDC and LVDC Infrastructures

ModernBallast

Digital Lighting

EV

1.4 Motivations and Challenges for DC-DC Converters 15

in multi-voltage dc network interconnection. The discussion in Section 1.3 and the illustrations

of infrastructure in Figure 1.11 and Figure 1.12 have shown that multi-voltage dc networks

require high step-ratio dc-dc conversion to interface dc systems with different voltage levels and

require low step-ratio dc-dc conversion to interconnect dc links with similar but not identical

voltages. High step-ratio dc-dc converters would choose a shunt connection [96], [97] with the

higher voltage sub-system to interface the lower voltage sub-system. Considering the voltage

ratings and power ratings of different sub-systems in a multiple voltage power system structure,

the voltage step-ratio requirement between a high voltage line to a low voltage line would be

around 10:1 and the power throughput of the high step-ratio dc-dc converter would be around

1:10 of the link power of the higher voltage system [92], [98]–[100]. Low step-ratio dc-dc

converters should be directly integrated into the higher voltage sub-systems. Since the

interconnected dc links are in the same voltage level with similar power rating, the step-ratio

requirement for the low step-ratio dc-dc converters should be close to 1:1 and the power

throughput of the low step-ratio dc-dc converters needs to be about 1:1 of the whole link power

[101]–[103].

The combination of voltage rating, power rating and step-ratio requirements for these dc-dc

converters in multi-voltage dc network interconnection is a new application for power

electronics and a fresh area of research. It requires new circuit topologies and operating

principles to accomplish these conversions in a low-cost, high-compactness, high-efficiency

and high-reliability fashion.

The cost, density, efficiency and reliability are the most important four challenges and

considerations in the design and operation of dc-dc converters for the multi-voltage dc network

interconnection. Firstly, the total number and power rating of the semiconductor devices in

these converters should be carefully managed to reduce the capital cost because these high

voltage and medium voltage applications would usually need a large number of semiconductor

devices and their cost accounts for a major part of the overall cost. Also, the energy storage

rating of passive components in these dc-dc converters need to be constrained to increase the

power density and reduce the platform footprint cost, especially in offshore cases and in

densely developed city centre cases. Further, the conduction losses and switching losses of

these converters have to be limited to increase the overall power efficiency and reduce the

16 Introduction

operational cost over a long lifetime service. Moreover, these dc-dc converters must have fault-

tolerant operation to address the faults from the converters themselves and keep their reliability

at high value to decrease the cost of planned and unplanned outages. These converters should

also have protection schemes (with or without additional equipment) to deal with the faults

from the dc network and reduce the damage cost for semiconductor devices and passive

components.

1.5 Research Questions

This key work of thesis investigates the potential high step-ratio and low step-ratio dc-dc

converters for multi-voltage dc network interconnection, and it sets out to address the following

research questions.

1. What are the best structures for high voltage dc-dc conversion, recognising that multiple

individual semiconductor switches will need to be used?

2. How can the modular multilevel technologies that have been proved very successful in

high voltage ac-dc conversion be adapted and applied to medium voltage and high

voltage dc-dc conversion?

3. How can the key metrics of cost, density, efficiency and reliability be improved for

modular multilevel dc converters?

4. Are different approaches needed to address the high step-ratio conversion and low step-

ratio conversion?

5. What are the application areas that suit resonant and non-resonant modular multilevel

dc converters?

These questions will be addressed through a three-step process that is applied to a variety of

circuit topologies that are known from the literature or were created when looking for new

applications. The three steps are (i) to analyse the circuits to define operating principles and

size principal components, (ii) to simulate the circuits at the power ratings envisaged for

commercial use and (iii) to confirm the analysis and simulation by comparison to operation of

experimental prototypes at reduced ratings.

1.6 Thesis Outline 17

1.6 Thesis Outline

A general introduction to the multi-voltage dc networks and the motivations and challenges for

dc-dc converters in medium voltage level and high voltage level power networks have been

given earlier in Chapter 1. Before addressing the research questions set out in Section 1.5,

Chapter 2 presents a review of the literature and discusses the technology current status of dc-

dc converters for applications at various voltage levels.

This thesis explores both (i) the high step-ratio dc-dc conversion to interface dc systems with

different voltage levels and (ii) the low step-ratio dc-dc conversion to interface dc systems with

similar but not identical voltages (still in the same voltage level). Chapter 3 and Chapter 4 focus

on resonant approaches for MVDC networks, and Chapter 5 and Chapter 6 concentrate on non-

resonant solutions for HVDC networks.

Chapter 3 describes proposals for a family of resonant modular multilevel dc converters

(RMMCs) which accomplishes bidirectional high step-ratio connection between MVDC and

LVDC distribution networks. Circuit analysis is undertaken to establish the design equations

to be used for sizing components. A modulation scheme is devised that enables flexibility in

the choice of voltage step-ratio value and exploits inherent voltage-balancing of the sub-

module (SM) capacitors.

Chapter 4 presents a step-by-step circuit evolution which drives the basic high step-ratio

RMMC to a basic low step-ratio RMMC and further creates a new family of low step-ratio

RMMCs which achieves bidirectional interface between two MVDC distribution links with

similar but not identical voltages. Examination of the circuit operation will show that this low

step-ratio RMMC family inherits all the operational benefits from the high step-ratio RMMC

family in Chapter 3, and this low step-ratio family also demonstrates an additional advantage

of extremely low rating requirement for both semiconductor devices and SM capacitors.

Considering the technical difficulties and limitations of RMMC families for high voltage level

interconnection, two non-resonant modular multilevel dc converters are presented in Chapter

5 and Chapter 6 for high step-ratio and low step-ratio conversion in HVDC networks.

18 Introduction

A modular multilevel dc-ac-dc converter based on single-active-bridge or dual-active-bridge

structure is explored in Chapter 5. It is examined for the purpose of unidirectional or

bidirectional connection between an HVDC terminal and an MVDC network where the high

step-ratio low power throughput conversion applies. Operation with near-square-wave current

is proposed for this single-phase converter in order to decrease the volt-ampere rating

requirement for semiconductor devices and reduce the energy storage requirement for SM

capacitors.

Noting that multi-stage conversion, in the case of Chapter 5 using an intermediate ac stage,

invariably increases the overall cost, system footprint and power losses, Chapter 6 presents a

single-stage direct-chain-link modular multilevel buck-boost converter which is suitable for

low step-ratio high power throughput conversion between two dc terminals with similar but

not identical voltages. The circuit employs an ac circulating current to balance the stack

energies and the design approach described includes the identification of the circulating

frequency choice for the minimum current stresses and reactive power losses in the conversion.

In Chapter 7, the various threads of the study are drawn together and the main advantages and

limitations of the various dc-dc converters presented in Chapter 3 to Chapter 6 are summarised.

From this, conclusions are drawn, the contributions of the thesis identified and some items for

future work discussed.

The down-scaled experimental prototypes for the dc-dc converters in Chapter 3 to Chapter 6

are demonstrated in Appendix. These include resonant modular multilevel dc converters with

DXP controller system for high step-ratio and low step-ratio conversion and non-resonant

modular multilevel dc converters with OPAL-RT controller system for high step-ratio and low

step-ratio conversion.

1.7 Author’s Publications Based on This Work 19

1.7 Author’s Publications Based on This Work

1.7.1 Journal Papers

[1] X. Zhang, M. Tian, X. Xiang, J. Pereda, T. C. Green and X. Yang, “Large Step Ratio Input-

Series-Output-Parallel Chain-Link DC-DC Converter,” IEEE Trans. on Power Electron.

(Online Published, Early Access).

[2] Y. Gu, Y. Li, H. Yoo, T. Nguyen, X. Xiang, H. Kim, A. Junyent-Ferre, T. C. Green,

“Transfverter: Imbuing Transformer-like Properties in an Interlink Converter for Robust

Control of a Hybrid AC-DC Microgrid,” IEEE Trans. on Power Electron. (Online Published,

Early Access).

[3] X. Xiang, X. Zhang, G. P. Chaffey and T. C. Green, “A Modular Multilevel DC-DC

Converter with a Compact Sub-Module Stack Suited to Low Step-Ratios,” in IEEE Trans. on

Power Del. vol. 34, no. 1, pp. 312-323, Feb. 2019.

[4] X. Zhang, X. Xiang, T. C. Green and X. Yang, “A Push-Pull Modular Multilevel Converter

Based Low Step-Up Ratio DC Transformer,” in IEEE Trans. on Ind. Electron., vol. 66, no. 3,

pp. 2247-2256, Feb. 2019.

[5] X. Xiang, X. Zhang, T. Luth, M. M. C. Merlin and T. Green, “A Compact Modular

Multilevel DC-DC Converter for High Step-ratio MV and HV Use,” in IEEE Trans. on Ind.

Electron., vol. 65, no. 9, pp. 7060-7071, Sept. 2018.

[6] X. Xiang, X. Zhang, G. P. Chaffey and T. C. Green, “An Isolated Resonant Mode Modular

Converter with Flexible Modulation and Variety of Configurations for MVDC Application,”

in IEEE Trans. on Power Del., vol. 33, no. 1, pp. 508-519, Feb. 2018.

[7] X. Zhang, X. Xiang, T. C. Green and X. Yang, “Operation and Performance of Resonant

Modular Multilevel Converter with Flexible Step Ratio,” in IEEE Trans. on Ind. Electron., vol.

64, no. 8, pp. 6276-6286, Aug. 2017.

20 Introduction

[8] X. Xiang, X. Zhang, Y. Gu, G. P. Chaffey and T. C. Green, “Analysis and Choice of

Circulating Current Frequency in Chain-link Modular Multilevel DC-DC Converters,” IEEE

Trans. on Power Electron. (In Peer Review).

[9] X. Xiang, Y. Gu and T. C. Green, “Comparison of HVAC, LFAC and HVDC for Large-

scale Offshore Wind Farm Connection,” IEEE Trans. on Sustain. Energy. (In Peer Review).

[10] Y, Qiao, X. Zhang, X. Xiang, X. Yang and T. C. Green, “Active Trapezoidal Current

Modulation for Bidirectional High Step Ratio Modular DC-DC Converters,” IEEE Trans. on

Power Electron. (In Peer Review).

1.7.2 Conference Papers

[11] X. Xiang, X. Zhang, G. P. Chaffey, Y. Gu and T. C. Green, “Analysis and Investigation

on the Fundamental Frequency of Chain-link Modular Multilevel DC-DC Converter for Low

Step-Ratio High-Power MVDC Applications,” 10th Energy Conversion Congress and

Exposition, Portland, OR, pp.2963-2969, 2018.

[12] Y. Sang, A. Junyent-Ferre, X. Xiang and T. C. Green, “Analysis and Control of a Parallel

DC Collection System for Wind Turbines with Single Active Bridge Converters,” 10th Energy

Conversion Congress and Exposition, Portland, OR, pp.1005-1012, 2018.

[13] X. Xiang, X. Zhang, G. P. Chaffey, Y. Gu and T. C. Green, “The isolated resonant modular

multilevel converters with large step-ratio for MVDC applications,” 18th Workshop on Control

and Modeling for Power Electronics, Stanford, CA, pp. 1-6, 2017.

[14] X. Xiang, M. M. C. Merlin and T. C. Green, “Cost analysis and comparison of HVAC,

LFAC and HVDC for offshore wind power connection,” 12th AC and DC Power Transmission

Conference, Beijing, pp. 1-6, 2016.

[15] X. Xiang, M. M. C. Merlin and T. C. Green, “A New Modulation Method for Resonant

Modular Multilevel DC/DC Converter with Flexible Ratio Operation and Inherent Balance

Capability in HVDC Application,” in 2nd International CIGRE HVDC, Shanghai, pp. 1-6,

2016.

1.7 Author’s Publications Based on This Work 21

1.7.3 Role of Main Co-Authors

Dr. Xiaotian Zhang was a post-doctoral researcher in Prof. Timothy C. Green’s group from

2012 to 2015 and became an Associate Professor at Xi’an Jiaotong University, China in 2015.

He proposed the non-isolated high step-ratio RMMCs with fixed modulation scheme in 2013

and 2014 [91], [99]. I developed this idea and proposed the isolated high step-ratio RMMCs

with flexible modulation schemes in 2016, presented in Chapter 3, and I further evolved the

high step-ratio RMMCs to low step-ratio RMMCs in 2017, presented in Chapter 4. Dr. Xiaotian

Zhang offered advice on analysis of resonant circuits and his experimental test system was

adapted for the investigations of RMMCs reported in this thesis. He is named as a co-author

on many of the papers.

Dr. Thomas Luth was a Ph.D. student in Prof. Timothy C. Green’s group from 2010 to 2014

and worked on non-resonant modular multilevel dc-dc converters. The work of the high step-

ratio modular multilevel dc-ac-dc converter in Chapter 5 builds on his preliminary work [97]

and he is named as a co-author in the paper arising from this chapter.

Dr. Michael Merlin was a post-doctoral researcher in Prof. Timothy C. Green’s group from

2013 to 2017 and worked on control and topology of modular multilevel converter for HVDC

applications. He provided advice on the control of the high step-ratio modular multilevel dc-

ac-dc converter in Chapter 5, and he is named as a co-author in the paper arising from this

chapter.

Dr. Yunjie Gu was a post-doctoral researcher in Prof. Timothy C. Green’s group from 2016 to

2018 and became a Research Fellow in 2018. He worked on advanced control and networking

of power conversion systems. He provided mathematical analysis and derivation advice on the

low step-ratio modular multilevel dc-dc converter in Chapter 6, and he is named as a co-author

in the paper arising from this chapter.

Dr. Geraint Chaffey was a Ph.D. student in Prof. Timothy C. Green’s group from 2012 to 2016

and worked on analysis of fault current and protection in HVDC networks. He provided

assistance on the use of the OPAL-RT controller system and helped draft several papers.

Chapter 2 Literature Review and Technology

Current Status

As identified in Chapter 1, there will be important roles for both high step-ratio and low step-

ratio dc-dc converters in future multi-voltage dc networks. As a step towards satisfying these

emerging demands and overcoming the difficulties presented in Section 1.4, this Chapter

examines the published literature concerning dc-dc converter technologies for applications at

various voltage levels and provides a detailed analysis and comparison of the advantages and

disadvantages of the common dc-dc converter types. This chapter also sets out to describe and

clarify the recent focus of research and trends in development of medium voltage and high

voltage dc-dc conversion with the intention of identifying the inspiration and pathways to find

promising new dc-dc solutions that address the challenges in the interconnection of multi-

voltage dc networks.

2.1 DC-DC Converters in the Low Voltage Level

At the low voltage level, dc-dc conversion has been extensively investigated for several

decades to achieve conversion at various step-ratios with high power efficiency and high power

density [104]–[107]. The topologies can be generally classified into non-isolated circuits and

isolated circuits.

2.1.1 Non-isolated Circuits

The classic buck converter, boost converter and buck-boost converters [108], shown in Figure

2.1–Figure 2.3, are often considered as the starting points for creation of further advanced non-

isolated topologies in this voltage level [104]–[107], and most of these advanced dc-dc

24 Literature Review and Technology Current Status

topologies, to some extent, can be seen as derivations, variations or combinations from these

classic circuits.

(a) (b)

Figure 2.1. Classic buck converter. (a) Unidirectional version. (b) Bidirectional version.

(a) (b)

Figure 2.2. Classic boost converter. (a) Unidirectional version. (b) Bidirectional version.

(a) (b)

Figure 2.3. Classic buck-boost converter. (a) Unidirectional version. (b) Bidirectional version.

The semiconductor power switches in Figure 2.1–Figure 2.3 utilise IGBTs for illustration, but

they can be replaced by metal-oxide-semiconductor field-effect transistor (MOSEFT) directly

for high frequency (hundreds of kilohertz) conversion. The variety of auxiliary soft-switching

vLS

Lm vHS CHS

CLS

S

D vLS

Lm vHS CHS

CLS

S1

S2

vLS

Lm vHSCHS

CLS S

D

vLS

Lm vHSCHS

CLS

S1

S2

Lm

vHS CHS

vLSCLS +

S

D

Lm

vHS CHS

vLSCLS +

S1

S2

2.1 DC-DC Converters in the Low Voltage Level 25

circuits [109]–[111], active/passive clamp arrangements [112]–[114] and coupled-

inductor/built-in-transformer structures [115]–[118] can be all used in these typical dc-dc

converters to realise the high frequency soft-switching operation, decrease the voltage/current

stress on semiconductor switch/diode and develop the voltage step-ratio range.

2.1.2 Isolated Circuits

Turning to the isolated low voltage level dc-dc converters, the classic forward converter and

flyback converter [108] can be seen as isolated version of buck converter and buck-boost

converter respectively for unidirectional conversion and their circuit analysis is similar to the

unidirectional buck and buck-boost circuit. Apart from the forward and flyback converters, the

widespread single-active-bridge (SAB) / dual-active-bridge (DAB) converter [119]–[121] and

LLC resonant converter [122]–[124] are also popular solutions in low-voltage isolated dc-dc

conversion. Figure 2.4 and Figure 2.5 demonstrate the single-phase full-bridge configuration

of SAB/DAB and LLC converters and there are many different variations and derivations,

including the three-phase version [125], [126], half-bridge vision [127], [128] and multilevel

version [129]–[131]. There are also many choices for the modulation methods [132]–[134] to

increase efficiency and widen operation range, but the basic operating principles are almost the

same. The internal transformer provides galvanic isolation and facilitates the high step-ratio

conversion. All the switches can achieve soft-switching for high efficiency conversion, and the

switching frequency is usually operated at tens or hundreds of kilohertz, so the power density

is another important advantage of SAB/DAB and LLC converters.

(a)

Ll

Lm N2N1 CLS vLS

SH1 SH3

SH2 SH4

vHS

DL1 DL3

DL2 DL4

CHS


(b)

Figure 2.4. Full bridge configuration of single-active-bridge and dual-active-bridge converter. (a)

Unidirectional single-active-bridge converter. (b) Bidirectional dual-active-bridge converter.

(a)

(b)

Figure 2.5. Full bridge configuration of LLC resonant converter. (a) Unidirectional version. (b)

Bidirectional version.

These typical dc-dc converters (including both non-isolated and isolated) have the common

advantages of low-cost circuit design, high power density and high power efficiency in low

voltage dc conversion but this does not scale to medium voltage or high voltage ranges.

Switches in these topologies have to process the dc terminal voltage and/or dc terminal current

Ll

Lm N2N1 CLS vLS

SH1 SH3

SH2 SH4

vHS

SL1 SL3

SL2 SL4

CHS

Lm N2N1 CLS vLS

SH1 SH3

SH2 SH4

vHS

DL1 DL3

DL2 DL4

CHS

LrCr

Lm N2N1 CLS vLS

SH1 SH3

SH2 SH4

vHS

SL1 SL3

SL2 SL4

CHS

LrCr

2.2 DC-DC Converters in the Medium Voltage Level 27

with high switching frequency and therefore are not readily extended to the medium voltage

and high voltage applications, but they provide the promising basic structures for further

modifications and configurations.

2.2 DC-DC Converters in the Medium Voltage Level

For medium voltage dc-dc conversion (at least one dc terminal voltage in the medium voltage

range), the main solutions published concentrate on the advanced configurations of the classic

dc-dc circuits and develop their voltage rating for medium voltage level applications.

2.2.1 Cascaded Configuration

The simple cascaded configuration of the classic dc-dc circuits [135]–[137], shown in Figure

2.6, could develop the step-ratio limitation and avoid extreme duty-cycle of power switches in

the high step-ratio connection between LVDC and MVDC, but it is very hard for this type of

configurations to solve the problem of high voltage stress on the high-voltage side switch/diode

and the problem of high current stress on the low-voltage side switch/diode.

Figure 2.6. Cascaded configuration

2.2.2 Switching Capacitor Configuration

The switching capacitor configuration [138]–[140] is another approach for high step-ratio

conversion between LVDC and MVDC, show in Figure 2.7. It boosts the LVDC voltage by

fast switching of the connections of the capacitors and a large step-ratio conversion can be

achieved. It has partial self-balanced capability and it supports modular design without

changing the main circuit. However, it also has to face the issue of large current through the

low-voltage side switch and face the disadvantages that all the switches and diodes are operated

vLS

Lm1

vHSCHS1CLS

D1

S1

Lm2

CHS2S2 CHSN

D2


in hard switching mode. These factors result in large power losses and low conversion

efficiency.

Figure 2.7. Switching capacitor configuration

2.2.3 Multilevel Configuration

The traditional multilevel technologies of the neutral-point-clamped structure [141], [142] and

the flying-capacitor structure [143], [144] have been applied to the non-isolated classic dc-dc

circuits in order to partition the terminal voltage equally across many power devices and

thereby achieve an overall voltage rating applicable to the medium voltage level. Two basic

three-level boost converters are shown in Figure 2.8 as examples of this approach. The main

circuit maintains almost the same configuration as the classic boost converter in Figure 2.2 (a),

and it can be extended to an n-level configuration and thereby accomplish a high step-ratio

power conversion between LVDC and MVDC. The duty-cycle of each switch can be operated

in a normal range to avoid the extreme duty-cycle difficulty often seen in high step-ratio

conversion, and the passive inductor is also smaller than the original boost converter thanks to

vLS

Lm

vHS

CHS1

CLS S

D1

D2

DN1

DN2

CHSN

CO

DO

CS1

CSN


the benefit of multilevel operation and its high effective switching frequency. However, the

balancing of the voltages of the dc capacitors is a major challenge when the number of voltage

levels is high. Also, all the power devices are operated in hard-switching conditions, which

leads to relatively large switching losses in high frequency operation. Further, these multilevel

configurations do not provide fault-tolerance operation, and so it is hard for them to achieve a

high system reliability.

(a) (b)

Figure 2.8. Multilevel boost converter. (a) Neutral-point-clamped structure. (b) Flying-capacitor

structure.

2.2.4 Modular Configuration

The multiple module concept is a good solution to extend the application of isolated classic dc-

dc converters for medium voltage level conversion [65], [121], [145], [146]. The input-series-

output-parallel configurations of modular full-bridge DAB and LLC converters are presented

in Figure 2.9 as two illustrative examples of this topology family. The high-voltage side circuits

are connected in series to support the medium voltage dc terminal stress, and the low-voltage

side circuit are connected in parallel to share the current stress. These modular converters

inherit all the operational advantages from the original single circuit, including the soft-

switching operation for high efficiency conversion, high switching frequency for highly-

compact design and galvanic isolation for high step-ratio voltage transformation, and the

vLS

Lm CH1

S1

D1

S2

vHS

CH2

CLS

D2

vLS

Lm CH

S2

S1

CF1

CLS

vHS

D1

D2


modular design itself is also a very important factor in medium voltage and high voltage

applications for high system reliability. The modular DAB configuration has been also widely

applied for ac-ac conversion, and it has been considered as the key circuit for solid state

transformers (SST) in ac system [147]–[150].

(a)

(b)

Figure 2.9. Multiple module configuration of full-bridge bidirectional DAB and LLC. (a) Input-series-

output-parallel modular DAB. (b) Input-series-output-parallel modular LLC resonant converter.

vLSvHSDAB Module 1

DAB Module 2

DAB Module Nm

Ll

Lm N2N1 CLS

SH1 SH3

SH2 SH4

SL1 SL3

SL2 SL4

CHS

vLSvHSLLC Module 1

LLC Module 2

LLC Module Nm

Lm N2N1 CLS

SH1 SH3

SH2 SH4

SL1 SL3

SL2 SL4

CHS

LrCr


However, these modular converters and their derivative topology families all need

sophisticated algorithms to balance the voltage and current in each module circuit, which raised

challenges in the practical operation although solutions have been presented [151], [152].

Moreover, the requirements placed on the insulation of the transformer windings and other

components because of the large differences between the potentials of the primary side and

secondary side would lead to some serious design challenges especially when the dc terminal

voltage reaches high and the module number becomes large. Additional, the breakdown of any

single module transformer could cause the whole system failure, so the system reliability would

be undermined.

2.2.5 Resonant Configuration

Beyond the well-known configurations and topologies discussed in the preceding sections, the

resonant dc transformer offers an alternative direction for medium voltage dc-dc conversion.

The basic resonant topology is proposed in [153], [154], and unidirectional and bidirectional

circuits are shown in Figure 2.10 (a) and Figure 2.10 (b) respectively. Series connected

thyristors are utilised in these circuits to withstand the dc terminal voltage and their conduction

losses can be reduced compared to the IGBT switches. The anti-parallel configuration of

thyristors in Figure 2.10 (b) facilitates bidirectional conversion following the principle

established in conventional thyristors-based line-commutated converters. The bidirectional

configuration can realise reversal of the power flow without changing dc terminal voltage

polarity, making it more suitable for multi-terminal dc network interconnection [155]. The

resonant operation facilitates achieving soft-switching of all switches, so the switching losses

are very low [90], [156]. However, the resonant capacitors in these circuits have to face a high

voltage stress which is even higher than the high-side terminal voltage, and this issue will cause

design difficulty and insulation challenge. Further, the anti-parallel configuration at both the

low-voltage and high-voltage sides leads to a high cost for the large number of semiconductor

devices. Moreover, these resonant converters would also need auxiliary passive circuits to

ensure adequate static and dynamic sharing of voltage stress in the series-connected thyristors.


(a)

(b)

Figure 2.10. Resonant dc transformer. (a) Unidirectional version. (b) Bidirectional version.

2.3 DC-DC Converters in the High Voltage Level

Most of the drawbacks and difficulties in Figure 2.6–Figure 2.10 could be overcome by

applying the ideas of the modular multilevel converter (MMC) [157] to the dc-dc case. The

MMC concept combines constructional and reliability advantages of modular design with the

CHS vHSvLS CLS Cr

Lr1 Lr2

TL11 TL31

TL21 TL41

TL1N TL3N

TL2N TL4N

DH11 DH31

DH21 DH41

DH1N DH3N

DH2N DH4N

CHS vHSvLS CLS Cr

Lr1 Lr2

TL11 TL31

TL21 TL41

TL1N TL3N

TL2N TL4N

TH11 TH31

TH21 TH41

TH1N TH3N

TH2N TH4N

2.3 DC-DC Converters in the High Voltage Level 33

high effective switching of multilevel operation, in turn leading to both good efficiency and

little requirement for passive filtering. It also scales very well to medium voltage and high

voltage level conversion.

The original MMC based half-bridge SM was proposed for high voltage and high power ac-dc

or dc-ac conversion [157], shown in Figure 2.11. It has been very successful in HVDC

transmission over the last decade [31]–[33], [158], [159] and is set to have a profound impact

on future multi-terminal and multi-voltage dc networks [76]–[78], [80]–[83].

Figure 2.11. Half-bridge SM based modular multilevel converter

Compared to the thyristor-based line-commutated / current source converter (LCC/CSC),

shown in Figure 2.12, [28], [29], this IGBT-based self-commutated converter is a voltage

sourced converter (VSC). In contrast to the LCC, it can be operated across all four quadrants

of the real-reactive power plane and is capable of operating in weak ac grids and indeed of

black-starting ac grid. It achieves bidirectional power flow without changing the polarity of the

dc terminal voltage.

vDC

SMB

SMT

vAC

LBT

LBB

SMBT1

SMBTN

SMB B1

SMB BN

LCT

LCB

SMCT1

SMCTN

SMCB1

SMCB N

LAT

LAB

SMAT1

SMATN

SMA B1

SMA BN


Figure 2.12. Thyristors-based line-commutated converter

Figure 2.13. IGBT-based self-commutated two-level converter

Compared to the traditional two-level converter [28], [160], shown in Figure 2.13, which is

also an IGBT-based self-commutated voltage source converter, the MMC topology in Figure

2.11 has advantages in many aspects. First, the modular configuration is convenient to be

extended for high voltage and high power conversion, and the system reliability could stay at

very high value with redundancy design [161], [162]. Redundant SMs can be inserted into the

stack and faulty SMs could be bypassed without interrupting normal operation. Second, the

vDCLDC1

LDC2

vAC

LA,B,C

TAT1

TATN

TAB1

TABN

TBT1

TBTN

TBB1

TBBN

TCT1

TCTN

TCB1

TCBN

vDC

vAC

CDC1

LA,B,C

CDC2

SAT1

SATN

SAB1

SABN

SBT1

SBTN

SBB1

SBBN

SCT1

SCTN

SCB1

SCB N


multilevel operation does not need to use series-connected press-pack IGBTs [163] as required

in a two-level converter (to ensure integrity of the current path after a device failure).

Meanwhile, the multilevel operation also leads to low harmonic contents and so the filter value

in MMC is much smaller than two-level converter. Third, the nearest level modulation (NLM)

[157], [164], [165] with low switching frequency can be utilised for MMC which leads to much

lower switching losses than pulse width modulation (PWM) between two levels in which every

switch must switch at every instance and this further decreases the design difficulty of thermal

management in high power rating conversion.

Many variations of the basic MMC have been proposed to improve the dc fault handing

capability [166]–[170] and reduce the system footprint [171]–[174]. Some examples are shown

in Figure 2.14, including the full-bridge SM based MMC, the half-bridge SM and full-bridge

SM based hybrid MMC, the double-clamp SM based MMC, the hybrid cascaded multilevel

converter and the alternate arm converter (AAC). Also, considerations have been given to the

SM semiconductor design to decrease the conduction losses in the SMs and expand their

voltage/current limitation [175], which can increase the overall power efficiency and system

power rating closer to that of a thyristor-based LCC.

(a)

vDC

SMB

SMT

vAC

LBT

LBB

SMBT1

SMBTN

SMB B1

SMB BN

LCT

LCB

SMCT1

SMCTN

SMCB1

SMCB N

LAT

LAB

SMAT1

SMATN

SMA B1

SMA BN


(b)

(c)

(d)

vDC

SMF

SMF

vAC

LBT

LBB

SMBTH

SMBTF

SMB BH

SMB BF

LCT

LCB

SMCTH

SMCTF

SMCB H

SMCB F

LAT

LAB

SMATH

SMATF

SMA BH

SMA BF SMH

SMH

NH NF

vDC

SMB

SMT

vAC

LBT

LBB

SMBT1

SMBTN

SMB B1

SMB BN

LCT

LCB

SMCT1

SMCTN

SMCB1

SMCB N

LAT

LAB

SMAT1

SMATN

SMA B1

SMA BN

vDC

CDC1

CDC2

SAT1

SATN

SA B1

SA BN

SBT1

SBTN

SB B1

SB BN

SCT1

SCTN

SCB1

SCB N

vAC

SMA1 SMA N

SMB1 SMB N

SMC1 SMCN LA,B,C

SM


(e)

Figure 2.14. Variations of the basic MMC. (a) Full-bridge SM based MMC [167], [170]. (b) Half-bridge

SM and full-bridge SM based hybrid MMC [169]. (c) Double-clamp SM based MMC [167]. (d) Hybrid

cascaded multilevel converter [171], [172]. (e) Alternate arm converter [171], [173], [174].

Despite the fact that the original MMC topology in Figure 2.11 and its variations in Figure 2.14

are all ac-dc conversion technology, the modular multilevel concept of these structures can be

generalized and applied for dc-dc conversion with the expectation that, the operational

advantages of modularity, flexibility, and controllability could be inherited. Furthermore, the

MMC technology is developing very fast, spurred on by numerous commercial VSC-HVDC

transmission projects, and the overall cost of this technology is being driven down [26], [27].

Based on these factors, recent research work on medium voltage and high voltage dc-dc

conversion is shifting to concentrate on the adoptions and reconfigurations of the latest ac-dc

MMC technology to form modular multilevel dc-dc converters [87], [176], [177] for both high

step-ratio and low step-ratio applications. This trend can be expected to continue, and perhaps

dominate, in next decade due to the huge impact and cost-saving potential of MMC technology.

SA B1

SA BN

SB B1

SB BN

SCB1

SCB N

vDC

SMB

SMT

vAC

LBT

LBB

SMBT1

SMBTN

SMB B1

SMB BN

LCT

LCB

SMCT1

SMCTN

SMCB1

SMCB N

LAT

LAB

SMAT1

SMATN

SMA B1

SMA BN

SAT1

SATN

SBT1

SBTN

SCT1

SCTN

CDC1

CDC2

LDC1

LDC2


The MMC-based dc-dc converters reported to date can be classified into two broad groups

according to the arrangements and functions of the SM stacks as will now be discussed.

2.3.1 Front-to-Front Configuration

The first group of MMC-based dc-dc converters uses two ac-dc MMCs coupled via their ac

terminals to accomplish a dc-ac-dc conversion [87]. This has been called a front-to-front (FTF)

configuration to contrast with connection via the dc terminals which is commonly referred to

as a back-to-back (BTB) configuration. The three-phase version and single-phase version are

illustrated in Figure 2.15 (a) and Figure 2.15 (b) respectively. Not only do they inherit all the

benefits of the ac-dc MMC they can also block the propagation of dc fault current from either

side to the other side. The internal ac-stage waveform and frequency can be freely chosen to

prioritise the increase in overall efficiency or decrease in the converter volume or a

combination of the two [178]–[180]. The transformer-coupled configuration can provide

galvanic isolation and the turns-ratio provides for a wide choice of voltage conversion. The

transformer-less configuration may offer advantages in system footprint and overall efficiency

[88]. There are also many choices of SM type and stack configuration that could be made to

suit particular application requirements [87], [103], [181]–[183], and the relatively maturity of

the sub-system technologies and the commercial experience in ac-dc MMCs can contribute a

lot to the practical design and implementation of these front-to-front dc-dc converters.

However, the front-to-front converter has the disadvantage that the full throughput power is

processed twice through the pair of MMC converters. The double-conversion arrangement

leads to low power device utilisation (each phase leg has to process 1/3 or 1/2 of the power

throughput) and high power losses. Further, the configuration is also bulky because there are

12 SM stacks in the three-phase version or 8 stacks in the single-phase version. Each stack

requires a large volume of capacitive energy storage and needs isolation clearances to

neighbouring stacks and the valve hall walls. Thus, the power density is poor and the cost will

be high for installation on offshore platforms or in substations where land is expensive [26],

[64]. In addition, it also needs a rotation and selection algorithm to balance all the SM capacitor

voltages and the hard-switching condition might need improvement for some medium voltage

application cases.


(a)

(b)

Figure 2.15. Front-to-front based MMCs for dc-ac-dc conversion. (a) Three-phase version. (b). Single-

phase version.

vLS

LLSA T

LLSA B

LLSC T

LLSC B

LLSB T

LLSB B

vAC1

vHS

LHSA T

LHSA B

LHSC T

LHSC B

LHSB T

LHSB B

vAC2

= N1

N2

vAC1vAC2

= rT

SMHSA T1

SMHSA TN

SMHSAB1

SMHSABN

SMHSBT1

SMHSBTN

SMHSB B1

SMHSB BN

SMHSCT1

SMHSCTN

SMHSCB1

SMHSCBN

SMLSA T1

SMLSA TN

SMLSBT1

SMLSBTN

SMLSCT1

SMLSCTN

SMLSCT1

SMLSCTN

SMLSBT1

SMLSBTN

SMLSA T1

SMLSA TN

vLS

LLS1

LLS2

LLS3

LLS4

vAC1

vHS

LHS3

LHS4

LHS1

LHS2

vAC2

= N1

N2

vAC1vAC2

= rT

SMHS11

SMHS1N

SMHS31

SMHS3N

SMHS21

SMHS2N

SMHS41

SMHS4N

SMLS11

SMLS1N

SMLS31

SMLS3N

SMLS21

SMLS2N

SMLS41

SMLS4N


2.3.2 Direct-Chain-Link Configuration

Another group of MMC-based dc-dc converters uses only one MMC-like configuration

(single-phase MMC leg or multi-phase MMC legs) to accomplish a single-stage direct dc-dc

conversion [176], [184]. This is usually called as direct-chain-link (DCL) configuration. The

basic single-phase leg and two-phase legs (push-pull) version are illustrated in Figure 2.16 (a)

and Figure 2.16 (b) respectively. Three-phase variations and bipolar arrangements can be

provided similarly [185]–[188], and the filter design can be either a passive configurations [85],

[189], or an active configurations [190]–[192]. Based on this direct-chain-link concept, many

further topologies can be derived for multiport configurations [193], [194]. All of these direct-

chain-link modular multilevel dc-dc converters avoid an explicit internal ac stage in the

conversion process. An important feature is that, a fraction of the SMs in the stack are utilised

on both high-voltage side and low-voltage side, and therefore there are expected advantages in

power device utilisation, overall conversion efficiency and system footprint, especially in

comparison to the front-to-front circuits. However, the direct-chain-link dc-dc converters also

need to overcome some technical difficulties before they can be applied to the dc network

interconnection. Firstly, although there is no separate and explicit ac stage in the conversion

process, the circuits still rely on internal-circulating ac currents to balance the stack energies in

normal operation. These currents could cause large current amplitude stresses and power losses

for both SM switches and filters in the operation [195], [196]. Moreover, the filter design in

these circuits need to overcome some challenges, notably, to avoid the extremely large

inductance in a passive filter [185], [197] or reduce the expense of an active filter with SMs

arrangement [188], [192]. Further, this direct dc-dc conversion cannot block high-voltage side

dc fault current if half-bridge SMs are utilised in stack. The low-side dc terminal has a path for

fault current through the diodes of the half-bridge SMs (similar in nature to the dc fault current

path in classic ac-dc MMC [167]), and extra fast protection equipment would be required for

these converters in the dc network interconnection. Lastly, all the SM switches are operated in

hard switching condition and a control algorithm is needed to balance the SM capacitor

voltages.

2.4 Chapter Summary 41

(a) (b)

Figure 2.16. Direct-chain-link based MMCs for dc-dc conversion. (a) Single-phase leg version. (b).

Two-phase legs (push-pull) version.

2.4 Chapter Summary

Dc-dc power conversion has always been an important research area in power electronics. In

recent years, medium voltage and high voltage dc-dc conversion has emerged as a vigorous

topic to support the increased interest in dc technology for renewable energy integration and

electricity networks expansion.

Following the rapid development and great success of the ac-dc MMC since it was first

proposed nearly two decades ago, there has been much interest and research work on adoptions

and reconfigurations of this technology to form modular multilevel dc converters for both high

step-ratio and low-step-ratio dc-dc applications. The emphasis on this approach is expected to

continue, and perhaps even dominate, in the next decade ahead due to the huge impact and

cost-saving potential of MMC technology. The two large groups of modular multilevel dc-dc

topologies, namely the front-to-front and direct-chain-link MMC-based dc-dc converters, have

potential to solve the major difficulties that exist in attempting to scale-up the classic dc-dc

circuits discussed in Section 2.1 and Section 2.2 for medium voltage and high voltage

vHS

LT

LB

vLS Filter

Filte

r

SMB1

SMB N

SMT1

SMTN

vHS

LT2

LB2

LT1

LB1

vLSFilter

SMT11

SMT1N

SMT21

SMT2N

SMB11

SMB1N

SMB21

SMB2N


applications. However, these new dc-dc topologies also raise many new issues and problems

that have to be addressed, such as the low power device utilisation, low power density and high

power losses for front-to-front configurations and high current stress, expensive filter design

and complicate energy balancing for direct-chain-link configurations.

The MMC technology and its recent variations provide inspiration and a possible path toward

favourable dc-dc solutions that overcome the challenges of cost, density, efficiency and

reliability in multi-voltage dc networks interconnection. Nonetheless, there still needs to be

much effort in the enhancement and development of this technology for specific medium

voltage level or high voltage level, high step-ratio or low step-ratio dc-dc conversion.

The challenge for the work reported in this thesis is to explore the further possibility of

combining the up-to-date MMC technology (noted Section 2.3) with the classic dc-dc circuits

(noted in Section 2.1 and Section 2.2) in order to systematically propose several competitive

modular multilevel dc converters, and then to devise suitable modulation methods and control

schemes. The intention is that the new circuits not only inherit the main advantages from both

MMC technologies and classic dc-dc circuits but also avoid the major disadvantages from these

two. The objectives are to achieve low-cost, high-compactness, high-efficiency and high-

reliability conversion for medium voltage level and high voltage level dc interconnection and

thereby make a contribution to realising multi-voltage dc networks.

Across the next four chapters (Chapter 3 to Chapter 6), the new modular multilevel dc

converters and their associated modulation methods and control schemes will be explored for

the combinations of high step-ratio and low step-ratio, medium voltage level and high voltage

level.

Chapter 3 High Step-ratio Resonant Modular

Multilevel DC Converter for MVDC Applications

This chapter introduces a family of resonant modular multilevel dc converters (RMMCs) for

bidirectional high step-ratio conversion between MVDC and LVDC distribution networks.

First, a basic high step-ratio RMMC topology is proposed in Section 3.1, which can be seen as

an extension from the classic LLC resonant circuit by introducing MMC-like stack of SMs in

place of the half-bridge or full-bridge inverter in the original configuration. It inherits the

advantages of the original LLC circuit from LVDC applications, and so soft-switching

operation is achieved for all the switches to decrease switching losses and increase power

efficiency. It utilises the MMC-like structure to support the MVDC stress and the modular

structure can provide high reliability.

Second, a phase-shift modulation scheme for this converter is further proposed in Section 3.2.

The effective switching frequency for resonant operation can be several times greater than that

of each SM, which has benefit for stack physical volume reduction. Moreover, this phase-shift

modulation creates an inherent balancing mechanism that ensures all the SM capacitor voltages

are balanced. The available flexibility in the choice of phase-shift value and SM duty-cycle

provides a wide range of step-ratio values. Design guidelines are derived and presented, and

modulation constraints are determined so that soft-switching and inherent-balancing capability

are maintained for all the step-ratio cases.

The overall performance of the basic high step-ratio RMMC is investigated in detail in Section

3.3, which includes the analysis of SM stack rating, step-ratio range and the voltage and current

stresses. Some of the key parameters are compared with other popular MMC-based dc-dc

alternatives to demonstrate the merits of this circuit for medium voltage level high step-ratio

applications.

44 High Step-ratio Resonant Modular Multilevel DC Converter for MVDC Applications

As an extension, it will be shown that this basic high step-ratio RMMC can serve as a starting

point for variety of further configurations. A series of derived topologies is discussed in Section

3.4 and Section 3.5. These derivative configurations form a family of high step-ratio RMMCs,

which shares all the operational advantages of the basic RMMC but addresses its limitations in

order to satisfy a wider range of specifications for MVDC and LVDC interconnection.

The results of full-scale simulation examples and down-scaled prototype experiments are

provided and analysed in Section 3.6 and Section 3.7 to verify the theoretical analysis and

demonstrate the potential for practical high step-ratio applications.

3.1 Topology Derivation and Description

The topology of the basic high-step ratio RMMC is derived from the classic LLC circuit with

an MMC-like stack replacing the primary-side half-bridge or full-bridge inverter configuration,

and its detailed schematic is shown in Figure 3.1. The high-voltage side (MVDC side) circuit

contains a stack of 𝑁 half-bridge SMs to support the high-side terminal voltage 𝑣𝐻𝑆 and it is

also connected to the primary winding 𝑁1 of the internal transformer. The leakage inductance

of the transformer can be served as the resonant inductance 𝐿𝑟, and the magnetizing inductor

𝐿𝑚 appears in parallel and provides the return path for the dc current component. An active

full-bridge rectifier/inverter (𝑆1, 𝑆2, 𝑆3, 𝑆4) with fully controllable IGBT devices is utilised to

connect the secondary winding 𝑁2 to the low-side (LVDC side) capacitor 𝐶𝐿𝑆, enabling the

bidirectional power conversion.

The arrows in Figure 3.1 denote the reference directions of the stack voltage 𝑣𝑆𝑇, SM voltage

𝑣𝑆𝑀 , upper switch voltage 𝑣𝑢𝑝 , lower switch voltage 𝑣𝑙𝑜𝑤 , SM capacitor voltage 𝑣𝐶 ,

transformer voltage on the primary side 𝑣𝑃 and secondary side 𝑣𝑆, stack current 𝑖𝑆𝑇, secondary-

side current 𝑖𝑆, upper switch current 𝑖𝑢𝑝 and lower switch current 𝑖𝑙𝑜𝑤. The turns-ratio of the

internal transformer is denoted as 𝑟𝑇=𝑁1/𝑁2, and the stack modulation ratio is defined as 𝑟𝑆 =

𝑣𝐻𝑆/𝑟𝑇𝑣𝐿𝑆, indicating the voltage conversion achieved within the SM stack itself. The overall

step-ratio of this converter is denoted as 𝑅 = 𝑣𝐻𝑆/𝑣𝐿𝑆 = 𝑖𝐿𝑆/𝑖𝐻𝑆, where 𝑣𝐻𝑆 and 𝑖𝐻𝑆 are the

3.2 Operating Principle and Flexible Phase-shift Modulation 45

voltage and current on the high-voltage side while 𝑣𝐿𝑆 and 𝑖𝐿𝑆 are the voltage and current on

the low-voltage side.

Figure 3.1. Basic high step-ratio resonant modular multilevel dc converter.

3.2 Operating Principle and Flexible Phase-shift Modulation

This SM stack is utilised to support the high-side MVDC terminal voltage. By switching either

𝑦 or 𝑥 SM capacitors into the circuit (0 < 𝑦 < 𝑥 ≤ 𝑁) for equal durations, a symmetrical

square-wave voltage 𝑣𝑃 can be obtained and imposed across the primary winding of the

internal transformer. The positive stage is defined as 𝑦 SMs switched in, the stack voltage is

less than 𝑣𝐻𝑆 and a positive voltage across 𝐿𝑚. In the negative stage, 𝑥 SMs are switched in

and the voltage across 𝐿𝑚 is negative. This symmetrical square-wave voltage excites an energy

exchange between the SM capacitors (𝐶1 to 𝐶𝑁) and the resonant inductor 𝐿𝑟, which together

constitute the resonant tank of this high step-ratio RMMC. The dc component of the stack

current, 𝑖𝑆𝑇−𝑑𝑐 , passes through the magnetizing inductor while the ac component of stack

current, 𝑖𝑆𝑇−𝑎𝑐 , flows into the primary winding of transformer and becomes the secondary-side

current 𝑖𝑆 with turns-ratio conversion. The secondary-side current 𝑖𝑆 flows through 𝑆1 and 𝑆4

Lr

C2

CN

vSM2

vSMN S1 S3

S2 S4

Lm CLSN2

C1

vSM1

iST

vS

T

N1

vST

CHS

Upper Switch

Lower Switch

Sub-module(SM)

iS

vP

iLS

iHS

vHS

vLS

iup

ilow

vlow

vup

vC


when it is positive and the resonant tank is being charged in this period, while 𝑆2 and 𝑆3

conduct when 𝑖𝑆 is negative and the resonant tank is discharging for this duration.

The voltage relationship derived from the positive and negative stages can be written as (3.1)

and (3.2) respectively, given the assumptions that all of the SM capacitor voltages are well-

balanced at their average value 𝑣𝐶 and the voltage across 𝐿𝑟 is far smaller than the dc terminal

voltages 𝑣𝐻𝑆 and 𝑣𝐿𝑆.

𝑣𝐻𝑆 − 𝑦𝑣𝐶 = 𝑟𝑇𝑣𝐿𝑆 (3.1)

𝑣𝐻𝑆 − 𝑥𝑣𝐶 = −𝑟𝑇𝑣𝐿𝑆 (3.2)

Then, the overall step-ratio 𝑅 between the high-side voltage 𝑣𝐻𝑆 and low-side voltage 𝑣𝐿𝑆 is

described in (3.3) and the average voltage of the SM capacitors 𝑣𝐶 is derived (3.4).

𝑅 =𝑣𝐻𝑆

𝑣𝐿𝑆= 𝑟𝑆𝑟𝑇 =

𝑥 + 𝑦

𝑥 − 𝑦𝑟𝑇 (3.3)

𝑣𝐶 =2𝑣𝐻𝑆

𝑥 + 𝑦=

2𝑟𝑇𝑣𝐿𝑆

𝑥 − 𝑦 (3.4)

For resonant frequency, the proposed RMMC has some differences with the classic LLC circuit

since it has two resonant frequencies in one cycle. In the positive stage, the capacitors of 𝑦

SMs join a resonant circuit with inductor 𝐿𝑟 , and its resonance assists the switches of the

inserted SMs to achieve soft-switching operation. The remaining 𝑁 − 𝑦 SMs are bypassed in

this stage. The inserted 𝑦 capacitors are in series connection with inductor 𝐿𝑟 , and so the

resonant frequency in this positive stage, 𝑓𝑝, is presented in (3.5) under the assumption that

each SM capacitance equals 𝐶𝑆𝑀. Likewise, the resonant frequency in negative stage, 𝑓𝑛, is

given in (3.6), in which 𝑥 SM capacitors are deployed in the stack in series with 𝐿𝑟 and 𝑁 − 𝑥

SMs are bypassed in this stage.

𝑓𝑝 =√𝑦

2𝜋 ∙ √𝐿𝑟𝐶𝑆𝑀

(3.5)


𝑓𝑛 =√𝑥

2𝜋 ∙ √𝐿𝑟𝐶𝑆𝑀

(3.6)

To balance all the SM capacitor voltages in operation and also to increase the frequency of the

stack voltage 𝑣𝑆𝑇 and square-wave voltage 𝑣𝑃 for converter volume reduction, a phase-shift

modulation scheme is developed here. All the upper switches of the SMs are operated with a

duty-cycle value of (𝑥 + 𝑦)/2𝑥, and each SM switching sequence keeps a phase-shift value of

2𝜋/𝑥 with respect to the previous one. In this manner, the SM voltages will form a sequence

of voltage pulses with a phase-shift value of 2𝜋/𝑥 and the SM capacitors can join the circuit

resonant operation according to a preset sequence for voltage balancing. Also, the frequency

of the stack voltage 𝑣𝑆𝑇 and square-wave voltage 𝑣𝐿𝑚 will be increased to 𝑥/(𝑥 − 𝑦) times

greater than that of each SM switching frequency 𝑓𝑠, which could largely reduce the volume of

the passive components, including the dc link capacitors, SM capacitors, resonant inductor and

internal transformer. The voltage frequency of 𝑣𝑆𝑇 and 𝑣𝐿𝑚 is denoted as the effective

frequency 𝑓𝑒 in this circuit, and it is normally chosen at a value between 𝑓𝑝 and 𝑓𝑛 (𝑓𝑝 < 𝑓𝑒 =

𝑥

𝑥−𝑦𝑓𝑠 < 𝑓𝑛), which would make the RMMC operated in continuous current mode (CCM) in

positive stage and in discontinuous current mode (DCM) in negative stage to trade-off the

conduction losses and switching losses for the best overall efficiency [91]. The square-wave

voltage 𝑣𝑝, stack current 𝑖𝑆𝑇 and magnetizing inductor current 𝑖𝐿𝑚 are depicted in Figure 3.2

to illustrate the normal operation of the resonant tank of this RMMC.

Figure 3.2. Operation waveforms of the resonant tank.

fe

vP

iLm0 t

rTvLS

rTvLS

iST

v 1


3.2.1 Basic Operation with Highest Step-ratio Conversion

For further explanation of the operating principle in each SM, a detailed example with 𝑦 = 4

and 𝑥 = 𝑁 = 5 is given in Figure 3.3, in which the voltage waveform of each SM (𝑣𝑆𝑀1, 𝑣𝑆𝑀2,

𝑣𝑆𝑀3, 𝑣𝑆𝑀4, 𝑣𝑆𝑀5) is coloured black when the upper switch of this SM is on (SM capacitor

inserted) and coloured red when the lower switch is on (SM capacitor bypassed). For the stack

voltage 𝑣𝑆𝑇 and magnetizing inductor voltage 𝑣𝐿𝑚 , the waveforms are coloured red for the

positive stages and black for the negative ones. In the circuit operation diagrams, solid arrows

indicate the current direction when power flow is from the high-side terminal to the low-side

terminal, and dash arrows for current flow when the power flow is reversed. For the SMs, the

bold black box means this SM is inserted into the resonant path and the current passes through

its capacitor (meaning that the upper switch of this SM is on and the lower is off) while the

pink box means this SM is bypassed (meaning that the upper switch of this SM is off and the

lower is on). The SM operation waveforms with upper switch detail and lower switch detail

are provided in Figure 3.4 (a) and Figure 3.4 (b) respectively. 𝑣𝑢𝑝 and 𝑣𝑙𝑜𝑤 are the voltages

across the upper switch and lower switch, and 𝑖𝑢𝑝 and 𝑖𝑙𝑜𝑤 are the currents through the upper

switch and lower switch.

In Figure 3.3, it can be seen that each SM voltage waveform has one red negative pulse in each

2π cycle. This pulse takes 10% period of a 2π cycle and keeps 0.4π phase-shift with respect to

the same pulses of the previous SM. It means that each SM capacitor is inserted into the circuit

with 90% period of a 2π cycle, and each SM insertion is phase-shifted by 0.4π with respect to

the previous one. It can be found that there are four SM capacitors inserted into the stack to

join the resonant operation in each positive stage, which equals 10% period of a 2π cycle. The

remaining one SM is bypassed, and each of five SMs rotates to play this bypassed role for one

positive stage. Since the negative stage SM number equals the SM total number (𝑥 = 𝑁) in this

example, all of the five SM capacitors are switched into the circuit and join the resonance in

each negative stage, which also equals 10% period of a 2π cycle. The effective frequency 𝑓𝑒

(1/𝑇𝑒) of the stack voltage 𝑣𝑆𝑇 and square-wave voltage 𝑣𝐿𝑚 is 5 times of the SM switching

frequency 𝑓𝑠 (1/𝑇𝑠) in this case (𝑇𝑠 = 5𝑇𝑒 = 2π), and the resonant frequency for positive stage

and negative stage can be derived from (3.5) and (3.6) respectively.


Figure 3.3. Operation waveforms with 𝑦 = 4, 𝑥 = 5,𝑁 = 5.

(a) (b)

Figure 3.4. SM operation waveforms. (a) Upper switch. (b) Lower switch.

Substituting the individual SM capacitor voltage (𝑣𝐶1 , 𝑣𝐶2 , 𝑣𝐶3 , 𝑣𝐶4 , 𝑣𝐶5) into the average

value equations (3.1) and (3.2), the voltage relationship of each SM capacitor for a 2π cycle is

0

0

0

0

0

vC1

vC2

vC3

vC4

vC5

Ts=5Te=2πvSM1

vSM2

vSM3

vSM4

vSM5

t

t

t

t

tvST

Te

t

0 t

0.4π

SM1

SM3

SM4

SM5

SM2

Positive Stage (P1)

Negative Stage (N)

Positive Stage (P2)

Negative Stage (N)

P1 N P2 N

vP,vLm

vC0.5vC0.5

5vC4vC

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

t

vup

fn fn fn fn fn

fp fp fp fp

0

iupvCiST

0

ilow

t

iST

vC

vlow

fp


derived and summarised in (3.7). In the equation, 𝐀𝟓,𝟒 is defined as the operation matrix, and

it denotes there are five SMs switched into the stack for the negative stage and four for the

positive stage. “1” means the SM upper switch is on and its capacitor is inserted in the circuit

whereas “0” means the lower switch is on and the capacitor is bypassed. The first five rows

represent the five individual positive stages of a 2π cycle and the sixth row indicates the

common negative stage with all the five SMs deployed. The individual SM capacitor voltage

can be found from (3.7) and are written in (3.8). It means that all the SM capacitor voltages of

this converter naturally balance at the value of 2𝑣𝐻𝑆/9 as an inherent feature of this phase-shift

modulation without the need for extra voltage adjustment. In the meantime, the overall step-

ratio can be also derived from (3.7) as 9𝑟𝑇 in this case.

[𝐀𝟓,𝟒 𝟏𝟓×𝟏

𝟏𝟏×𝟓 −1] ∙ [

𝒗𝑪𝒊

𝑟𝑇𝑣𝐿𝑉] = [

𝟏𝟓×𝟏

1] ∙ 𝑣𝐻𝑆 (3.7)

with 𝐀𝟓,𝟒 =

[ 0 1 1 1 11 0 1 1 11 1 0 1 11 1 1 0 11 1 1 1 0]

and 𝒗𝑪𝒊 =

[ 𝑣𝐶1

𝑣𝐶2 𝑣𝐶3 𝑣𝐶4

𝑣𝐶5 ]

𝑣𝐶1 = 𝑣𝐶2 = 𝑣𝐶3 = 𝑣𝐶4 = 𝑣𝐶5 = 𝑣𝐶 =2𝑣𝐻𝑆

9 (3.8)

According to (3.3), this operational example has achieved the highest step-ratio conversion of

this RMMC with five SM configuration (𝑁 = 5) since both the positive stage number y and

negative stage number 𝑥 have selected the maximum values they can have (𝑦 = 4, 𝑥 = 5), and

it is also the most basic operation case for this RMMC because there is only one SM in the

rotation for voltage balancing.

3.2.2 General Operation with Flexible Modulation

In the general operation cases, the value of 𝑦 and 𝑥 can be flexibly chosen from their minimum

to maximum in the modulation (1 ≤ 𝑦 ≤ 𝑥 − 1, 𝑦 + 1 ≤ 𝑥 ≤ 𝑁) to provide a wide operation

range and satisfy various high-step ratio dc connection.


To explain the general operation and flexible modulation more in detail, a further example is

illustrated in Figure 3.5 with 𝑦 = 3 and 𝑥 = 𝑁 = 5 to show the operating principle when

positive stage SM number 𝑦 ranges from its minimum to maximum (1 ≤ 𝑦 ≤ 𝑥 − 1, 𝑥 = 𝑁).

Figure 3.5. Operation waveforms with 𝑦 = 3, 𝑥 = 5,𝑁 = 5.

Since the negative stage SM number still equals the SM total number (𝑥 = 𝑁), the negative

stage operation is the same as that in Figure 3.3, and the positive stage and negative stage

periods still equal 10% period of a 2π cycle (π/𝑁). However, the positive stage operation

becomes different because only three SM capacitors join the resonance path. It means that two

(𝑁 − 𝑦 = 2) consecutive SMs are modulated out of the stack in sequence for each positive

stage and each SM is bypassed for two consecutive positive stages in each 2π cycle. It can be

seen in Figure 3.5 that the negative pulse period (π/𝑁) and phase-shift value (2π/𝑁) keep

the same value as that in Figure 3.3 but each SM voltage waveform has two consecutive

negative pulses in a 2π cycle. It also means that the SM switching frequency in this case is

0

0

0

0

0

vC1

vC2

vC3

vC4

vC5

2Ts=5Te=2π

t

t

t

t

t

Te

t

0 t

0.4π

P1 N P2 N

vSM1

vSM2

vSM3

vSM4

vSM5

vST

vP,vLm

SM1

SM3

SM4

SM5

SM2

Positive Stage (P1)

Negative Stage (N)

Positive Stage (P2)

Negative Stage (N)

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

5vC

3vC

vC

vC


increased twice to generate the same effective frequency (2𝑇𝑠 = 5𝑇𝑒 = 2π) as the highest

operation case in Figure 3.3, and the duty-cycle of each SM upper switch is decreased from

90% to 80% ((𝑁 + 𝑦)/2𝑁). According to (3.5) and (3.6), the negative resonant frequency

would not change compared to the basic conversion case while the positive stage frequency

would be slightly reduced.

The voltage relationship with operation matrix of 𝐀𝟓,𝟑 for a 2π cycle is given in (3.9). The

inherent balancing for SM capacitor voltages is still achieved and the capacitors adopt the

voltage expression in (3.10). The step-ratio in this operation case is 4𝑟𝑇.

[𝐀𝟓,𝟑 𝟏𝟓×𝟏

𝟏𝟏×𝟓 −1] ∙ [

𝒗𝑪𝒊


𝟏𝟓×𝟏

1] ∙ 𝑣𝐻𝑆 (3.9)

with 𝐀𝟓,𝟑 =

[ 0 0 1 1 11 0 0 1 11 1 0 0 11 1 1 0 00 1 1 1 0]

and 𝒗𝑪𝒊 =

[ 𝑣𝐶1


𝑣𝐶5 ]

𝑣𝐶1 = 𝑣𝐶2 = 𝑣𝐶3 = 𝑣𝐶4 = 𝑣𝐶5 = 𝑣𝐶 =𝑣𝐻𝑆

4 (3.10)

The operating principle and rotation mechanism will be the same as this example when positive

stage SM number 𝑦 is further decreased to 1 and 2. There will be 𝑁 − 𝑦 consecutive SMs

modulated out of the stack in sequence for each positive stage and each SMs is bypassed for

𝑁 − 𝑦 consecutive positive stages in each 2π cycle ((𝑁 − 𝑦)𝑇𝑠 = 𝑁𝑇𝑒 = 2π). The phase-shift

value is kept at 2𝜋/𝑁, and the value of the positive or negative stage period in square-wave

voltage and the value of each negative pulse period in SM voltages remain at 𝜋/𝑁, but the total

number of the consecutive negative pulses for each SM modulation needs to follow the value

of 𝑁 − 𝑦 . In this manner, it could systematically solve the voltage balancing issue when

positive stage SM number y ranges from the minimum to maximum (1 ≤ 𝑦 ≤ 𝑥 − 1, 𝑥 = 𝑁).

Then, the final example is given in Figure 3.6 with 𝑦 = 3, 𝑥 = 4 and 𝑁 = 5 to display the

general operating principle when negative stage SM number 𝑥 also ranges from the minimum

to maximum (1 ≤ 𝑦 ≤ 𝑥 − 1, 𝑦 + 1 ≤ 𝑥 ≤ 𝑁).


It can be seen in Figure 3.6 (a) and Figure 3.6 (b) that there are only four (𝑥 = 4 < 𝑁 = 5)

SMs inserted into the stack and participate in the resonant operation in each 2π cycle

((𝑥 − 𝑦)𝑇𝑠 = 𝑥𝑇𝑒 = 2π), and these four SMs are defined as the active SMs. The operation

scheme of these four SMs is the same as the operation explained in Figure 3.3 and Figure 3.5,

and the positive stage SM number 𝑦 can still be modulated from 1 to 3. The main difference is

that the remaining one SM is bypassed throughout this 2π cycle and defined as the redundant

SM, which is denoted by blue colour in both Figure 3.6 (a) (SM5 is redundant SM) and Figure

3.6 (b) (SM4 is redundant SM).

To balance the active SMs and redundant SM, it needs an “external” phase-shift scheme for

the redundant SM among different 2π cycles besides the “internal” phase-shift within each 2π

cycle for the active SMs, which means that each of the five SMs rotates to play the redundant

role for a 2π cycle. Figure 3.6 (a) shows that SM5 is bypassed throughout the first 2π cycle, and

the other four SMs resonate with inductor 𝐿𝑟. The phase-shift value between the four active

SMs in the first 2π cycle is increased to 0.5π (2𝜋/𝑥), and the value of the positive or negative

stage period and the value of each negative pulse period are adjusted to 12.5% period of a 2π

cycle (𝜋/𝑥). When the second 2π cycle begins, SM5 replaces the role of SM4 and participates

in the resonant operation while SM4 is bypassed for the whole cycle and plays the redundant

role, as shown in Figure 3.6 (b). The voltage relationships with operation matrix of 𝐀𝟒,𝟑 in these

two 2π cycles are described in (3.11) and (3.12) respectively.

[𝐀𝟒,𝟑 𝟏𝟒×𝟏

𝟏𝟏×𝟒 −1] ∙ [

𝒗𝑪𝒊𝟏


𝟏𝟒×𝟏

1] ∙ 𝑣𝐻𝑆 (3.11)

[𝐀𝟒,𝟑 𝟏𝟒×𝟏

𝟏𝟏×𝟒 −1] ∙ [

𝒗𝑪𝒊𝟐


𝟏𝟒×𝟏

1] ∙ 𝑣𝐻𝑆 (3.12)

with 𝐀𝟒,𝟑 = [

0 1 1 11 0 1 11 1 0 11 1 1 0

] ,𝒗𝑪𝒊𝟏 = [

𝑣𝐶1

𝑣𝐶2 𝑣𝐶3

𝑣𝐶4

] and 𝒗𝑪𝒊𝟐 = [

𝑣𝐶1

𝑣𝐶2 𝑣𝐶3

𝑣𝐶5

].

In the next (third) 2π cycle, SM3 replaces and SM4 returns to take part in the resonance again.

From (3.11) and (3.12), it can be derived all of the SM capacitor voltages are still inherently


balanced and their voltages adopt the value in (3.13). The step-ratio can be also obtained from

(3.11) and (3.12) as 7𝑟𝑇 in this case.

𝑣𝐶1 = 𝑣𝐶2 = 𝑣𝐶3 = 𝑣𝐶4 = 𝑣𝐶5 = 𝑣𝐶 =2𝑣𝐻𝑆

7 (3.13)

The operating principle and rotation mechanism will be the same as this example when

negative stage SM number 𝑥 is further decreased to 2 and 3. There will be 𝑁 − 𝑥 consecutive

SMs modulated out of the stack in sequence as the redundant SMs for each 2π cycle and each

redundant SM is bypassed for 𝑁 − 𝑥 consecutive 2π cycles. This “external” phase-shift scheme

could systematically solve the voltage balancing issue when negative stage SM number 𝑥 also

ranges from the minimum to maximum (𝑦 + 1 ≤ 𝑥 ≤ 𝑁).Within each 2π cycle, The value of

the phase-shift angle between active SMs and the value of the positive/negative stage period

should be adjusted to 2𝜋/𝑥 and 𝜋/𝑥 respectively, and the total number of the consecutive

negative pulses for each SM modulation needs to follow the value of 𝑥 − 𝑦.

(a)

0

0

0

0

0

vC1

vC2

vC3

vC4

vC5

T1s=4Te=2π

t

t

t

t

t

t

0 t

Te

0.5π

vC0.50.5vC

P1 N P2 N

vSM1

vSM2

vSM3

vSM4

vSM5

vST

vP, vLm

SM1

SM3

SM4

SM5

SM2

Positive Stage (P1)

Negative Stage (N)

Positive Stage (P2)

Negative Stage (N)

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

3vC

4vC

3.3 Circuit Performance Analysis 55

(b)

Figure 3.6. Operation waveforms with 𝑦 = 3, 𝑥 = 4,𝑁 = 5. (a) First 2π cycle. (b) Second 2π cycle.

Besides, since all the SMs take turns to be the redundant SMs, the faulty or unhealthy SMs can

be bypassed directly without interrupting the system operation as that in the classic MMC

[157], [161].

3.3 Circuit Performance Analysis

After the detailed description for operating principle and modulation scheme in previous

section, the performance of this high step-ratio RMMC is analysed in this section and the

operational advantages and limitations discussed. It mainly focuses on the SM stack rating,

step-ratio range, inherent-balancing capability and voltage/current stresses.

0

0

0

0

0

vC1

vC2

vC3

vC4

vC5

T2s=4Te=2π

t

t

t

t

t

t

0 t

Te

0.5π

vC0.50.5vC

P1 N P2 N

vSM1

vSM2

vSM3

vSM4

vSM5

vST

vP, vLm

SM1

SM3

SM4

SM5

SM2

Positive Stage (P1)

Negative Stage (N)

Positive Stage (P2)

Negative Stage (N)

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

3vC

4vC


3.3.1 SM Stack Rating

The physical volume and cost of SM stack are important metrics for MMC-based converters

and the required rating of the SM stack is the crucial factor, which includes the stack

semiconductor volt-ampere rating and stack capacitive energy storage.

3.3.1.1 Stack Semiconductor Volt-ampere rating

For a general MMC-based dc-dc converter, the normalised stack semiconductor volt-ampere

rating, 𝑆𝑆𝑇, can be defined as a ratio of the sum of the semiconductor volt-ampere rating to the

converter power throughput PT, shown in (3.14), where 𝑣𝑆𝑀𝑗𝑘 and 𝑖𝑆𝑀𝑗𝑘 are the rated voltage

and current of kth (half-bridge) SM power device in jth stack, 𝑁𝑗 is the number of the SMs in

jth stack and 𝑁𝑆𝑇 is the number of stacks in the circuit.

𝑆𝑆𝑇 =2∑ ∑ 𝑣𝑆𝑀𝑗𝑘

𝑁𝑗

𝑘=1𝑁𝑆𝑇𝑗=1 𝑖𝑆𝑀𝑗𝑘

𝑃𝑇=

2∑ 𝑖𝑆𝑀𝑗𝑘 ∑ 𝑣𝑆𝑀𝑗𝑘𝑁𝑗

𝑘=1𝑁𝑆𝑇𝑗=1

𝑃𝑇 (3.14)

To keep the power devices working safely within their rated voltage and current, the sum of

the 𝑣𝑆𝑀𝑗𝑘 for jth stack should be larger than the maximum value (absolute value) of jth stack

voltage and 𝑖𝑆𝑀𝑗𝑘 also needs to be larger than the maximum value (absolute value) of jth stack

current. In this manner, 𝑆𝑆𝑇 must be larger than 𝑅𝑆𝑆𝑇, which is defined as the operation required

volt-ampere rating normalised to 𝑃𝑇 and it leads to the minimum volt-ampere rating

requirement for SM stack semiconductors without considering power device safety margin.

The detailed relationship is presented in (3.15), and it needs to note that the units of numerator

and denominator in (3.14) and (3.15) are the same, so 𝑆𝑠𝑝 and 𝑅𝑠𝑝 are both ratio value without

unit.

𝑆𝑆𝑇 ≥ 𝑅𝑆𝑆𝑇 =2∑ 𝑚𝑎𝑥 |𝑣𝑆𝑇𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝑆𝑇𝑗|

𝑁𝑆𝑇𝑗=1

𝑃𝑇 (3.15)

With the analysis in (3.1) and (3.2), the stack voltage 𝑣𝑆𝑇 of the proposed high step-ratio

RMMC can be given in (3.16), which is comprised of a dc offset 𝑣𝐻𝑆 and an square-wave ac


component 𝑟𝑇𝑣𝐿𝑆. The stack current 𝑖𝑆𝑇 also has both dc and ac components. The dc component

𝑖𝑆𝑇−𝑑𝑐 is the average value of 𝑖𝑆𝑇 over each effective cycle 𝑇𝑒, which come from the high-side

terminal and flows back through the transformer magnetizing inductor, and the ac component

𝑖𝑆𝑇−𝑎𝑐 is the resonant current of this circuit, which goes through the transformer winding and

becomes the secondary-side current 𝑖𝑆 with turns-ratio conversion. It can be described as

(3.17) given the fact that the time difference between resonant cycle and effective cycle is short

and the stack current value in this short time difference is negligible.

𝑣𝑆𝑇(𝑡) = 𝑣𝐻𝑆 ∓ 𝑟𝑇𝑣𝐿𝑆 = 𝑣𝐻𝑆 − 𝑠𝑔𝑛 (𝑠𝑖𝑛2𝜋

𝑇𝑒𝑡)

𝑟𝑇𝑣𝐻𝑆

𝑅 (3.16)

𝑖𝑆𝑇(𝑡) = 𝑖𝑆𝑇−𝑑𝑐(𝑡) + 𝑖𝑆𝑇−𝑎𝑐(𝑡) = 𝑖𝐻𝑆 + 𝐼𝑟 𝑠𝑖𝑛2𝜋

𝑇𝑒𝑡 (3.17)

The amplitude of the resonant ac component current 𝐼𝑟 can be derived from (3.18) and

expressed in (3.19) under the assumption that there is no power losses in the whole conversion

process.

∫ 𝑣𝐿𝑚(𝑡)𝑖𝑆𝑇−𝑎𝑐(𝑡)𝑑𝑡𝑇𝑒

0

= 2∫ 𝑟𝑇𝑣𝐿𝑆𝐼𝑟 𝑠𝑖𝑛2𝜋

𝑇𝑒𝑡𝑑𝑡

𝑇𝑒2

0

= 𝑣𝐿𝑆𝑖𝐿𝑆𝑇𝑒 (3.18)

𝐼𝑟 =𝜋𝑖𝐿𝑆

2𝑟𝑇=

𝜋𝑅𝑖𝐻𝑆

2𝑟𝑇 (3.19)

Then, substituting the results of (3.16), (3.17) and (3.19) into (3.15), the operation required

volt-ampere rating for SM stack of this high step-ratio RMMC, 𝑅𝑆𝑆𝑇−𝐻𝑆𝑅, is shown in (3.20).

𝑅𝑆𝑆𝑇−𝐻𝑆𝑅𝑆 =𝜋𝑅2 + (𝜋 + 2)𝑅𝑟𝑇 + 2𝑟𝑇

2

𝑅𝑟𝑇 (3.20)

To make a fair comparison with other MMC stack based dc-dc alternatives, the volt-ampere

rating of the secondary-side rectifiers S1–S4 in this converter should be also taken into

consideration.


The rectifiers need to withstand the low-side terminal voltage, and their maximum voltage

stress is shown in (3.21). The secondary-side current goes through S1 and S4 in the positive

stage and goes through S2 and S3 in the negative stage. Hence, the maximum current on

rectifiers is expressed in (3.22). Thus, the operation required volt-ampere rating of the

secondary-side rectifiers is obtained in (3.23).

𝑣𝑆1−𝑚𝑎𝑥 = 𝑣𝑆2−𝑚𝑎𝑥 = 𝑣𝑆3−𝑚𝑎𝑥 = 𝑣𝑆4−𝑚𝑎𝑥 =𝑣𝐻𝑆

𝑅 (3.21)

𝑖𝑆1−𝑚𝑎𝑥 = 𝑖𝑆2−𝑚𝑎𝑥 = 𝑖𝑆3−𝑚𝑎𝑥 = 𝑖𝑆4−𝑚𝑎𝑥 =𝜋𝑅𝑖𝐻𝑆

2 (3.22)

𝑅𝑆𝑆1 = 𝑅𝑆𝑆2 = 𝑅𝑆𝑆3 = 𝑅𝑆𝑆4 =𝜋

2 (3.23)

Then, combining the results in (3.20) and (3.23), the overall required volt-ampere rating

(including both SM stack and rectifiers) of this high step-ratio RMMC is given in (3.24).

𝑅𝑆𝑆𝑇−𝐻𝑆𝑅 = 𝑅𝑆𝑆𝑇−𝐻𝑆𝑅𝑆 + 4𝑅𝑆𝑆1 =𝜋𝑅2 + (3𝜋 + 2)𝑅𝑟𝑇 + 2𝑟𝑇

2

𝑅𝑟𝑇 (3.24)

The stack volt-ampere rating expression for the standard transformer-coupled front-to-front

MMC (see Figure 2.15 in Section 2.3.1), 𝑅𝑆𝑆𝑇−𝐹𝑇𝐹, is given in (3.25) based on the analysis in

[180], [181], where 𝑁𝐻𝑆𝑆𝑇 and 𝑁𝐿𝑆𝑆𝑇 are the total stack number in the high-voltage side and in

the low-voltage side, 𝑣𝐻𝑆𝑆𝑇𝑗 and 𝑖𝐻𝑆𝑆𝑇𝑗 are the voltage and current of jth stack in the high-

voltage side, 𝑣𝐿𝑆𝑆𝑇𝑗 and 𝑖𝐿𝑆𝑆𝑇𝑗 are the voltage and current of jth stack in the low-voltage side.

It is worth noting that the calculation process in (3.25) is derived for the transformer-coupled

three-phase front-to-front MMC configuration in Figure 2.15 (a), but the result of (3.25) can

be applied directly to the transformer-coupled singe-phase front-to-front configuration in

Figure 2.15 (b).

𝑅𝑆𝑆𝑇−𝐹𝑇𝐹 =2∑ 𝑚𝑎𝑥 |𝑣𝐻𝑆𝑆𝑇𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝐻𝑆𝑆𝑇𝑗|

𝑁𝐻𝑆𝑆𝑇𝑗=1

𝑃𝑇+

2∑ 𝑚𝑎𝑥 |𝑣𝐿𝑆𝑆𝑇𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝐿𝑆𝑆𝑇𝑗|𝑁𝐿𝑆𝑆𝑇𝑗=1

𝑃𝑇


= 2 ∙6

𝑣𝐻𝑆𝑖𝐻𝑆𝑚𝑎𝑥 |

1

2𝑣𝐻𝑆 −

1

2

𝑟𝑇

𝑅𝑣𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡| ∙ 𝑚𝑎𝑥 |

1

3𝑖𝐻𝑆 +

2

3

𝑅

𝑟𝑇𝑖𝐻𝑆𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡|

+2 ∙6


1

2

𝑣𝐻𝑆

𝑅−

1

2

𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡| ∙ 𝑚𝑎𝑥 |

1

3𝑅𝑖𝐻𝑆 +

2

3𝑅𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡|

=4𝑅2 + 18𝑅𝑟𝑇 + 2𝑟𝑇

2

𝑅𝑟𝑇 (3.25)

The required semiconductor volt-ampere rating for the direct-chain-link based MMC (see

Figure 2.16 in Section 2.3.2), 𝑅𝑆𝑆𝑇−𝐷𝐶𝐿, has two different expressions for the whole step-ratio

range. When the step-ratio value 𝑅 ≥ 2, the derivation process and result are given in (3.26)

based on the analysis in [184], [198], where 𝑁𝑆𝑇𝑇 and 𝑁𝑆𝑇𝐵 are the total stack number in the

top arms and in the bottom arms, 𝑣𝑆𝑇𝑇𝑗 and 𝑖𝑆𝑇𝑇𝑗 are the voltage and current of jth stack in top

arms, 𝑣𝑆𝑇𝐵𝑗 and 𝑖𝑆𝑇𝐵𝑗 are the voltage and current of jth stack in bottom arms. The formula in

(3.26) is derived for the single-phase leg direct-chain-link MMC configuration in Figure 2.16

(a), but it can be also applied directly to two-phase legs push-pull configuration in Figure 2.16

(b). For the case of 𝑅 < 2, the detailed expression will be presented in next chapter for low

step-ratio analysis and comparison.

𝑅𝑆𝑆𝑇−𝐷𝐶𝐿 =2∑ 𝑚𝑎𝑥 |𝑣𝑆𝑇𝑇𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝑆𝑇𝑇𝑗|

𝑁𝑆𝑇𝑇𝑗=1

𝑃𝑇+

2∑ 𝑚𝑎𝑥 |𝑣𝑆𝑇𝐵𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝑆𝑇𝐵𝑗|𝑁𝑆𝑇𝐵𝑗=1

𝑃𝑇

= 2 ∙1


𝑅 − 1

𝑅𝑣𝐻𝑆 −

𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡| ∙ 𝑚𝑎𝑥 |𝑖𝐻𝑆 + 2(𝑅 − 1)𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡|

+2 ∙1


𝑣𝐻𝑆

𝑅+

𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡| ∙ 𝑚𝑎𝑥 |−(𝑅 − 1)𝑖𝐻𝑆 + 2(𝑅 − 1)𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡|

=4𝑅2 + 10𝑅 − 12

𝑅 (3.26)

The detailed comparison results among these three MMC-based dc-dc converters are presented

in Figure 3.7 with the transformer turns-ratio 𝑟𝑇 = 1, in which the SM stacks take all the duty

for the high step-ratio voltage conversion, and the results with the case of 𝑟𝑇 = 5 are provided


in Figure 3.8, in which the internal transformers undertake the major task of voltage conversion

for the proposed RMMC and front-to-front MMC.

Figure 3.7. Comparison for operation required volt-ampere rating (𝑟𝑇 = 1).


From Figure 3.7 and Figure 3.8, it can be seen that the values of 𝑅𝑆𝑆𝑇−𝐻𝑆𝑅 , 𝑅𝑆𝑆𝑇−𝐷𝐶𝐿 and

𝑅𝑆𝑆𝑇−𝐹𝑇𝐹 are all increased as step-ratio rises, which indicates that the high step-ratio

conversion would need larger volt-ampere rating requirement for semiconductors than that in

low step-ratio conversion for all of the three topologies. More importantly, the value for the

proposed high step-ratio RMMC, 𝑅𝑆𝑆𝑇−𝐻𝑆𝑅 , is generally below 40 (normalised to power

throughput) for the case of 𝑟𝑇 = 1 (stack modulation ratio dominant) and below 20 for the case

Step-Ratio R

Ope

ratio

n R

equi

red

Vol

t-am

pere

Rat

ing

RS S

T

6 107 8 9

RSST-FTF

RSST-HSR

RSST-DCL40

20

80

0

60

Step-Ratio R

Ope

ratio

n R

equi

red

Vol

t-am

pere

Rat

ing

RS S

T

6 107 8 9

RSST-FTF

RSST-HSR

RSST-DCL40

20

80

0

60


of 𝑟𝑇 = 5 (transformer turns-ratio dominant) in the presented high step-ratio conversion range.

These values are smaller than 𝑅𝑆𝑆𝑇−𝐹𝑇𝐹 and 𝑅𝑆𝑆𝑇−𝐷𝐶𝐿 for the front-to-front and direct-chain-

link based MMC alternatives, and they demonstrate the advantage of the proposed RMMC in

both stack ratio dominant case and transformer ratio dominant case, which may imply that the

proposed RMMC could save some physical volume and cost in its semiconductor design in the

high step-ratio applications compared to other MMC-based dc-dc topologies [87], [176].

In addition, it is worth noting that the results in Figure 3.7 and Figure 3.8 represent the situation

that the SM stacks shoulder the task for the variable step-ratio operation. If the converter in the

operation process only needs to satisfy one fixed voltage step-ratio, the stack modulation ratio

and transformer turns-ratio of this RMMC can find an optimum combination in the circuit

design process to achieve a minimum value of 𝑅𝑆𝑆𝑇 based on the formula of (3.24). Also, it

needs to mention the difference of semiconductor voltage and current rating is not considered

in the analysis of 𝑅𝑆𝑆𝑇. The stack ratio dominant case leads to lower stack voltage but higher

current according to (3.16) and (3.17), which may need less power device number but with

higher current rating requirement, while the transformer ratio dominant case results in higher

stack voltage but lower current, which would require more power device number but with lower

current requirement.

3.3.1.2 Stack Capacitive Energy Storage

Similarly to (3.13), the stack capacitive energy storage, normalised to the power throughput, is

defined as 𝐸𝑆𝑇 and given by (3.27), where 𝐶𝑗𝑘 and 𝑣𝐶𝑗𝑘∗ are the capacitance value and the

reference voltage for kth SM in jth stack.

𝐸𝑆𝑇 =∑ ∑

12𝐶𝑗𝑘𝑣𝐶𝑗𝑘

∗2𝑁𝑗


𝑃𝑇 (3.27)

The stack capacitors need to absorb and release the energy fluctuations from the varying current

flow of the stacks, so the SM capacitor voltage varies in the operation. The peak-to-peak range

of the capacitive energy storage is expressed in (3.28), where 𝑣𝐶𝑗𝑘−𝑚𝑎𝑥 and 𝑣𝐶𝑗𝑘−𝑚𝑖𝑛 are the


maximum and minimum voltage allowed for kth SM capacitor in jth stack, and 𝛾 is the

maximum ripple percentage (𝑣𝐶𝑗𝑘−𝑚𝑎𝑥 = (1 + 𝛾)𝑣𝐶𝑗𝑘∗ , 𝑣𝐶𝑗𝑘−𝑚𝑖𝑛 = (1 − 𝛾)𝑣𝐶𝑗𝑘

∗ ).

𝐸𝑆𝑇−𝑝𝑡𝑝 =∑ ∑ (

12𝐶𝑗𝑘𝑣𝐶𝑗𝑘−𝑚𝑎𝑥

2 −12𝐶𝑗𝑘𝑣𝐶𝑗𝑘−𝑚𝑖𝑛

2 )𝑁𝑗


𝑃𝑇

=∑ ∑ {

12𝐶𝑗𝑘[(1 + 𝛿)𝑣𝐶𝑗𝑘

∗ ]2−

12𝐶𝑗𝑘[(1 − 𝛿)𝑣𝐶𝑗𝑘

∗ ]2}

𝑁𝑗


𝑃𝑇= 4𝛾𝐸𝑆𝑇 (3.28)

To balance the SM voltages within the nominal range, the value of 𝐸𝑆𝑇−𝑝𝑡𝑝 should be larger

than the operation generated energy deviation 𝐺𝐸𝐷𝑆𝑇−𝑝𝑡𝑝, which is defined a ratio of the sum

of the peak-to-peak energy deviation of each stack to the converter power throughput 𝑃𝑇, as

shown in (3.29), where ∆𝐸𝑆𝑇𝑗 denotes the energy deviation of jth stack and it depends on the

varying stack voltage and current in the operation.

𝐸𝑆𝑇−𝑝𝑡𝑝 ≥ 𝐺𝐸𝐷𝑆𝑇−𝑝𝑡𝑝 =∑ (𝑚𝑎𝑥 ∆𝐸𝑆𝑇𝑗 − 𝑚𝑖𝑛 ∆𝐸𝑆𝑇𝑗)

𝑁𝑆𝑇𝑗=1

𝑃𝑇

= ∑ (𝑚𝑎𝑥∆𝐸𝑆𝑇𝑗

𝑃𝑇− 𝑚𝑖𝑛

∆𝐸𝑆𝑇𝑗

𝑃𝑇)

𝑁𝑆𝑇

𝑗=1 (3.29)

The operation required stack capacitive energy storage 𝑅𝐶𝐸 is then defined as 𝐺𝐸𝐷𝑆𝑇−𝑝𝑡𝑝/4𝛾,

which should be smaller than the value of 𝐸𝑆𝑇, and the expression is given in (3.30).

𝐸𝐶𝐸 ≥ 𝑅𝐸𝑆𝑇 =𝐺𝐸𝐷𝑆𝑇−𝑝𝑡𝑝

4𝛾=

1

4𝛾∑ (𝑚𝑎𝑥

∆𝐸𝑆𝑇𝑗


∆𝐸𝑆𝑇𝑗

𝑃𝑇)

𝑁𝑆𝑇

𝑗=1 (3.30)

In this manner, the operation required SM stack capacitive energy storage of this high step-

ratio RMMC, 𝑅𝐶𝐸−𝐻𝑆𝑅, is presented in (3.31). With (3.16), (3.17) and (3.19), its stack energy

deviation is given in (3.32).

𝑅𝐸𝑆𝑇−𝐻𝑆𝑅 =1

4𝛾(𝑚𝑎𝑥

∆𝐸𝑆𝑇−𝐻𝑆𝑅



𝑃𝑇) (3.31)



𝑃𝑇=

1

𝑣𝐻𝑆𝑖𝐻𝑆∫ 𝑣𝑆𝑇(𝑡)𝑖𝑆𝑇(𝑡)𝑑𝑡

𝑡

0

= ∫ {1 − 𝑠𝑔𝑛 [𝑠𝑖𝑛2𝜋𝑥

𝑇𝑠(𝑥 − 𝑦)𝑡]

𝑟𝑇

𝑅} ∙

𝑡

0

[1 +𝜋𝑅

2𝑟𝑇𝑠𝑖𝑛

2𝜋𝑥

𝑇𝑠(𝑥 − 𝑦)𝑡] 𝑑𝑡 (3.32)

It is worth noting that this high step-ratio RMMC needs dc link capacitors at dc terminals, but

the sum of their required capacitive energy store are smaller than that in SM stack, and their

capacitance can be largely reduced by interleave configuration with phase-shift operation. With

these considerations, they are not taken account into the comparison of SM stack energy storage

requirement with other MMC-based dc-dc converters.

For a transformer-coupled front-to-front MMC (including three-phase and sing-phase) and

direct-chain-link MMC (including single-phase leg and two-phase leg with 𝑅 ≥ 2 ), the

expressions of the required stack capacitive energy store and the relevant stack energy

deviations are provided in (3.33)–(3.38) based on the analysis in [198]–[200].

𝑅𝐸𝑆𝑇−𝐹𝑇𝐹 =1


∆𝐸𝐻𝑆𝑆𝑇𝑗


∆𝐸𝐻𝑆𝑆𝑇𝑗

𝑃𝑇)

𝑁𝐻𝑆𝑆𝑇

𝑗=1

+1


∆𝐸𝐿𝑆𝑆𝑇𝑗


∆𝐸𝐿𝑆𝑆𝑇𝑗

𝑃𝑇)

𝑁𝐿𝑆𝑆𝑇

𝑗=1

=1

4𝛾(𝑚𝑎𝑥

6∆𝐸𝐻𝑆𝑆𝑇𝑗



𝑃𝑇) +

1

4𝛾(𝑚𝑎𝑥

6∆𝐸𝐿𝑆𝑆𝑇𝑗



𝑃𝑇) (3.33)


𝑃𝑇=

6

𝑣𝐻𝑆𝑖𝐻𝑆∫ (

1

2𝑣𝐻𝑆 −

1

2

𝑟𝑇


2𝜋

𝑇𝑠𝑡) ∙ (

1

3𝑖𝐻𝑆 +

2

3

𝑅

𝑟𝑇𝑖𝐻𝑆𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡) 𝑑𝑡

𝑡

0

= ∫ (−2 𝑠𝑖𝑛22𝜋

𝑇𝑠𝑡 +

2𝑅2 − 𝑟𝑇2

𝑅𝑟𝑇𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡 + 1)

𝑡

0

𝑑𝑡 (3.34)


𝑃𝑇=

6


1

2

𝑣𝐻𝑆

𝑅−

1

2

𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡) ∙ (

1

3𝑅𝑖𝐻𝑆 +

2


2𝜋


𝑡

0


= ∫ (−2𝑠𝑖𝑛22𝜋

𝑇𝑠𝑡 + 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡 + 1)

𝑡

0

𝑑𝑡 (3.35)

𝑅𝐸𝑆𝑇−𝐷𝐶𝐿 =1


∆𝐸𝑆𝑇𝑇𝑗



𝑃𝑇)

𝑁𝑆𝑇𝑇

𝑗=1

+1


∆𝐸𝑆𝑇𝐵𝑗



𝑃𝑇)

𝑁𝑆𝑇𝐵

𝑗=1

=1

4𝛾(𝑚𝑎𝑥




𝑃𝑇) +

1

4𝛾(𝑚𝑎𝑥




𝑃𝑇) (3.36)


𝑃𝑇=

1


𝑅 − 1


𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡) ∙ [𝑖𝐻𝑆 + 2(𝑅 − 1)𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡] 𝑑𝑡

𝑡

0

= ∫ [−2(𝑅 − 1)

𝑅𝑠𝑖𝑛2

2𝜋

𝑇𝑠

𝑡 +2𝑅2 − 4𝑅 + 1

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠

𝑡 +𝑅 − 1

𝑅]

𝑡

0

𝑑𝑡 (3.37)


𝑃𝑇=

1


𝑣𝐻𝑆

𝑅+

𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡) ∙ [−(𝑅 − 1)𝑖𝐻𝑆 + 2(𝑅 − 1)𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋


𝑡

0

= ∫ [2(𝑅 − 1)

𝑅𝑠𝑖𝑛2

2𝜋

𝑇𝑠

𝑡 +𝑅 − 1

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠

𝑡 −𝑅 − 1

𝑅]

𝑡

0

𝑑𝑡 (3.38)

The analysis and comparison results with high step-ratio 𝑅 = 9, switching frequency 𝑓𝑠 =

500 Hz and maximum ripple 𝛾 = 10% are given in Figure 3.9 and Figure 3.10 for the case of

𝑟𝑇 = 1 and 𝑟𝑇 = 5 respectively.

First, it can be observed that the stack energy of the RMMC in each effective cycle

((𝑥 − 𝑦)𝑇𝑠 = 𝑥𝑇𝑒) is naturally balanced in both cases as the front-to-front and direct-chain-link

configurations, which means the dc energy from the dc terminal and ac energy from the

resonant tank balance each other in the SM stack without the requirement for extra adjustments.

Moreover, the required stack energy storage sum for this RMMC is about 4.5 kJ/MVA in the

stack ratio dominant case and about 2.3 kJ/MVA in the transformer ratio dominant case, which

are both clearly smaller values than those for front-to-front and direct-chain-link circuits with


the same operation conditions. So, there would be some saving in SM capacitor volume and

cost with this RMMC compared to the other MMC-based dc-dc alternatives.

Figure 3.9. Comparison for stack energy deviation and operation required capacitive energy storage

(𝑅 = 9, 𝑟𝑇 = 1, 𝑓𝑠 = 500 Hz, 𝑦 = 4, 𝑥 = 5, 𝛾 = 10%,𝑅𝐸𝑆𝑇−𝐻𝑆𝑅 ≈ 4.5 kJ/MVA, 𝑅𝐸𝑆𝑇−𝐹𝑇𝐹 ≈ 30 kJ/

MVA, 𝑅𝐸𝑆𝑇−𝐷𝐶𝐿 ≈ 22.5 kJ/MVA).


(𝑅 = 9, 𝑟𝑇 = 5, 𝑓𝑠 = 500 Hz, 𝑦 = 2, 𝑥 = 5, 𝛾 = 10%,𝑅𝐸𝑆𝑇−𝐻𝑆𝑅 ≈ 2.3 kJ/MVA, 𝑅𝐸𝑆𝑇−𝐹𝑇𝐹 ≈ 8.0 kJ/

MVA, 𝑅𝐸𝑆𝑇−𝐷𝐶𝐿 ≈ 22.5 kJ/MVA).

Additionally, it need to note that there is also an optimized combination of the stack modulation

ratio and transformer turns-ratio in the circuit design process for this RMMC to achieve a

minimum value of 𝑅𝐸𝑆𝑇 for the fixed ratio conversion, but this combination would not match

Stac

k E

nerg

y D

evia

tion

(kJ/

MV

A)

0.0 0.4 0.8 1.2 1.6 2.0

14.0

10.0

6.0

2.0

-2.0

ΔESTBj/PT

6ΔELSSTj/PT

ΔESTTj/PT

6ΔEHSSTj/PT

ΔEST-HSR/PT

Stac

k E

nerg

y D

evia

tion

(kJ/

MV

A)

0.0 0.4 0.8 1.2 1.6 2.0

10.5

7.5

4.5

1.5

-1.5

ΔESTBj/PT

6ΔELSSTj/PT

ΔESTTj/PT

6ΔEHSSTj/PT

ΔEST-HSR/PT


the optimum design for minimum 𝑅𝑆𝑆𝑇 as introduced in previous sub-section, which may need

a trade-off design between the minimum semiconductor cost and minimum capacitor volume.

3.3.2 Wide Step-ratio Range in Operation

To analyse the step-ratio flexibility of this RMMC during operation (i.e. once the transformer

turns-ratio is decided in the circuit design), the minimum and maximum expression for overall

step-ratio 𝑅 with fixed transformer turns-ratio 𝑟𝑇 are presented in (3.39) and (3.40)

respectively. In (3.39), the positive stage number 𝑦 selects the minimum value while the

negative stage number 𝑥 chooses the maximum (𝑦 = 1, 𝑥 = 𝑁). In (3.40), both the positive

stage number 𝑦 and negative stage number 𝑥 select their maximum values (𝑦 = 𝑥 − 1, 𝑥 = 𝑁).

𝑅𝑚𝑖𝑛 = 𝑟𝑆−𝑚𝑖𝑛𝑟𝑇 =𝑁 + 1

𝑁 − 1𝑟𝑇 (3.39)

𝑅𝑚𝑎𝑥 = 𝑟𝑆−𝑚𝑎𝑥𝑟𝑇 = (2𝑁 − 1)𝑟𝑇 (3.40)

Since the positive stage number 𝑦 and negative stage number 𝑥 can be flexibly chosen from

their minimum to maximum values (1 ≤ 𝑦 ≤ 𝑥 − 1, 𝑦 + 1 ≤ 𝑥 ≤ 𝑁) in the modulation, it

could provide 𝑁(𝑁 − 1)/2 combinations to satisfy various high step-ratio application cases

and gives a large degree of flexibility for the converter in the operation process.

Figure 3.11. Step-ratio range of the basic high step-ratio RMMC (𝑁 ≤ 10 and 𝑟𝑇 = 1).

Step

-rat

io V

alue

s (R)

Positive Stage SM Number (y)

Negati

ve Stag

e SM N

umbe

r

(x = 10

)

x = 2

x = 3

x = 4

x = 5

x = 8

x = 7

x = 6

x = 9


Figure 3.12. Step-ratio range of the basic high step-ratio RMMC (𝑁 ≤ 10 and 𝑟𝑇 = 5).

The overall step-ratio values when 𝑁 ≤ 10 for the case of 𝑟𝑇 = 1 and 𝑟𝑇 = 5 are plotted in

Figure 3.11 and Figure 3.12 respectively as two illustration examples to show the wide step-

ratio ranges of this RMMC. It can be seen that there are 45 different step-ratio choices available

for this RMMC, and the step-ratio value gap between different y-x combinations could be

bridged by adjusting the switching frequency and effective frequency [91], [99].

3.3.3 Inherent Voltage-balancing Capability

For the analysis of inherent voltage-balancing capability, the relationships of the SM capacitor

voltages in general operation can be expressed in (3.41).

[𝐀𝒙,𝒚 𝟏𝒙×𝟏

𝟏𝟏×𝒙 −1] ∙ [

𝒗𝑪𝒊


𝟏𝒙×𝟏

1] ∙ 𝑣𝐻𝑆 (3.41)

with 𝒗𝑪𝒊 =

[ 𝑣𝐶1

𝑣𝐶2 𝑣𝐶3

⋮𝑣𝐶𝑥 ]

.

As long as the value of 𝑦 and 𝑥 are mutually prime, the operation matrix of 𝐀𝒙,𝒚 will have the

full rank and all the SM capacitor voltages (𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶𝑥) are linearly independent

Step

-rat

io V

alue

s (R)

Positive Stage SM Number (y)

Negati

ve Stag

e SM N

umbe

r

(x = 10

)

x = 2

x = 3

x = 4

x = 5

x = 8

x = 7

x = 6

x = 9


in the equation. This is named as the “prime” discipline, and in this condition, each SM

capacitor voltage adopts the expression in (3.42) and the converter has the voltage inherent-

balancing capability.

𝑣𝐶1 = 𝑣𝐶2 = 𝑣𝐶3 = ⋯ = 𝑣𝐶𝑁 = 𝑣𝐶 =2𝑣𝐻𝑆

𝑥 + 𝑦 (3.42)

For example, the operation matrix 𝐀𝟓,𝟒 in (3.7), 𝐀𝟓,𝟑 in (3.9), 𝐀𝟒,𝟑 in (3.11) and (3.12) are all

full rank because the values of 𝑦 and 𝑥 are all mutually prime in these operational cases. So,

their SM capacitor voltages are all linearly independent in the equation, and each SM capacitor

voltage adopts the generalized expression in (3.42). However, if the positive stage number 𝑦

and negative stage number 𝑥 have common divisor, for example they are set with 2 and 4

respectively, the voltage relationship in each 2π cycle is described as (3.43).

[𝐀𝟒,𝟐 𝟏𝟒×𝟏

𝟏𝟏×𝟒 −1] ∙ [

𝒗𝑪𝒊


𝟏𝟒×𝟏

1] ∙ 𝑣𝐻𝑆 (3.43)

with 𝐀𝟒,𝟐 = [

0 0 1 11 0 0 11 1 0 00 1 1 0

] ,𝒗𝑪𝒊𝟏 = [

𝑣𝐶1

𝑣𝐶2 𝑣𝐶3

𝑣𝐶4

].

The solution of (3.43) is not unique since the operation matrix 𝐀𝟒,𝟐 is rank deficient. There is

at least one SM capacitor voltage becoming linearly dependent in the equation. As a result, a

complete inherent balancing is not guaranteed and this situation should be avoided in the

operation.

The inherent balancing analysis for all the possible combinations when 𝑁 ≤ 10 is shown in

Figure 3.13. It can be seen that, under all the conditions of 𝑦 = 𝑥 − 1, the converter always has

the inherent voltage-balancing capability since 𝑦 and 𝑥 do not have any common divisor and

the relevant operation matrix 𝐀𝒙,𝒚 has full rank. In other words, the SM capacitor voltages will

be always self-balanced in the highest step-ratio conversion. Also, if the value of 𝑥 is a prime

number, the inherent balancing capability will exist in the converter regardless the value of 𝑦,


and so a prime number of 𝑥 is highly recommended in the converter design and modulation

process.

Figure 3.13. Analysis of inherent voltage-balancing capability (𝑁 ≤ 10).

3.3.4 DC Fault Management

Providing effective dc fault management would be desirable for dc-dc converters especially

when they interconnect two sub-systems with different voltage levels [72], [92], [201]. This

high step-ratio RMMC has this advantage because it can make use of the intermediate ac stage

to prevent the short circuit fault propagating from one side to the other side.

A fault on the high-voltage side will ground the primary stacks but the secondary-side active

rectifier can prevent flow of fault current from the low-voltage side to the fault. In the case of

a fault on the low-voltage side, the primary stack remains in full control of the currents as they

have sufficient SM voltage to withstand the high-side terminal voltage.

This dc-ac-dc conversion itself provides a good dc fault management without any extra

protection equipment.

Posi

tive

Sta

ge S

M N

umbe

r (y)

Negative Stage SM Number (x)


3.3.5 Challenges and Limitations

Based on the analysis in (3.42), the maximum voltage stress on upper switch and lower switch

of each SM of this high step-ratio RMMC is given in (3.44), and the voltage stress on

secondary-side rectifiers is rewritten in (3.45) from (3.21).

𝑣𝑢𝑝𝑛−𝑚𝑎𝑥 = 𝑣𝑙𝑜𝑤𝑛−𝑚𝑎𝑥 =2𝑣𝐻𝑆

𝑥 + 𝑦, (𝑛 = 1, 2,⋯𝑁) (3.44)

𝑣𝑆1−𝑚𝑎𝑥 = 𝑣𝑆2−𝑚𝑎𝑥 = 𝑣𝑆3−𝑚𝑎𝑥 = 𝑣𝑆4−𝑚𝑎𝑥 =𝑣𝐻𝑆

𝑅=

(𝑥 − 𝑦)𝑣𝐻𝑆

(𝑥 + 𝑦)𝑟𝑇 (3.45)

From (3.17) and (3.19), the current stress on SM switches equals the maximum value of stack

current and the expression is given in (3.46). The maximum current stress on rectifiers is

rewritten in (3.47) from (3.22).

𝑖𝑢𝑝𝑛−𝑚𝑎𝑥 = 𝑖𝑙𝑜𝑤𝑛−𝑚𝑎𝑥 =2𝑟𝑇 + 𝜋𝑅

2𝑟𝑇𝑖𝐻𝑆, (𝑛 = 1, 2,⋯𝑁) (3.46)

𝑖𝑆1−𝑚𝑎𝑥 = 𝑖𝑆2−𝑚𝑎𝑥 = 𝑖𝑆3−𝑚𝑎𝑥 = 𝑖𝑆4−𝑚𝑎𝑥 =𝜋𝑅

2𝑖𝐻𝑆 (3.47)

When the high-side terminal voltage increases, the voltage stress for this high step-ratio

RMMC would need more SM number in the stack to support the sum of dc terminal voltage

and transformer primary-side voltage, which would increase the design complexity for the

phase-shift modulation, especially the tiny value for the phase-shift angle between a large

number of SMs and the short period time for each negative pulse in each SM. In the meantime,

the choice for effective frequency would be challenging since the difference between positive

stage resonant frequency and negative stage resonant frequency becomes large when the SM

total number keeps increasing.

If the current rating increases, it may cause more serious difficulties for this basic RMMC.

From (3.47), the basic full-bridge rectifiers have to carry all the current on the secondary-side

circuit and the single switch arrangement would face challenges when current rating

3.4 Variety of Configurations 71

requirement keep rising. Also, these rectifiers need to pass through the current with the short

and fast cycle effective cycle 𝑇𝑒 rather than the longer and slower switching cycle 𝑇𝑠 which the

SM switches on the primary side go through with.

Combining these two factors, the most challenging aspects for the power rating expansion of

this RMMC would be the current stress on secondary-side single rectifiers and the total number

limitation on primary-side SMs. The internal transformer with higher turns-ratio could provide

solution to interconnect lower low-side terminal voltage, but it cannot address the restrictions

on high-side voltage rating and low-side current rating. As a result, this basic high step-ratio

RMMC is more suitable to serve as a high step-ratio but small power rating interface between

MVDC and LVDC distribution networks. For higher power rating and higher step-ratio

(connecting lower 𝑣𝐿𝑆 is not considered here) conversion, it faces technical difficulties.

3.4 Variety of Configurations

Fortunately, though, this basic high step-ratio RMMC can lend itself to be the starting point

and building block for further configurations. The extended topologies are proposed and

discussed in this section to overcome the inherent challenges in single circuit operation and

accomplish the higher power rating and higher step-ratio conversion.

3.4.1 Bipolar and Monopolar Configurations

Firstly, by combining two basic high step-ratio RMMC stacks into positive and negative poles

and inserting one medium frequency transformer between the high-voltage side and low-

voltage side, the bipolar configuration is derived in Figure 3.14. The high-voltage side has been

developed as a typical single-phase MMC but operated in resonant mode as described in

Section 3.2, and the low-voltage side rectifiers are still formed of IGBTs for bidirectional

power flow. The SM switches are modulated in the same way as the single RMMC operation,

but the top stack and bottom stack need to keep a phase shift value of half effective cycle (𝜋/𝑥,

𝑥 is the SM number in the negative stage). The modulation difficulty and the effective

frequency for each stack stay the same, but the high-side voltage rating and overall step-ratio

are both doubled. The expression of the generalized step-ratio of this bipolar high step-ratio


RMMC is given in (3.48), and all the SM capacitor adopt the voltage in (3.49). However, it

needs to note that the current amplitude on the secondary-side rectifiers in this bipolar

configuration is increased to twice of that in basic RMMC, so the power rating of this converter

would not be extended a lot in practical applications.

𝑅 =𝑣𝐻𝑆

𝑣𝐿𝑆=

2(𝑥 + 𝑦)

𝑥 − 𝑦𝑟𝑇 (3.48)

𝑣𝐶𝑇𝑛 = 𝑣𝐶𝐵𝑛 =𝑣𝐻𝑆

𝑥 + 𝑦, (𝑛 = 1, 2,⋯𝑁) (3.49)

Secondly, if the top stack and bottom stack work in the same switching sequence, the primary

winding of the transformer can be inserted between the two stacks, forming the monopolar

configuration, shown in Figure 3.15. The dc terminal voltage at both side will be doubled of

that in basic RMMC while the current amplitude and frequency could keep the same condition

as those in basic RMMC. In this manner, the power rating will be increased to twice of the

basic RMMC but the step-ratio is the same.

Figure 3.14. Bipolar configuration of the basic high step-ratio RMMC.

N1

CHS+

CHS-

iST

iSTT iSTB

iHS

vHS

Top Stack

Bottom Stack

SMT2

SMT1

SMT4

SMT3

SMTN

SMB2

SMB1

SMB4

SMB3

SMBN

N2

S1 S3

S2 S4

CLSvS

iS

iLS

vLS

Lm

LrT

LrB


Figure 3.15. Monopolar configuration of the basic high step-ratio RMMC.

It can be seen that the bipolar and monopolar configurations could extend either step-ratio or

power rating to some extent without increasing the difficulties for stack modulation design and

effective frequency choice, but they are still strictly constrained due to the current stress

limitation on the secondary-side rectifiers.

3.4.2 Modular Configurations

Thanks to the internal transformer isolation in the circuit, the concept of multi-module

configuration can be also applied to the basic high step-ratio RMMC as the classic modular

DAB or LLC converter, and the difficulties and limitations for step-ratio and power rating in

single circuit operation could be overcome. The basic high step-ratio RMMC serves as the

module circuit and the total number of the module circuit is scalable for various conversion

requirement, as shown in Figure 3.16. To decrease the requirements of dc capacitance for both

terminals, two module circuits for a pair are placed in parallel with the second module phase-

shifted by 𝜋/𝑥 with respect to the first to offset the resonant current ripple imposed in the

LrT

LrB

CHS

Top Stack

Bottom Stack

N1

L m

iSTT

iSTB

iHS

vHS

SMT2

SMT1

SMT4

SMT3

SMTN

N2

S1 S3

S2 S4

CLS

vS

iS

iLS

vLS

SMB2

SMB1

SMB4

SMB3

SMBN


capacitors of the high-voltage dc terminal, and the switching frequency of each module circuit

is adjustable to balance the current within one pair. Then, the various pairs are placed in series

and have a phase-shift angle of 𝜋/𝑥𝑁𝑃 (𝑁𝑃 is the total pair number of the module circuits) with

respect to the previous pair in order to alleviate the filtering demand on the low-voltage side.

Since all the modules are operated in the same way as in the single circuit RMMC, the operation

benefits stated before will all remain in this multi-module configuration.

Figure 3.16. Multi-module configuration of the basic high step-ratio RMMC.

The high-side voltage rating of this multi-module configuration can be developed to 𝑁𝑃 times

of that in the basic high step-ratio RMMC, and the overall voltage step-ratio between high-side

terminal and low-side terminal is given in (3.50). The maximum voltage and current stress on

the each SM switches are described as (3.51) and (3.52), and the stress on each rectifier is

expressed in (3.53) and (3.54). The total pair number of the module circuits can be flexibly

configured to meet various conversion specification requirements, and the voltage/current

CLS11

CLS12

CLSNp1CHSNp

CLSNp2

iHS11

iHS12

iHSNp1

iHSNp2

iLS11

iLS12

iLSNp1

iLSNp2

iST11

iST12

iSTNp1

iSTNp2

T12

vS12

TNp1

vSNp1

TNp2

vSNp2

CHS1

Pair 1

Pair Np

T11

vS11

iHSvHS

iLSvLS

SMN

p21

SMN

p22

SMN

p23

SMN

p24

SMN

p2N

SMN

p11

SMN

p12

SMN

p13

SMN

p14

SMN

p1N

SM12

1

SM12

2

SM12

3

SM12

4

SM12

N

SM11

1

SM11

2

SM11

3

SM11

4

SM11

N


limitation on single power device would be no longer the obstacle to realise the large step-ratio

and large power rating interconnection between MVDC and LVDC distribution networks.

𝑅 =𝑣𝐻𝑆

𝑣𝐿𝑆=

𝑥 + 𝑦

𝑥 − 𝑦𝑟𝑇𝑁𝑝 (3.50)

𝑣𝑢𝑝−𝑚𝑎𝑥 = 𝑣𝑙𝑜𝑤−𝑚𝑎𝑥 =2𝑣𝐻𝑆

(𝑥 + 𝑦)𝑁𝑝 (3.51)

𝑖𝑢𝑝−𝑚𝑎𝑥 = 𝑖𝑙𝑜𝑤−𝑚𝑎𝑥 =(2𝑟𝑇𝑁𝑝 + 𝜋𝑅)𝑖𝐻𝑆

4𝑟𝑇𝑁𝑝 (3.52)

𝑣𝑆1−𝑚𝑎𝑥 = 𝑣𝑆2−𝑚𝑎𝑥 = 𝑣𝑆3−𝑚𝑎𝑥 = 𝑣𝑆4−𝑚𝑎𝑥 =(𝑥 − 𝑦)𝑣𝐻𝑆

(𝑥 + 𝑦)𝑟𝑇𝑁𝑝 (3.53)

𝑖𝑆1−𝑚𝑎𝑥 = 𝑖𝑆2−𝑚𝑎𝑥 = 𝑖𝑆3−𝑚𝑎𝑥 = 𝑖𝑆4−𝑚𝑎𝑥 =𝜋𝑅𝑖𝐻𝑆

4𝑁𝑝 (3.54)

On the down side, the multi-module arrangement of dc-dc circuits would always bring about

insulation challenge and reliability concern for the module transformers and these difficulties

are common issues for all of the similar input-series-output-parallel topologies for medium

voltage or high voltage applications. The multi-module configuration of this high step-ratio

RMMC could alleviate these difficulties and has some benefits over the traditional modular

DAB or LLC converter in this aspect.

On the one hand, because the SM stack itself could contribute a significant part for voltage

conversion, the required module transformer number in Figure 3.16 is much less than that

needed in modular DAB or LLC circuits for the same overall step-ratio conversion. It would

increase the system reliability because it decreases the system failure rate caused by the

breakdown of any single module transformer. In the meantime, the maximum insulation

voltage between the transformer primary side and secondary side in modular DAB or LLC

converter has to be the difference between high-side terminal voltage 𝑣𝐻𝑆 and low-side

terminal voltage 𝑣𝐿𝑆 [92], [121], but the maximum transformer insulation voltage in Figure

3.16 would be smaller than the difference between 𝑣𝐻𝑆 and 𝑣𝐿𝑆.


On the other hand, the transformer position in the Figure 3.16 is adjustable to reduce the

insulation requirement between module circuit transformers. In a four-module configuration

example shown in Figure 3.17, the SM stack in the first pair is placed before its module

transformer but the second pair is placed after. The operating principle remains the same as

Figure 3.16 but the transformer insulation voltage between the first pair and second pair is

reduced.

Figure 3.17. Four-module example of the enhanced multi-module configurations for module

transformer insulation.

Similarly, the bipolar and monopolar high step-ratio RMMC can also serve as the building

block and module circuit for multi-module configuration, and the multi-module design of the

bipolar and monopolar RMMC are shown in Figure 3.18 and Figure 3.19 respectively. The

module circuits are placed in series on the high-voltage side and in parallel on the low voltage-

side. For each module circuit, there is also a phase-shift value of 𝜋/𝑥𝑁𝑚 (𝑁𝑚 is the total

CLS11

CLS12

CLS21CHS2

CLS22

iHS11

iHS12

iHS21

iHS22

iLS11

iLS12

iLS21

iLS22

iST11

iST12

iST21

iST22

T12

vS12

T21

vS21

T22

vS22

CHS1

Pair 1

Pair 2

T11

vS11

iHSvHS

iLSvLS

SM11

1

SM11

2

SM11

3

SM11

4

SM11

N

SM12

1

SM12

2

SM12

3

SM12

4

SM12

N

SM211

SM212

SM213

SM214

SM21N

SM221

SM222

SM223

SM224

SM22N


number of the module circuits) with respect to the previous module in order to mitigate the

current ripple on the low-voltage side. Further, the primary-side circuits of Figure 3.18 and

Figure 3.19 can be developed to a full-bridge arrangement to double the power rating

(secondary-side power device limitation is not considered here) and remove the requirement

for high-side dc link capacitors, as shown in Figure 3.20. In each full-bridge high step-ratio

RMMC module, the SMs in stack 1 and stack 4 are operated in the same switching sequence

and constitute one resonant loop, while stack 2 and stack 3 resonate in another loop with the

opposite current direction. Thus, the resonant currents sum at the module transformer and

cancel at the high-side dc terminal, which increases the power rating twice compared to the

bipolar or monopolar RMMC and also removes all the dc link capacitors on high-voltage side.

The phase-shift scheme between different modules keeps the same as that in multi-module

bipolar or monopolar RMMC in order to reduce the capacitance on the low-voltage side.

Figure 3.18. Multi-module configuration of the bipolar high step-ratio RMMC.

N11

CHS1+

CHS1-

iST1

iST1T

iST1B

Top Stack

Bottom Stack

SM1T2

SM1T1

SM1T4

SM1T3

SM1TN

SM1B2

SM1B1

SM1B4

SM1B3

SM1BN

N12 vS1

iLS1

CLS1

iHS

vHS

vLS

Bipolar RMMC Module 1

Bipolar RMMC Module 2

Bipolar RMMC Module Nm

iLS


Figure 3.19. Multi-module configuration of the monopolar high step-ratio RMMC.

Monopolar RMMC Module 2

Monopolar RMMC Module Nm

Monopolar RMMC Module 1

vLS

vHS

iLS

CHS1

Top Stack

Bottom Stack

N11

iST1T

iST1B

iHS

SM1T2

SM1T1

SM1T4

SM1T3

SM1TN

N21

CLS1

vS1

iLS1

SM1B2

SM1B1

SM1B4

SM1B3

SM1BN

3.5 Derivative Topologies 79

Figure 3.20. Multi-module configuration of the full-bridge high step-ratio RMMC.

3.5 Derivative Topologies

The basic high-step ratio RMMC is derived from the classic isolated LLC circuit with an MMC-

like stack replacing the original single-switch half-bridge or full-bridge configuration, shown

in Figure 3.21.

Figure 3.21. LLC-based RMMC.

N11 iST1

iST13

iST14

Stack 13

SM132

SM131

SM134

SM133

SM13N

SM142

SM141

SM144

SM143

SM14N

N12 vS1

iLS1

CLS1

iHS

vHS

vLS

Full-bridge RMMC Module 1

Full-bridge RMMC Module 2

Full-bridge RMMC Module Nm

iLS

iST11

iST12

SM112

SM111

SM114

SM113

SM11N

SM122

SM121

SM124

SM123

SM12N

Stack 11

Stack 14

Stack 12

Lr

Lm

SM1

SMN

N2N1 CLS vLSvHS CHS

Lr

Lm N2N1 CLS vLSvHS CHS

Cr


Actually, this derivation methodology is not just limited to the LLC resonant circuit. It can be

generalized and applied to other classic dc-dc circuits for medium voltage level high step-ratio

conversion. The application examples for buck-based RMMC, buck-boost-based RMMC and

flyback-based RMMC are shown in Figure 3.22–Figure 3.24 respectively.

Figure 3.22. Buck-based RMMC.

Figure 3.23. Buck-Boost-based RMMC.

Figure 3.24. Flyback-based RMMC.

The operating principle and modulation scheme of these derivative high step-ratio RMMCs are

similar to the LLC-based basic high step-ratio RMMC described in Section 3.2. By switching

either 𝑦 or 𝑥 SM capacitors into the stack for equal durations, a symmetrical square-wave

vLS

Lm vHS CHS

CLS

SM1

SMN

Lr

vLS

Lm vHS CHS

CLS

Lm

vHS CHS

vLSCLS

SM1

SMN

Lr

+

vHS CHS

vLSCLS +

vLSCLS

vHS CHS

vLSCLS

vHS CHS

SM1

SMN

Lr

3.6 Medium Voltage Application Examples 81

voltage can be generated in the circuit and excites a resonance between SM capacitors and

resonant inductor 𝐿𝑟 to assist all the SM switches achieve soft-switching operation. As long as

the value of 𝑦 and 𝑥 are mutually prime in the phase-shift modulation, each SM capacitor

voltage will be inherently balanced in the operation. The stack rating requirement could be also

small for these derivative RMMCs because the effective frequency for the stack is higher than

the switching frequency for the individual SM. The current stress on secondary-side rectifiers

and the total number limitation on primary-side SMs would be also the most challenging issues

for these circuits to expand their power limitation, but these circuits could also have variety of

further configurations to alleviate or overcome this difficulty.

3.6 Medium Voltage Application Examples

To verify the theoretical analysis in this chapter, this section conducts a set of medium voltage

level full-scale simulations and also explores some practical application examples. The

transformer turns-ratio of all the example converters in this section has been set as 𝑟𝑇 = 1 in

order to clearly and fully demonstrate the flexibility and capability of SM stack in high step-

ratio voltage conversion.

3.6.1 Simulation Results for Single Circuit

Recognizing the voltage and current limits of up-to-date power devices, the basic RMMC in

Figure 3.1 is suitable to accomplish a high step-ratio (4 ≤ 𝑅 ≤ 9) but small power rating

( 0.7 MW ≤ 𝑃𝑇 ≤ 1 MW ) conversion between MVDC and LVDC distribution networks.

Redrawing the multi-voltage network of Figure 1.12 for illustration in Figure 3.25, the basic

RMMC can serve as the bidirectional interface to realise the power connection between an

MVDC link and a small LVDC distributed microgrid, shown as the pink box in the right side

of Figure 3.25.


Figure 3.25. Multi-voltage dc network with MVDC and LVDC infrastructures.

Table 3.1. Simulation parameters of the basic high step-ratio RMMC for application examples

Symbol Description Value

𝑃𝑇 Power Throughput 0.7 MW–1.0 MW

𝑣𝐻𝑆 High-side Terminal Voltage 10 kV

𝑣𝐿𝑆 Low-side Terminal Voltage 1.1 kV–2.5 kV

𝐿𝑚 Magnetizing Inductance 0.98 mH

𝑟𝑇 Transformer Turns-ratio 1:1

𝐿𝑟 Resonant Inductance 15.6 µH

𝑁 SM Number 5

𝐶𝑘 SM Capacitance (𝑘 = 1,2, … ,5) 950 µF with ±10% variation

𝛾 Maximum Ripple for SM Capacitor Voltage 10%

𝑓𝑠 Switching Frequency 500 Hz–1000 Hz

𝐸𝑆𝑇 Normalised Stack Capacitive Energy Storage 11.5 kJ/MVA

𝑆

Power Switches Selected Type ABB 5SNA1500E330305

Power Switches Rated Voltage 3300 V

Power Switches Rated Current 1500 A

𝑆𝑆𝑇 Normalised Semiconductor Volt-ampere Rating 69.3

PV Wind Battery

ModernBallast

Digital Motor Lighting

Large Step-upLarge Power Rating

DC-DC


PV Battery

HVAC Transmission

HVDC Transmission

Large LVDC Distributed Generation Small LVDC Distributed Microgrid

High Step-RatioSmall Power Rating

DC-DC

Large LVDC Load Distribution

Multi-voltage DC Network with MVDC and LVDC Infrastructures

ModernBallast

Digital Lighting

EV

≈10 kV

≈1kV ≈1kV

≈1kV

>10 kV <20 kV

Large Step-downLarge Power Rating

DC-DC


The detailed parameters of an example converter with 5 SMs configuration are listed in Table

3.1. The SM capacitances used in the simulation were deliberately given a ± 10% variation

from the nominal capacitance to reflect manufacturing tolerances. Based on the analysis in

(3.14) and (3.28), it can be found this converter has implemented a relatively low-cost and

highly-compact SM stack design, in which the normalised semiconductor volt-ampere rating

𝑆𝑆𝑇 is 69.3 (including both SM stack and rectifiers) and the stack capacitive energy storage

𝐸𝑆𝑇 is 11.5 kJ/MVA.

Firstly, the simulation results for the highest step-ratio conversion with 𝑦 = 4 and 𝑥 = 𝑁 = 5

are demonstrated in Figure 3.26. From the circuit parameters in Table 3.1, the positive and

negative resonant frequency are approximately 2.6 kHz and 2.9 kHz respectively, so, for the

resonance performance and conversion efficiency, the switching frequency is chosen as 550

Hz and effective frequency is 2.75 kHz (𝑇𝑠 = 5𝑇𝑒 = 2π). Figure 3.26 (a) and Figure 3.26 (b)

shows that the capacitor of SM1 is inserted into the stack for 90% period of a 2π cycle before

being bypassed for the remaining 10% period, which is one of the five individual positive

stages in a 2π cycle. The SM capacitors participate in the resonance with 𝐿𝑟 and thus assist all

the SM switches achieve the soft-switching operation. In Figure 3.26 (c), all the SM capacitor

voltages are inherently well-balanced at round 2.2 kV without any extra voltage adjustment,

and the phase-shift angle between the adjacent ones is 0.4π as expected. Lastly, it can be seen

from Figure 3.26 (d) that the transformer voltage on the secondary side 𝑣𝑆 is ± 1.11 kV and so

the step-ratio value in this case is 9:1. The amplitude of the stack current is about 1050 A, and

it verifies the theoretical analysis in (3.17) and demonstrates the power throughput for this

conversion case is 0.7 MW.

(a)


(b)

(c)

(d)


RMMC (𝑅 = 9: 1, 𝑃𝑇 = 0.7 MW). (a) Voltage and current of the upper switch in SM1, 𝑣𝑢𝑝 and 𝑖𝑢𝑝. (b)

Voltage and current of the lower switch in SM1, 𝑣𝑙𝑜𝑤 and 𝑖𝑙𝑜𝑤. (c) SM capacitor voltages 𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3,

𝑣𝐶4, 𝑣𝐶5. (d) Transformer voltage on the secondary side 𝑣𝑆 and stack current 𝑖𝑆𝑇.


Results for reverse power flow (low-side to high-side) are shown in Figure 3.27. Operation is

seen to be essentially the same as in Figure 3.26, with the same voltage values and resonant

frequencies but the current directions have been all reversed. It is worth noting that the SM

capacitor voltage waveform in Figure 3.27 (c) is similar to that in Figure 3.26 (c), but it can be

seen in detail that the voltage trends of each SM capacitor are actually in the opposite sense

due to the change of the current flow.

(a)

(b)

(c)


(d)


RMMC in reverse power flow (𝑅 = 9: 1, 𝑃𝑇 = −0.7 MW). (a) Voltage and current of the upper switch

in SM1, 𝑣𝑢𝑝 and 𝑖𝑢𝑝 . (b) Voltage and current of the lower switch in SM1, 𝑣𝑙𝑜𝑤 and 𝑖𝑙𝑜𝑤 . (c) SM

capacitor voltages 𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (d) Transformer voltage on the secondary side 𝑣𝑆 and stack

current 𝑖𝑆𝑇.

Then, the simulation results for 𝑦 = 3 and 𝑥 = 𝑁 = 5 are given in Figure 3.28 to show the

modulation flexibility in positive stage. The positive resonant frequency is decreased to about

2.3 kHz in this case, so the effective frequency of the square wave voltage is adjusted to 2.6

kHz in the operation (2𝑇𝑠 = 5𝑇𝑒 = 2π). It can be seen in Figure 3.28 (a) and Figure 3.28 (b)

that there are two SMs modulated out of the stack for each positive stage and each SM is

bypassed for two positive stages in each 2π cycle. The phase-shift value between the adjacent

SMs still keeps the value of 0.4π, but the SM duty-cycle has been decreased to 80%. All the

SM capacitor voltages are self-balanced at about 2.5 kV as expected, shown in Figure 3.28 (c).

From Figure 3.28 (d), the transformer secondary-side voltage is ± 2.5 kV and so the step-ratio

in this conversion is 4:1. The amplitude of the stack current is about 500 A, which still reaches

good agreement with the result of (3.17), and the power throughput in this case is also 0.7 MW.

Lastly, the SM number in the negative stage is further adjusted to 4 (𝑦 = 3, 𝑥 = 4 and 𝑁 = 5)

to demonstrate the flexible modulation in negative stage, and the simulation results are shown

in Figure 3.29. Since there are only 4 active SMs resonating with 𝐿𝑟 in a 2π cycle (𝑇𝑠 = 4𝑇𝑒 =

2π), the switching frequency is set at 600 Hz to match the range of resonant frequencies. In

Figure 3.29 (a), SM1 is operated as an active SM in this 2π cycle and participates in the

resonance. It is inserted into the stack for a duty-cycle of 87.5% and removed from the stack


for 12.5%. All these five SMs take turns to be the redundant SM, which is bypassed in the

whole specific 2π cycle and the capacitor voltage keeps a constant value. It can be observed

from Figure 3.29 (b) that SM4 (purple line) is operated as the redundant SM in the whole first

2π cycle and SM5 (green line) replaces it when time goes to 1.7 ms. From Figure 3.29 (a) and

Figure 3.29 (b), the soft-switching and inherent balancing are still achieved, and the amplitude

of 𝑣𝑆 and 𝑖𝑆𝑇 are adjusted to 1.43 kV and 830 A, shown in Figure 3.29 (c), which further verifies

the theoretical analysis in (3.3) and (3.17).

(a)

(b)

(c)


(d)


RMMC (𝑅 = 4: 1, 𝑃𝑇 = 0.7 MW). (a) Voltage and current of the upper switch in SM1, 𝑣𝑢𝑝1 and 𝑖𝑢𝑝1.

(b) Voltage and current of the upper switch in SM2, 𝑣𝑢𝑝2 and 𝑖𝑢𝑝2. (b) SM capacitor voltages 𝑣𝐶1, 𝑣𝐶2,

𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (c) Transformer voltage on the secondary side 𝑣𝑆 and stack current 𝑖𝑆𝑇.

(a)

(b)


(c)


RMMC (𝑅 = 7: 1, 𝑃𝑇 = 0.7 MW). (a) Voltage and current of the upper switch in SM1, 𝑣𝑢𝑝 and 𝑖𝑢𝑝. (b)

SM capacitor voltages 𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (c) Transformer voltage on the secondary side 𝑣𝑆 and

stack current 𝑖𝑆𝑇.

In addition to the operational model, a power losses estimate model [99], [201] based on IEC

61803 and IEC 62751 [202] was also built using manufacturer’s data for the chosen device

ABB 5SNA1500E330305 for both SMs and rectifiers. Each constituent of the power device

losses in the highest step-ratio conversion case (𝑅 = 9: 1, 𝑃𝑇 = 0.7 MW) is shown in Table 3.2.

Table 3.2. Power device losses analysis for the highest step-ratio conversion case

Constituents of Power Losses Value

SM Stack IGBT Conduction 6.377 kW

SM Stack IGBT Switching 1.545 kW

Rectifier IGBT Conduction 2.297 kW

Rectifier IGBT Switching 0.243 kW

Total Losses 10.462 kW

Percentage of Power Throughput 1.48%

The SM IGBT conduction loss is the largest constituent as expected, and its switching loss is

relatively low due to the soft-switching turn-on benefit. The rectifier IGBT losses is relatively

small because the current goes through its ant-parallel diode and it achieves both soft-switching


turn-on and switching turn-off operation. The overall losses of the power devices are 10.462

kW, which accounts for about 1.48% of the 0.7 MW power throughput. Considering the high

step-ratio conversion in the SM stack and an explicit ac stage in the conversion process, this

power loss percentage is a competitive result for the interconnection between an MVDC link

and an LVDC microgrid [59], [72], [146].

3.6.2 Simulation Results for Further Configurations

The maximum step-ratio of this basic RMMC is 9:1, and its high-side voltage rating is 10 kV

and its power rating limitation is about 1 MW with the safety margin for the selected power

devices in Table 3.1. To extend the maximum step-ratio, voltage rating and power rating, the

bipolar, monopolar and multi-module configurations of this basic RMMC are further explored

in this section.

Simulation for the bipolar configuration (see Figure 3.14) with 𝑦 = 4 and 𝑥 = 5 is provided in

Figure 3.30, in which the high-side voltage rating has been increased to 20 kV. Figure 3.30 (a)

and Figure 3.30 (b) confirm that the SM in top stack and bottom stack are operated with the

same duty-cycle but phase-shifted by 0.2π. All the SM capacitor voltages are still self-balanced

at about 2.2 kV, shown in Figure 3.30 (c) and Figure 3.30 (d). It can be derived from Figure

3.30 (e) and Figure 3.30 (f) that the overall step-ratio has been extended to 18:1, but the power

limitation is still constrained at about 1.0 MW due to the current amplitude limitation on the

secondary-side power switches.

(a)


(b)

(c)

(d)

(e)


(f)

Figure 3.30. Simulation results for the bipolar configuration (𝑅 = 18: 1, 𝑃𝑇 = 1.0 MW). (a) Voltage

and current of the upper switch in SMT1, 𝑣𝑢𝑝𝑇1 and 𝑖𝑢𝑝𝑇1. (b) Voltage and current of the upper switch

in SMB1, 𝑣𝑢𝑝𝐵1 and 𝑖𝑢𝑝𝐵1. (c) SM capacitor voltages of top stack 𝑣𝐶𝑇1, 𝑣𝐶𝑇2, 𝑣𝐶𝑇3, 𝑣𝐶𝑇4, 𝑣𝐶𝑇5. (d) SM

capacitor voltages of bottom stack 𝑣𝐶𝐵1, 𝑣𝐶𝐵2, 𝑣𝐶𝐵3, 𝑣𝐶𝐵4, 𝑣𝐶𝐵5. (e) Top stack current and bottom stack

current, 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵. (f) Transformer voltage on the secondary side 𝑣𝑆 and the sum of stack current

𝑖𝑆𝑇.

The results for the monopolar configuration (see Figure 3.15) are similar, and they are given in

Figure 3.31, in which the high-side voltage rating has been also developed to 20 kV. The top

stack and bottom stack are operated in the same switching sequence without phase shift, so the

SM waveforms are almost identical for the two stacks, shown in Figure 3.31 (a) and Figure

3.31 (b). From Figure 3.31 (c), the SM voltages are also inherently balanced at 2.2 kV without

extra adjustment. In Figure 3.31 (d), the power rating could be increased to about 2 MW with

the same power devices selected in Table 3.1, but the maximum step-ratio of this configuration

is the same as the basic RMMC.

(a)


(b)

(c)

(d)

Figure 3.31. Simulation results for the monopolar configuration (𝑅 = 9: 1, 𝑃𝑇 = 2.0 MW). (a) Voltage

and current of the upper switch in SM1T or SM1B, 𝑣𝑢𝑝 and 𝑖𝑢𝑝. (b) Voltage and current of the lower

switch in SM1T or SM1B, 𝑣𝑙𝑜𝑤 and 𝑖𝑙𝑜𝑤. (c) SM capacitor voltages of top stack or bottom stack 𝑣𝐶1, 𝑣𝐶2,

𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (d) Transformer voltage on the secondary side 𝑣𝑆 and stack current 𝑖𝑆𝑇𝑇(𝑖𝑆𝑇𝐵).


To satisfy the large step-ratio (𝑅 ≈ 20) and large power rating (𝑃𝑇 ≈ 3 MW) conversion to

interconnect an MVDC link with a large LVDC generation network or distribution network, as

shown the pink boxes in the left side of Figure 3.25, the multi-module configuration with four-

module design (see Figure 3.16) is applied here and its simulation results are demonstrated in

Figure 3.32. The SM capacitance and resonant inductance in each module circuit are set with

10% variation for manufacture tolerance. The first two modules are paralleled as the first pair

and the last two modules are paralleled as the second pair. Firstly, the current and voltage on

each module are balanced, which can be observed in Figure 3.32 (a)–Figure 3.32 (d). Further,

the phase-shift angle within each pair is 0.2π and it can be found in the individual transformer

waveforms comparing Figure 3.32 (a) and Figure 3.32 (b) or Figure 3.32 (c) and Figure 3.32

(d). It contributes to the neutralization of the resonant current ripple on the high-side link

capacitors and the comparison results are given in Figure 3.32 (e). The switching sequences for

these two pairs have a 0.1π difference, shown in Figure 3.32 (a) and Figure 3.32 (c) or Figure

3.32 (b) and Figure 3.32 (d), and this alleviates the current ripple on the low-voltage side filters,

as illustrated in Figure 3.32 (f). This four-module example is designed for a 2.8 MW dc-dc

conversion from 20 kV to 1.11 kV, and the module number can be flexibly configured

following the analysis in Section 3.4.2 to meet the larger step-ratio and larger power rating

connection between MVDC and LVDC networks.

(a)


(b)

(c)

(d)

(e)


(f)

Figure 3.32. Simulation results for the multi-module configuration (𝑅 = 18: 1, 𝑃𝑇 = 2.8 MW). (a)

Transformer 𝑇11 secondary-side voltage 𝑣𝑆11 and stack current 𝑖𝑆𝑇11. (b) Transformer 𝑇12 secondary-

side voltage 𝑣𝑆12 and stack current 𝑖𝑆𝑇12. (c) Transformer 𝑇21 secondary-side voltage 𝑣𝑆21 and stack

current 𝑖𝑆𝑇21. (d) Transformer 𝑇22 secondary-side voltage 𝑣𝑆22 and stack current 𝑖𝑆𝑇22. (e) Comparison

of the high-side current for one module and high-side current for one pair, 𝑖𝐻𝑆11 and 𝑖𝐻𝑆11 + 𝑖𝐻12. (f)

Comparison of the low-side current for one pair and low-side current for all pairs, 𝑖𝐿𝑆11 + 𝑖𝐿𝑆12 and

𝑖𝐿𝑆11 + 𝑖𝐿𝑆12 + 𝑖𝐿𝑆21 + 𝑖𝐿𝑆22.

3.7 Experiment Results Analysis

To verify the theoretical analysis and simulation results, a down-scaled basic high step-ratio

RMMC prototype (see Figure A.1 in Appendix) was built with the circuit parameters given in

Table 3.3. It chooses digital signal processor TMS320F28335 from Texas Instrument (TI) as

the controller, and it utilises Infineon IGBT modules FF150R12ME3G as the SM power

switches. The volt-ampere ratings of power devices are oversized for safety considerations in

the laboratory, but the stack capacitive energy storage of this prototype is strictly configured

less than 12 kJ/MVA in the full range high step-ratio conversion, which is close to the

theoretical result in Section 3.3.1 and simulation examples in 3.6.1.

3.7 Experiment Results Analysis 97

Table 3.3. Experimental prototype parameters of the basic high step-ratio RMMC


𝑣𝐻𝑆 High-side Terminal Voltage 400 V

𝑣𝐿𝑆 Low-side Terminal Voltage 42 V–100 V



𝐿𝑟 Resonant Inductance 208 µH

𝑁 SM Number 5




3.7.1 Highest Ratio Conversion

Experimental results for the highest step-ratio conversion with 𝑦 = 4 and 𝑥 = 5 are shown in

Figure 3.33 first. The circuit parameters indicate resonant frequencies in the positive stage and

negative stage of 3.2 kHz and 3.6 kHz respectively. The switching frequency is set at 700 Hz

giving an effective frequency of 3.5 kHz (𝑇𝑠 = 5𝑇𝑒 = 2π). Each SM is designed with 90%

duty-cycle and the phase-shift angle between the adjacent ones is 0.4π. Figure 3.33 (a) shows

that zero-crossing of the resonant current is always after the step-change of SM voltage,

meaning that the current flows in the anti-paralleled diodes of the SM switches during each

turn-on operation and soft-switching is thereby achieved. In the meantime, the SM capacitor

voltage is inherently balanced at about 85 V as expected. The transformer voltage in Figure

3.33 (b) is a symmetrical square-wave and the low-side terminal voltage is about 42 V in this

conversion, which confirms the step-ratio is about 9:1 in this case.


(a)

(b)

Figure 3.33. Experimental results for the modulation with 𝑦 = 4 and 𝑥 = 5. (a) SM1 capacitor voltage

𝑣𝐶1, SM1 output voltage 𝑣𝑆𝑀1 and stack current 𝑖𝑆𝑇. (b) Transformer voltage on the secondary side 𝑣𝑆

and low-side terminal voltage 𝑣𝐿𝑆.

3.7.2 Flexible Modulation

The flexible modulation results are demonstrated in Figure 3.34 and Figure 3.35. With 𝑦 = 3

and 𝑥 = 4, the resonant frequencies are 2.8 kHz and 3.2 kHz respectively, so the switching

frequency and effective frequency are chosen at 750 Hz and 3.0 kHz (𝑇𝑠 = 4𝑇𝑒 = 2π). Also,

the duty-cycle and phase-shift value are adjusted to 87.5% and 0.5π accordingly in this case. It

can be observed from Figure 3.34 (a) that the SM switches still achieves soft-switching

vC1(50V/div)

vSM1(50V/div)

iST(2A/div)

200 μs/div

vLS(20V/div)

vS(20V/div)

iST(2A/div)

100 μs/div


operation and the SM capacitor voltage is balanced at 110 V as expected. Figure 3.34 (b) shows

that the low-side terminal voltage is about 55 V and so the step-ratio value in this case is around

7:1. When the modulation is changed to 𝑦 = 2 and 𝑥 = 3, the switching frequency is designed

at 930 Hz since only three SMs participate in the resonance in each 2π cycle (the other two

SMs are bypassed as redundancy, 𝑇𝑠 = 3𝑇𝑒 = 2π), and the duty-cycle and phase-shift are set

at 83.3% and 0.67π respectively. Figure 3.35 (a) shows that all the operational benefits remain

and the SM capacitor voltage is self-balanced at 158 V. The low-side voltage is 79 V and the

overall step-ratio is 5:1 in this modulation scheme.

(a)

(b)




vC1(50V/div)

vSM1(50V/div)

iST(2A/div)

200 μs/div

vLS(50V/div)

iST(2A/div)

vS(20V/div)

100 μs/div


(a)

(b)

Figure 3.35. Experimental results for the modulation of 𝑦 = 2 and 𝑥 = 3. (a) SM1 capacitor voltage



The potential and possibility of this RMMC for low step-ratio conversion are demonstrated in

in Figure 3.36 and Figure 3.37 with the modulation of 𝑦 = 1 and 𝑥 = 5 and 𝑦 = 1 and 𝑥 = 4

respectively. The switching frequency needs to be operated at 2.0 kHz and 2.25 kHz to match

the range of circuit resonant frequencies. As the results show, the inherent balancing capability

and soft-switching operation still exist in the conversion. The SM voltages are balanced at 131

V and 158 V, and the low-side voltage is 263 V and 238 V respectively.

iST(5A/div)

vC1(100V/div)

vSM1(100V/div)

200 μs/div

vLS(50V/div)

iST(5A/div)

vS(50V/div)

100 μs/div


It can be seen that this RMMC has the capability to achieve the low step-ratio conversion.

However, it needs to note that the SM voltage stress and rectifier voltage stress in these low

step-ratio conversion are relatively large and the SM switching frequency is much higher than

that in high step-ratio cases, which may pose serious challenges to both SM devices and

rectifier devices in the practical applications based on the analysis in (3.44) and (3.45). The

circuit topology and operating principle need some specific adjustment and development for

the low step-ratio conversion applications, which will be introduced and analysed in detail in

the next chapter.

(a)

(b)




vC1(100V/div)

vSM1(100V/div)

iST(20A/div)

200 μs/div

vLS(100V/div)

vS(100V/div)

iST(10A/div)

100 μs/div


(a)

(b)

Figure 3.37. Experimental results for the modulation of 𝑦 = 1 and 𝑥 = 4. (a) SM1 capacitor voltage




To fully demonstrate the inherent voltage-balancing capability, the average values of each SM

capacitor voltage during ten 2π cycles under the modulation of 𝑦 = 1,2,3,4, 𝑥 = 5 and 𝑦 =

1,2,3, 𝑥 = 4 are summarised in Figure 3.38.

vC1(100V/div)

vSM1(100V/div)

iST(10A/div)

200 μs/div

vLS(100V/div)

vS(100V/div)

iST(10A/div)

100 μs/div


(a)

(b)


different modulation cases. (a) 𝑦 = 1,2,3,4, 𝑥 = 5. (b) 𝑦 = 1,2,3, 𝑥 = 4.

It can be observed that all the SM capacitor voltages are balanced well around the theoretical

value of (3.42) when the negative stage number 𝑥 is set at 5, which is a prime number and it

cannot have any common divisor with the postage stage number 𝑦. In the modulation of 𝑥 =

4, it can be seen that the SM capacitor voltages are still inherently balanced with 𝑦 = 1 and 𝑦 =

3. However, this converter loses the self-balancing capability at 𝑦 = 2 because 𝑦 and 𝑥 have a


common divisor of 2 in this specific case and their SM capacitor voltages are not all linearly

independent in the operation equation, which validates the analysis in (3.43).

3.7.4 Linearity of Step-ratio Values

Finally, the relationships between the high-side voltage and low-side voltage in various high

step-ratio operation tests are shown in Figure 3.39. The step-ratio values demonstrate good

linearity under different modulation cases, and these experimental results also reach good

agreement with theoretical analysis in (3.3).

Figure 3.39. Experimental results of high-side voltages versus low-side voltage under different

modulation cases.

As a whole, the down-scaled experimental results from Figure 3.33–Figure 3.39 further verify

the theoretical analysis in Section 3.2 and simulations in Section 3.6.

3.8 Chapter Summary

A resonant modular multilevel dc converter (RMMC) based on a LLC resonant structure was

proposed in this chapter. It is intended to realise a bidirectional connection between MVDC

and LVDC networks.


The basic high step-ratio RMMC was derived from the classic LLC resonant circuit by

introducing MMC-like stack of SMs in place of the half-bridge or full-bridge inverter in the

original configuration. It inherits the soft-switching advantage from the original LLC circuit

and also inherits the modularity and high reliability characteristic from the MMC structure. A

phase-shift modulation scheme was developed for this converter that increases the effective

frequency of circuit to facilitate stack volume reduction and also provides inherent voltage

balancing of all the SM capacitors. There is flexibility in choices of phase-shift angle and SM

duty-cycle that can be used to cater for a wide range of step-ratio values. Design guidelines and

modulation constraints were also presented that maintain the soft-switching advantage and

inherent-balancing capability for all the step-ratio cases.

Analysis has shown that the required semiconductor volt-ampere rating and capacitive energy

storage in the SM stack of this converter are relatively small compared to the front-to-front and

direct-chain-link MMC-based dc-dc converters with the expectation that the footprint and cost

could be saved in the practical high step-ratio applications of MVDC and LVDC

interconnection.

It has been demonstrated that this basic high step-ratio RMMC can be employed as building

block for variety of further configurations, including monopolar, bipolar, full-bridge and multi-

module configurations. These various configurations form a family of high step-ratio RMMCs,

which addresses the limitations of step-ratio and power rating of the basic RMMC and satisfies

the higher step-ratio and higher power rating conversion specifications for MVDC and LVDC

interconnection. The approach to creating these derived configurations was also generalized

and applied to other classic dc-dc circuits for medium voltage level high step-ratio conversion.

The theoretical analysis and operating principles have been verified against full-scale

simulations of example converters and further verified against tests on a down-scaled

experimental converter. The results demonstrate that this LLC-based RMMC and its derivatives

family have good potential for operation as high step-ratio dc transformers between MVDC

and LVDC networks.

Chapter 4 Low Step-ratio Resonant Modular

Multilevel DC Converter for MVDC Applications

The investigation of high step-ratio RMMCs in Chapter 3 is now followed in this chapter by

exploration of a new family of low step-ratio RMMCs for bidirectional interconnection

between MVDC links with similar but not identical voltages.

A basic low step-ratio RMMC topology is proposed in Section 4.1, which is evolved from the

basic high step-ratio RMMC. The connection of these two basic RMMCs is presented and a

step-by-step circuit evolution is also provided.

The operating principle and modulation scheme for this low step-ratio RMMC are discussed in

Section 4.2. As expected from operation of the high-step-ratio counterpart, soft-switching is

achieved for all the SM switches of this converter and inherent voltage-balancing is also

realised for each SM capacitor. It will be shown that when the converter is applied for low step-

ratio conversion, the majority of the power throughput passes directly between the two dc links

and only a small fraction needs to be processed by the SM stack. This is an important

characteristic and implies that the required rating for SM stack in terms of semiconductor volt-

ampere rating and capacitive energy storage are very small and, in turn, this may save a lot of

physical space and cost in SM stack in practical low step-ratio applications. The detailed

quantitative analysis for this rating requirement advantage is provided in Section 4.3.

The further configurations and derivative topologies based on this basic low step-ratio RMMC

are analysed and discussed in Section 4.4, and as was the case for the high step-ratio RMMCs,

they form a family of low step-ratio RMMCs which accomplishes the higher voltage rating and

higher power rating conversion and also satisfy the interconnection requirements for various

dc terminal configurations.

108 Low Step-ratio Resonant Modular Multilevel DC Converter for MVDC Applications

Simulation and experiment results are presented and discussed in Section 3.6 and Section 3.7

to illustrate the validity of this low step-ratio RMMC family for low step-ratio MVDC

interconnection.

4.1 Evolution from High-step Ratio RMMC

The basic high step-ratio RMMC is redrawn in Figure 4.1 for analysis. If the low-voltage

terminal 𝑣𝐿𝑆 could be connected with the high-voltage terminal 𝑣𝐻𝑆 in series to form a new

high-voltage terminal 𝑣𝐿𝑆 + 𝑣𝐻𝑆 (the original high-voltage terminal 𝑣𝐻𝑆 becomes the new low-

voltage terminal), this high step-ratio RMMC converter would have the chance to be modified

to a low step-ratio RMMC (𝑅 = (𝑣𝐿𝑆 + 𝑣𝐻𝑆)/𝑣𝐻𝑆) and the value of 𝑣𝐿𝑆 turns to be the voltage

difference between the new high-side terminal (𝑣𝐿𝑆 + 𝑣𝐻𝑆) and the new low-side terminal

(𝑣𝐻𝑆).

Figure 4.1. Basic high step-ratio RMMC.

If the high-side circuit and low-side circuit in Figure 4.1 are grounded at the same point, the

positive terminal voltage of the low-side dc link should be close to the negative terminal voltage

of the high-side dc link due to the high step-ratio conversion and it only needs an extra dc

capacitor in the current path to eliminate this voltage difference and equalise the voltage of

these two terminals for series connection. This capacitor can be called as dc bias capacitor, and

it could also join the resonant operation with the resonant inductor and the SM capacitors. In

addition, noting that the flexibility of the stack modulation ratio is sufficient on its own to fulfil

the low step-ratio voltage transformation and that galvanic isolation is not always a

requirement, the internal transformer used in high step-ratio RMMCs could be removed in this

low-step RMMC with a consequential reduction in volume and increase in efficiency.

Lr

Lm N2N1 CLS vLSvHS CHS

S1

S2

S3

S4

SM1

SM2

SMy

SMx

SMN

4.1 Evolution from High-step Ratio RMMC 109

With this evolution path, the basic low step-ratio RMMC derived from the basic high step-ratio

RMMC is shown in Figure 4.2 (a), in which both the low-side terminal voltage and high-side

terminal voltage are negative, and the symmetrical positive configuration is provided in Figure

4.2 (b). The arrows in Figure 4.2 denote the reference of the voltages and currents in the circuit,

and the terminology is redefined here for clarification. The step-ratio between the high-voltage

terminal (MVDC link with higher voltage) and low-voltage terminal (MVDC link with lower

voltage) is defined as 𝑅 = 𝑣𝐻𝑆/𝑣𝐿𝑆 , and the capacitor 𝐶𝑑𝑖𝑓 supports the voltage difference

between 𝑣𝐻𝑆 and 𝑣𝐿𝑆 (𝑣𝑑𝑖𝑓 = 𝑣𝐻𝑆 − 𝑣𝐿𝑆 = 𝑅𝑣𝐿𝑆 − 𝑣𝐿𝑆). 𝑖𝐿𝑆 and 𝑖𝐻𝑆 are the currents passing

through the low-voltage terminal and high-voltage terminal, and their difference is the average

stack current 𝑖𝑠𝑡̅̅ ̅ ( 𝑖𝑠𝑡̅̅ ̅ = 𝑖𝐿𝑆 − 𝑖𝐻𝑆 = 𝑖𝐿𝑆 − 𝑖𝐿𝑆/𝑅 ). The detailed operating principle and

modulation scheme of this low step-ratio RMMC will be provided in next section.

(a)

(b)

Figure 4.2. Low step-ratio RMMC. (a) Negative configuration. (b) Positive configuration.

LmvLS

ir

Cdif

S1

S2

Lr Cb

vHS

vS1

vb vST

vLm iST

vdif

iHS

iLS

SM1

SM2

SMy

SMx

SMN

vHS

LmvLS

Lr Cb

ir

Cdif vS1

vb

vST

vLm

S2

S1

iST

vdif

iLS

iHS

SM1

SM2

SMy

SMx

SMN


4.2 Operating Principle and Modulation Scheme

The negative configuration is discussed here to illustrate the circuit operation, and the

principles are the same for the positive counterpart.

The resonant operation scheme introduced in Section 3.2 is applied for this low step-ratio

RMMC. By switching either 𝑦 or 𝑥 SM capacitors into the circuit (0 < 𝑦 < 𝑥 ≤ 𝑁) for equal

durations, a symmetrical square-wave voltage 𝑣𝐿𝑚 is imposed across the magnetizing inductor

𝐿𝑚 . This symmetrical square-wave voltage excites an energy exchange between the SM

capacitors (𝐶1 to 𝐶𝑁), the dc bias capacitor 𝐶𝑏 and the resonant inductor 𝐿𝑟, which together

constitute the resonant tank of this low step-ratio RMMC. The dc component of the stack

current goes through the magnetizing inductor while the ac component of stack current flows

into the resonant tank, denoted as resonant current 𝑖𝑟 . The resonant current flows onward

through 𝑆1 when it is positive and the resonant tank is being charged. During this time the high-

voltage terminal current, 𝑖𝐻𝑆, flows from the low-voltage terminal and differential capacitor

𝐶𝑑𝑖𝑓. 𝑆2 conducts when 𝑖𝑟 is negative and the resonant tank is discharging in this period to both

dc terminals and differential capacitor. The output voltage of this resonant tank as seen cross

S1, vs1, is a positive-biased square-wave because of the effect of the dc component voltage on

capacitor 𝐶𝑏. For illustration, a simple half-bridge rectifier (𝑆1 and 𝑆2) is shown in Figure 4.2,

connecting the resonant tank and the differential capacitor, and they can be formed of series

connection appropriate to the voltage difference between 𝑣𝐻𝑆 and 𝑣𝐿𝑆 . If 𝑆1 and 𝑆2 are

configured with reverse-blocked bidirectional switches, the capability for dc fault management

can be also obtained for this converter.

The voltage relationship of this low-step ratio RMMC in the positive stage and negative stage

is given in (4.1) and (4.2).

𝑣𝐿𝑆 = 𝑦𝑣𝐶 + 𝑣𝑏 (4.1)

𝑣𝐻𝑆 = 𝑣𝐿𝑆 + 𝑣𝑑𝑖𝑓 = 𝑥𝑣𝐶 + 𝑣𝑏 (4.2)

4.2 Operating Principle and Modulation Scheme 111

Since the average voltage across the magnetizing inductor 𝐿𝑚 is zero in steady state operation,

the average stack voltage 𝑣𝑠𝑡̅̅ ̅̅ will equal the low-side dc terminal voltage 𝑣𝐿𝑆 (𝑣𝑠𝑡̅̅ ̅̅ = 𝑣𝐿𝑆 ).

According to the voltage-time balance principle on inductor 𝐿𝑚 , and considering equal

durations for the positive and negative stages, the low-side terminal voltage 𝑣𝐿𝑆 is expressed

as (4.3).

𝑣𝐿𝑆 = 𝑣𝑠𝑡̅̅ ̅̅ =𝑥 + 𝑦

2𝑣𝐶 (4.3)

By substituting (4.3) into (4.1) and (4.2), the voltage on dc bias capacitor 𝑣𝑏 and the voltage

step-ratio are derived in (4.4) and (4.5). This converter is designed for low step-ratio conversion

and its maximum step-ratio value is limited to less than 3 with this operational scheme.

𝑣𝑏 =𝑥 − 𝑦

2𝑣𝐶 (4.4)

𝑅 =𝑣𝐻𝑆

𝑣𝐿𝑆=

3𝑥 − 𝑦

𝑥 + 𝑦≤ 𝑅𝑚𝑎𝑥 =

3𝑁 − 1

𝑁 + 1< 3 (4.5)

In the positive stage, the capacitors of 𝑦 SMs join a resonant circuit with capacitor 𝐶𝑏 and

inductor 𝐿𝑟 , and the resonant frequency in this positive stage, 𝑓𝑝 , is expressed in (4.6).

Likewise, the resonant frequency in negative stage, 𝑓𝑛 , is given in (4.7), in which 𝑥 SM

capacitors are deployed in the stack and resonate with 𝐶𝑏 and 𝐿𝑟.

𝑓𝑝 =√𝑦

2𝜋 ∙ √𝐿𝑟(𝐶𝑆𝑀 + 𝑦𝐶𝑏) (4.6)

𝑓𝑛 =√𝑥

2𝜋 ∙ √𝐿𝑟(𝐶𝑆𝑀 + 𝑥𝐶𝑏) (4.7)

The flexible phase-shift modulation scheme discussed in Section 3.2 can be also implemented

for this low step-ratio RMMC. The SMs are all operated with a duty-cycle value of (𝑥 + 𝑦)/2𝑥

at a switching frequency 𝑓𝑠 and they form a sequence of voltage pulses with a phase-shift value

of 2𝜋/𝑥. The effective frequency 𝑓𝑒 of the stack voltage 𝑣𝑆𝑇 and square-wave voltage 𝑣𝐿𝑚 will


be increased to 𝑥/(𝑥 − 𝑦) times of the SM switching frequency 𝑓𝑠, and 𝑓𝑒 is also normally set

at a value between 𝑓𝑝 and 𝑓𝑛 (𝑓𝑝 < 𝑓𝑒 =𝑥

𝑥−𝑦𝑓𝑠 < 𝑓𝑛 ) for good resonant performance and

overall efficiency.

4.2.1 Basic Operation with Lowest Step-ratio Conversion

For further illustration of the operating principles for this low step-ratio RMMC, a detailed

example of low step-ratio conversion ( 𝑦 = 4 and 𝑥 = 𝑁 = 5 ) with bidirectional power

conversion is given in Figure 4.3 and Figure 4.4.

Figure 4.3. Voltage waveforms with 𝑦 = 4, 𝑥 = 5,𝑁 = 5.

0

0

0

0

0

vC1

vC2

vC3

vC4

vC5

Ts=5Te=2πvSM1

vSM2

vSM3

vSM4

vSM5

t

t

t

t

tvST

t

0 t

0.4π

P1 N P2 N

vLm

vC0.5vC0.5

5vC4vC

Tet0

t0

vb

vS1

vC0.5

vC


Figure 4.4. Current flow with 𝑦 = 4, 𝑥 = 5,𝑁 = 5.

It can be seen that each SM capacitor is inserted into the circuit with 90% period of a 2π cycle,

and each SM insertion is phase-shifted by 0.4π from the previous one. The effective frequency

𝑓𝑒 (1/𝑇𝑒) is 5 times of the SM switching frequency 𝑓𝑠 (1/𝑇𝑠) in this operation example (𝑇𝑠 =

5𝑇𝑒 = 2π). Substituting the individual SM capacitor voltages (𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5) into the

equations (4.1) and (4.2), the voltage relationship in a 2π cycle is summarised in (4.8). The

individual SM capacitor voltage can be derived from (4.8) and expressed in (4.9). All the SM

capacitor voltages naturally balance at the value of 2𝑣𝐿𝑆/9 without requirement for extra

voltage adjustment.

Negative Configuration Positive Configuration

Negative Stage (N)

Negative Stage (N)

Positive Stage (P2)

Positive Stage (P1)

vLS

vHS

vLS

vHS

vLS

vHS

vLS

vHS vHS

vLS

vHS

vLS

vHS

vLS

vHS

vLS

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5


[𝐀𝟓,𝟒 𝟏𝟓×𝟏

𝟏𝟏×𝟓 1] ∙ [

𝒗𝑪𝒊

𝑣𝑏] = [

𝟏𝟓×𝟏

𝑅] ∙ 𝑣𝐿𝑆 (4.8)

with 𝐀𝟓,𝟒 =

[ 0 1 1 1 11 0 1 1 11 1 0 1 11 1 1 0 11 1 1 1 0]

and 𝒗𝑪𝒊 =

[ 𝑣𝐶1


𝑣𝐶5 ]

𝑣𝐶1 = 𝑣𝐶2 = 𝑣𝐶3 = 𝑣𝐶4 = 𝑣𝐶5 = 𝑣𝐶 =2𝑣𝐿𝑆

9 (4.9)

Using equations (4.4) and (4.5), the average voltage across the dc bias capacitor is 𝑣𝐿𝑆/9 and

the step-ratio in this example is found to be 11:9. This is a specific case for the lowest step-

ratio conversion with 𝑁 = 5 configuration for this converter and it is obtained with 𝑦 and 𝑥

selected at their maximum values they can have in this case. Moreover, the SM switching

frequency is also the lowest to generate the same the effective frequency for circuit resonance.

4.2.2 General Operation with Flexible Modulation

Another example is given in Figure 4.5 and Figure 4.6 with 𝑦 = 3 and 𝑥 = 𝑁 = 5 to

demonstrate the general operation and modulation flexibility of this low step ratio RMMC. The

phase-shift value and effective frequency keep the same as that in Figure 4.3, but the duty-

cycle is decreased to 80% and each SM voltage has two consecutive negative pulses in a 2π

cycle (2𝑇𝑠 = 5𝑇𝑒 = 2π). The voltage relationship for this operation example is given in (4.10),

and each SM capacitor inherently adopts the voltage in (4.11). Based on (4.4) and (4.5), the dc

average voltage across 𝐶𝑏 is 𝑣𝐿𝑆/4 and the step-ratio in this example is 3:2.

[𝐀𝟓,𝟑 𝟏𝟓×𝟏

𝟏𝟏×𝟓 1] ∙ [

𝒗𝑪𝒊

𝑣𝑏] = [

𝟏𝟓×𝟏

𝑅] ∙ 𝑣𝐿𝑆 (4.10)

with 𝐀𝟓,𝟑 =

[ 0 0 1 1 11 0 0 1 11 1 0 0 11 1 1 0 00 1 1 1 0]

and 𝒗𝑪𝒊 =

[ 𝑣𝐶1


𝑣𝐶5 ]

.


𝑣𝐶1 = 𝑣𝐶2 = 𝑣𝐶3 = 𝑣𝐶4 = 𝑣𝐶5 = 𝑣𝐶 =𝑣𝐿𝑆

4 (4.11)

In general operation of this low step-ratio RMMC, the value of 𝑦 and 𝑥 for the positive stage

and negative stage can be also flexibly chosen from their minimum to maximum values (1 ≤

𝑦 ≤ 𝑁 − 1, 𝑦 + 1 ≤ 𝑥 ≤ 𝑁) to provide various choices for step-ratio value and satisfy various

dc connection specifications. All the SM capacitors voltage will be also self-balanced at

2𝑣𝐿𝑆/(𝑥 + 𝑦) as long as the value of y and x are mutually prime.

Figure 4.5. Voltage waveforms with 𝑦 = 3, 𝑥 = 5,𝑁 = 5.

0

0

0

0

0

vC1

vC2

vC3

vC4

vC5

2Ts=5Te=2π

t

t

t

t

t

t

0 t

0.4π

P1 N P2 N

vSM1

vSM2

vSM3

vSM4

vSM5

vST

vLm

5vC

3vC

vC

Te

t0

t0

vb

vS1

vC

vC

vC2


Figure 4.6. Current flow with 𝑦 = 3, 𝑥 = 5,𝑁 = 5.

4.3 SM Stack Rating

Besides the operational benefits in soft-switching, inherently-balancing and flexible

modulation which are inherited from the high step-ratio RMMCs of Chapter 3, the main

advantage for this low step-ratio RMMC is the low stack rating requirement.

The power conversion process of this low-ratio RMMC is illustrated in Figure 4.7. Figure 4.7

(a) is a representation of Figure 4.2 (a), showing the SM stack with average voltage and current

(𝑣𝑠𝑡̅̅ ̅̅ and 𝑖𝑠𝑡̅̅ ̅), and a simplified resonant tank and rectifier (R+R). As in the original, the high-

Negative Configuration Positive Configuration

Negative Stage (N)

Negative Stage (N)

Positive Stage (P2)

Positive Stage (P1)

vLS

vHS

vLS

vHS

vLS

vHS

vLS

vHS vHS

vLS

vHS

vLS

vHS

vLS

vHS

vLS

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

SM1

SM2

SM3

SM4

SM5

4.3 SM Stack Rating 117

side terminal voltage 𝑣𝐻𝑆 is the sum of the low-side terminal voltage 𝑣𝐿𝑆 and the voltage across

differential capacitor 𝑣𝑑𝑖𝑓 (𝑣𝐻𝑆 = 𝑣𝐿𝑆 + 𝑣𝑑𝑖𝑓). The current from the low-voltage terminal 𝑖𝐿𝑆

divides to flow in two loops (𝑖𝐿𝑆 = 𝑖𝐻𝑆 + 𝑖𝑠𝑡̅̅ ̅): that flowing via the high-voltage terminal, 𝑖𝐻𝑆,

directly transfers power between two dc terminals; that flowing via the SM stack, 𝑖𝑠𝑡̅̅ ̅, transfers

power to the stack which then re-enters the circuit through ac current developed in the resonant

tank. The rectifier passes power to the differential capacitor 𝐶𝑑𝑖𝑓, which then flows to the high-

voltage terminal alongside the direct transferred power. Therefore, the SM stack processes only

a fraction of the power throughput as made clearly by redrawing the circuit in Figure 4.7 (b)

and Figure 4.7 (c). The power directly transferred between two terminals, 𝑃𝐷𝑇, is the blue loop

in Figure 4.7 (c), and the power processed through the SM stack, 𝑃𝑆𝑇, is the green loop, which

sum to give the total power throughput 𝑃𝑇. These powers are described by the relationships

given in (4.12)–(4.14).

𝑃𝑇 = 𝑣𝐿𝑆𝑖𝐿𝑆 = 𝑣𝐻𝑆𝑖𝐻𝑆 = 𝑃𝐷𝑇 + 𝑃𝑆𝑇 (4.12)

𝑃𝐷𝑇 = 𝑣𝐿𝑆𝑖𝐻𝑆 = 𝑣𝐿𝑆

𝑖𝐿𝑆

𝑅=

𝑃𝑇

𝑅=

𝑣𝐿𝑆

𝑣𝐻𝑆 𝑃𝑇 (4.13)

𝑃𝑆𝑇 = 𝑣𝑠𝑡̅̅ ̅̅ ∙ 𝑖𝑠𝑡̅̅ ̅ = 𝑣𝐿𝑆(𝑖𝐿𝑆 − 𝑖𝐻𝑆) = (1 −1

𝑅)𝑃𝑇 = (1 −

𝑣𝐿𝑆

𝑣𝐻𝑆)𝑃𝑇 (4.14)

This low step-ratio RMMC is very suitable for low step-ratio conversion (1 < 𝑅 ≤ 2) to

interface two dc terminals with similar but not identical voltages. It can be seen from (4.13)

and (4.14) that, when the step-ratio of this converter is a little above 1 for low step-ratio

conversion, then the bulk of the power passes directly between two dc terminals and only a

small fraction is processed by the SM stack. If the step-ratio of this converter keeps increasing

to medium ratio range (2 < 𝑅 < 3), the majority of the power will go through the SM stack,

and the requirements for stack semiconductor volt-ampere rating and stack capacitive energy

storage will be both increased.

It is also important to note that there is only one stack in the circuit and the small fraction of

the power throughput, 𝑃𝑆𝑇, passes through the stack just once. Together, these features create

a substantial advantage in terms of stack rating requirement compared to the front-to-front and


direct-chain-link MMC in low step-ratio dc-dc applications. The analysis and comparison in

the following section will quantify those benefits.

(a) (b) (c)

Figure 4.7. Illustration of the power conversion process. (a) Principal current loops. (b)

Equivalent transformation. (c) Separation of power flows.

4.3.1 Stack Semiconductor Volt-ampere Rating

With the analysis in (4.1), (4.2) and (4.5), the stack voltage 𝑣𝑆𝑇 of this low step-ratio RMMC

is given in (4.15). It is a relatively square-wave voltage with a large dc offset. The stack current

𝑖𝑆𝑇 also has both dc and ac components, shown in (4.16), where the dc component is the

average value of 𝑖𝑆𝑇 over each effective cycle 𝑇𝑒 and the ac component is the resonant current

of this circuit.

𝑣𝑆𝑇(𝑡) = 𝑣𝐿𝑆 ∓𝑅 − 1

2𝑣𝐿𝑆 = 𝑣𝐿𝑆 − 𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑒𝑡) ∙

𝑅 − 1

2𝑣𝐿𝑆 (4.15)

𝑖𝑆𝑇(𝑡) = 𝑖𝑑𝑐(𝑡) + 𝑖𝑎𝑐(𝑡) =𝑅 − 1

𝑅𝑖𝐿𝑆 + 𝐼𝑟 𝑠𝑖𝑛

2𝜋

𝑇𝑒𝑡 (4.16)

Similarly with (3.18) and (3.19), the amplitude of the resonant current 𝐼𝑟 can be also derived

from the power balance relationship in (4.17) and written in (4.18).

vLS

Cdif

vHS

iHS

iLS

Lm

StackR+

R

vST

iST

vdif

vLS

Cdif

iHS

iLS

Lm

R+R

iST

vdif

vLS

vLSvHSCdif

iHS

iLS

Lm

StackR+

R

vST

iST

vdif

vLSPDT PT

PST

vLS

vLSvHS

iHS

Stack vST


∫ 𝑣𝐿𝑚(𝑡)𝑖𝑟(𝑡)𝑑𝑡𝑇𝑒

0

=(𝑅 − 1)𝑣𝐿𝑆

2∙ 2∫ 𝐼𝑟𝑠𝑖𝑛

2𝜋

𝑇𝑒𝑑𝑡 = 𝑣𝐿𝑆(𝑖𝐿𝑆−𝑖𝐻𝑆)𝑇𝑒

𝑇𝑒2

0

(4.17)

𝐼𝑟 =𝜋𝑖𝐿𝑆

𝑅 (4.18)

Then, substituting the results of (4.15), (4.16) and (4.18) into (3.15), the operation required

volt-ampere rating for SM stack of this low step-ratio RMMC is shown in (4.19).

𝑅𝑆𝑆𝑇−𝐿𝑆𝑅𝑆 =𝑅2 + 𝜋𝑅 + 𝜋 − 1

𝑅 (4.19)

Also, the volt-ampere rating of the rectifiers S1 and S2 should be also taken into account for a

fair comparison with other MMC-based dc-dc converters. Based on the operation principle in

Section 4.2, the maximum voltage and current of S1 and S2 are expressed in (4.20) and (4.21)

respectively, and their operation required volt-ampere rating is shown in (4.22).

𝑣𝑆1−𝑚𝑎𝑥 = 𝑣𝑆2−𝑚𝑎𝑥 = 𝑣𝐻 − 𝑣𝐿 = (𝑅 − 1)𝑣𝐿𝑆 (4.20)

𝑖𝑆1−𝑚𝑎𝑥 = 𝑖𝑆2−𝑚𝑎𝑥 = 𝐼𝑟 =𝜋𝑖𝐿𝑆

𝑅 (4.21)

𝑅𝑆𝑆1 = 𝑅𝑆𝑆2 =𝜋(𝑅 − 1)

𝑅 (4.22)

Combining (4.19) and (4.22), the overall required volt-ampere rating (including both SM stack

and rectifiers) of this low step-ratio converter is obtained in (4.23).

𝑅𝑆𝑆𝑇−𝐿𝑆𝑅 = 𝑅𝑆𝑆𝑇−𝐿𝑆𝑅𝑆 + 2𝑅𝑆𝑆1 =𝑅2 + 3𝜋𝑅 − 𝜋 − 1

𝑅 (4.23)

According to the analysis in (3.25), the specific volt-ampere rating expression for the

transformer-less front-to-front MMC is presented in (4.24), including both three-phase and

single-phase configurations.


𝑅𝑆𝑆𝑇−𝐹𝑇𝐹 =4𝑅2 + 18𝑅 + 2

𝑅 (4.24)

For the direct-chain-link MMC, the volt-ampere rating expression has been given in (3.26) for

the case of the step-ratio value 𝑅 ≥ 2. When step-ratio value 𝑅 < 2, the calculation process

and result for its required semiconductor volt-ampere rating are presented in (4.25), including

both single-phase leg and two-phase leg configurations.

𝑅𝑆𝑆𝑇−𝐷𝐶𝐿 =2∑ 𝑚𝑎𝑥 |𝑣𝑆𝑇𝑇𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝑆𝑇𝑇𝑗|

𝑁𝑆𝑇𝑇𝑗=1

𝑃𝑇+

2∑ 𝑚𝑎𝑥 |𝑣𝑆𝑇𝐵𝑗| ∙ 𝑚𝑎𝑥 |𝑖𝑆𝑇𝐵𝑗|𝑁𝑆𝑇𝐵𝑗=1

𝑃𝑇

= 2 ∙1


𝑅 − 1


𝑅 − 1


2𝜋

𝑇𝑠𝑡| ∙ 𝑚𝑎𝑥 |𝑖𝐻𝑆 + 2𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡|

+2 ∙1


𝑣𝐻𝑆

𝑅+

𝑅 − 1


2𝜋

𝑇𝑠𝑡| ∙ 𝑚𝑎𝑥 |−(𝑅 − 1)𝑖𝐻𝑆 + 2𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡|

=2𝑅2 + 14𝑅 − 12

𝑅 (4.25)

The detailed comparison results among the low step-ratio RMMC, transformer-less front-to-

front MMC and direct-chain-link MMC are provided in Figure 4.8.

Figure 4.8. Comparison for operation required volt-ampere rating.

Step-Ratio R

Ope

ratio

n R

equi

red

Vol

t-am

pere

Rat

ing

RS S

T

1 31.5 2 2.5

RSST-FTF

RSST-LSR

RSST-DCL

25

12.5

50

0

37.5


It can be seen that the value for the low step-ratio RMMC, 𝑅𝑆𝑆𝑇−𝐿𝑆𝑅, is below 11 (normalised

to power throughput) in its whole step-ratio range (1 < 𝑅 < 3), and this value is much smaller

than 𝑅𝑆𝑆𝑇−𝐹𝑇𝐹 and 𝑅𝑆𝑆𝑇−𝐷𝐶𝐿 for the front-to-front and direct-chain-link MMC alternatives in

this same step-ratio range. This result indicate that this low step-ratio RMMC may save a large

amount of physical volume and cost in its SM stack semiconductor in the case of

interconnection of MVDC links with similar voltages.

4.3.2 Stack Capacitive Energy Storage

Similarly with (3.31), the operation required SM stack capacitive energy storage of this low

step-ratio RMMC is given in (4.26). Based on the analysis in (4.15), (4.16) and (4.18), the SM

stack energy deviation, ∆𝐸𝑆𝑇−𝐿𝑆𝑅, is derived in (4.27).

𝑅𝐸𝑆𝑇−𝐿𝑆𝑅𝑆 =1

4𝛾(𝑚𝑎𝑥

∆𝐸𝑆𝑇−𝐿𝑆𝑅



𝑃𝑇) (4.26)


𝑃𝑇=

1

𝑣𝐿𝑆𝑖𝐿𝑆∫ 𝑣𝑆𝑇(𝑡)𝑖𝑆𝑇(𝑡)𝑑𝑡

𝑡

0

= ∫ {1 − 𝑠𝑔𝑛 [𝑠𝑖𝑛2𝜋𝑥

𝑇𝑠(𝑥 − 𝑦)𝑡] ∙

𝑅 − 1

2} ∙

𝑡

0

[𝑅 − 1

𝑅+

𝜋

𝑅𝑠𝑖𝑛

2𝜋𝑥

𝑇𝑠(𝑥 − 𝑦)𝑡] 𝑑𝑡 (4.27)

The energy storage on dc bias capacitor of this low step-ratio RMMC should be included for a

fair comparison with other MMC-based dc-dc circuits. With (4.4), (4.16) and (4.18), its energy

deviation can be expressed in (4.28).

∆𝐸𝑆𝑇−𝐷𝐵𝐶

𝑃𝑇=

1

𝑣𝐿𝑆𝑖𝐿𝑆∫ 𝑣𝑏(𝑡)𝑖𝑎𝑐(𝑡)𝑑𝑡

𝑡

0

= ∫𝑅 − 1

2∙

𝑡

0

𝜋

𝑅𝑠𝑖𝑛

2𝜋𝑥

𝑇𝑠(𝑥 − 𝑦)𝑡𝑑𝑡 (4.28)

Then, the overall required capacitive energy storage is presented in (4.29) without accounting

dc link capacitors as the same analysis and consideration in Section 3.3.1.2.


𝑅𝐸𝑆𝑇−𝐿𝑆𝑅 =1

4𝛾(𝑚𝑎𝑥




𝑃𝑇) +

1

4𝛾(𝑚𝑎𝑥

∆𝐸𝑆𝑇−𝐷𝐶𝐵


∆𝐸𝑆𝑇−𝐷𝐶𝐵

𝑃𝑇)

(4.29)

For the transformer-less front-to-front MMC, the expression of the operation required stack

capacitive energy storage is the same as (3.33), and its stack energy deviations are written in

(4.30) and (4.31).


𝑃𝑇=

6


1

2𝑣𝐻𝑆 −

1

2𝑅𝑣𝐻𝑆 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡) ∙ (

1

3𝑖𝐻𝑆 +

2

3𝑅 𝑖𝐻𝑆𝑠𝑖𝑛

2𝜋


𝑡

0

= ∫ (−2 𝑠𝑖𝑛22𝜋

𝑇𝑠𝑡 +

2𝑅2 − 1

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡 + 1)

𝑡

0

𝑑𝑡 (4.30)


𝑃𝑇=

6


1

2

𝑣𝐻𝑆

𝑅−

1

2

𝑣𝐻𝑆

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡) ∙ (

1

3𝑅𝑖𝐻𝑆 +

2


2𝜋


𝑡

0

= ∫ (−2𝑠𝑖𝑛22𝜋

𝑇𝑠𝑡 + 𝑠𝑖𝑛

2𝜋

𝑇𝑠𝑡 + 1)

𝑡

0

𝑑𝑡 (4.31)

For the direct-chain-link MMC, the expression of the operation required stack capacitive

energy storage has been provided in (3.36), and the energy deviation analysis for the case of

step-ratio value 𝑅 ≥ 2 has been given in (3.48) and (3.49). When the step-ratio value 𝑅 <

2, the process and result for its energy deviations are presented here in (4.32) and (4.33).


𝑃𝑇=

1


𝑅 − 1


𝑅 − 1


2𝜋

𝑇𝑠𝑡) ∙ (𝑖𝐻𝑆 + 2𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋


𝑡

0

= ∫ [−2(𝑅 − 1)

𝑅𝑠𝑖𝑛2

2𝜋

𝑇𝑠

𝑡 +𝑅 − 1

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠

𝑡 +𝑅 − 1

𝑅]

𝑡

0

𝑑𝑡 (4.32)


𝑃𝑇=

1


𝑣𝐻𝑆

𝑅+

𝑅 − 1


2𝜋

𝑇𝑠𝑡) ∙ [−(𝑅 − 1)𝑖𝐻𝑆 + 2𝑖𝐻𝑆 𝑠𝑖𝑛

2𝜋


𝑡

0


= ∫ [2(𝑅 − 1)

𝑅𝑠𝑖𝑛2

2𝜋

𝑇𝑠

𝑡 −𝑅2 − 2𝑅 − 1

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑠

𝑡 −𝑅 − 1

𝑅]

𝑡

0

𝑑𝑡 (4.33)

The comparison results with low step-ratio 𝑅 = 3: 2, switching frequency 𝑓𝑠 = 500 Hz and

maximum ripple 𝛾 = 10% are summarised in Figure 4.9.

The stack energy deviation of this low step-ratio RMMC is also zero over each effective cycle

((𝑥 − 𝑦)𝑇𝑠 = 𝑥𝑇𝑒), which means the net dc energy and ac energy are naturally balanced in this

stack without requirement for extra adjustment. In other words, the dc energy injecting to the

SM stack is all converted to the ac energy going to the resonant tank. Moreover, the required

stack energy storage for this low step-ratio RMMC is only about 1.4 kJ/MVA, which is clearly

smaller than those for front-to-front and direct-chain-link MMC topologies. This result shows

that there could be also a considerable saving in stack capacitor volume and cost with this low

step-ratio RMMC compared to other MMC-based dc-dc alternatives for medium voltage level

low step-ratio applications.


(𝑅 = 3: 2, 𝑓𝑠 = 500 Hz, 𝑦 = 3, 𝑥 = 5, 𝛾 = 10%,𝑅𝐸𝑆𝑇−𝐿𝑆𝑅 ≈ 1.4 kJ/MVA, 𝑅𝐸𝑆𝑇−𝐹𝑇𝐹 ≈ 6.0 kJ/MVA,

𝑅𝐸𝑆𝑇−𝐷𝐶𝐿 ≈ 2.5 kJ/MVA).

Stac

k E

nerg

y D

evia

tion

(kJ/

MV

A)

Time (ms)0.0 0.4 0.8 1.2 1.6 2.0

1.75

1.25

0.75

0.25

-0.25

6ΔEHSSTj/PT

ΔESTBj/PT

6ΔELSSTj/PT

ΔESTTj/PT

ΔEST-LSRS/PT ΔEST-DBC/PT


4.4 Variety of Configurations

This low step-ratio RMMC can also lend it itself to be the starting point for variety of further

configurations, which can accommodate different configurations of MVDC systems and also

meet the requirements for higher voltage rating and higher power rating conversion.

On the one hand, the ground point of negative configuration and positive configuration can be

easily connected together as the bipolar configuration, shown in Figure 4.10, for bipolar

MVDC system interconnections. The same operation and modulation principles are applied

and all the operation benefits are inherited. Moreover, the switching sequence in the negative

stack can be given a half effective cycle (𝜋/𝑥) phase shift with respect to that in the positive

counterpart to achieve a reduction in voltage ripple on bipolar dc link.

Figure 4.10. Bipolar configuration of the basic low step-ratio RMMC.

On the other hand, pair of converters of the same polarity can be also paralleled directly as the

full-bridge push-pull configuration, shown in Figure 4.11 (a) and Figure 4.11 (b). Each stack

is implemented with a half effective cycle (𝜋/𝑥) phase-shift angle in switching sequence with

respect to other stack, and this create a symmetrical square-wave voltage between the mid-

Lm1vLS-

ir1

Cdif

S11

S12

Lr1 Cb1

vHS-

vS11

vb1

vLm1

vHS+

Lm2vLS+

Lr2 Cb2

ir2

Cdif vS21 vb2

vLm2

S22

S21

SM11

SM12

SM1y

SM1x

SM1N

SM11

SM12

SM1y

SM1x

SM1N


points of the two half-bridge which is equivalent to use full-bridge rectifier. The current will

flow through two resonant tanks (two stacks of SM capacitors, two dc bias capacitors and two

resonant inductors), but the resonant frequencies still keep the same as those in single circuit

operation according to (4.6) and (4.7).

(a)

(b)

Figure 4.11. Full-bridge push-pull configuration of the basic low step-ratio RMMC. (a) Negative

configuration (b) Positive configuration.

Combining the concepts of the series and parallel design, the bipolar full-bridge configuration

is derived and shown in Figure 4.12. It can be considered as a series design of positive and

negative full-bridge configurations or a parallel design of two bipolar arrangements. Since the

rectifier sub-sections are full-bridge architecture, the phase-shift value between the positive

pole and negative pole should be adjusted to a quarter of the effective cycle (𝜋/2𝑥) to achieve

voltage ripple reduction. The switching sequences for the pair of the stacks of the same polarity

are still operated with a half effective cycle (𝜋/𝑥) phase-shift angle to form the symmetrical

vLS

ir1

Cdif Lr1 Cb1

vHS

vb1

Lm2

S21

S22

vS21

vLm2 Lm1

S11

S12

vS11

vLm1

ir2

Lr2Cb2

vb2SM

11

SM12

SM1y

SM1x

SM1N

SM21

SM22

SM2y

SM2x

SM2N

vHS

vLS

Lr1 Cb1

ir1

Cdif

vb1

Lm1

vS11

vLm1

S12

S11

Lm2

vS21

vLm2

S22

S21

Lr2Cb2

ir2

vb2

SM11

SM12

SM1y

SM1x

SM1N SM

21

SM22

SM2y

SM2x

SM2N


square-wave voltage for full-bridge rectifier. The operational advantages of original single

circuit are preserved and the power throughput is four times that of the single circuit.

Figure 4.12. Bipolar full-bridge configuration of the basic low step-ratio RMMC.

4.5 Medium Voltage Application Examples

In this section, a trail design of a medium voltage level low step-ratio RMMC is undertaken

and its simulation results are used to verify the theoretical analysis in Section 4.2 and Section

4.3. Application examples for this low step-ratio RMMC and its derivatives are also explored.

4.5.1 Simulation Results for Single Circuit

The application chosen is bidirectional dc power flow between two monopole MVDC

terminals, as shown the blue box in the centre of Figure 3.25, one at 10 kV and the other in the

range between 10 kV and 20 kV. A high power rating (4 MW ≤ 𝑃𝑇 ≤ 5 MW) is chosen to that

and this can be accomplished with only 5 SMs using a presently available IGBT. The detailed

vLS-

ir1

Cdif- Lr1 Cb1

vHS-

vb1

Lm3

S31

S32

vS31

vLm3 Lm1

S11

S12

vS11 vLm1

ir3

Lr3Cb3 vb3

vHS+

vLS+

Lr2 Cb2

ir2

Cdif+

vb2

Lm2

vS21

vLm2

S22

S21

Lm4

vS41

vLm4

S42

S41

Lr4Cb4

ir4

vb4

Positive Full-bridge

Negative Full-bridge

SM21

SM22

SM2y

SM2x

SM2N SM

41

SM42

SM4y

SM4x

SM4N

SM11

SM12

SM1y

SM1x

SM1N

SM31

SM32

SM3y

SM3x

SM3N


parameters of the design are listed in Table 4.1. From (4.19) and (4.27), it can be found the SM

stack configuration has implemented a very compact and cost-effective design, in which the

normalised semiconductor volt-ampere rating 𝑆𝑆𝑇 is 13.9 (including both SM stack and

rectifiers) and the capacitive energy storage 𝐸𝑆𝑇 is only 3.0 kJ/MVA (including both SM stack

and dc bias capacitors).

Table 4.1. Simulation parameters of the basic low step-ratio RMMC for application examples


𝑃𝑇 Power Throughput 4 MW–5 MW

𝑣𝐻𝑆 Low-side Terminal Voltage 10 kV

𝑣𝐿𝑆 High-side Terminal Voltage 10 kV–20 kV


𝐶𝑏 DC Bias Capacitor 1.2 mF

𝐿𝑟 Resonant Inductance 15.6 µH

𝑁 SM Number 5

𝐶𝑘 SM Capacitance (𝑘 = 1,2, … ,5) 1.2 mF with ±10% variation




𝑆

Power Switches Selected Type ABB 5SNA1500E330305




Simulation results are given in Figure 4.13 for the same operating condition (𝑦 = 4, 𝑥 = 5) as

illustrated in Figure 4.3 and Figure 4.4, which is the lowest step-ratio conversion for this stack

configuration. The switching frequency was operated at 550 Hz to create an effective frequency

of 2.75 kHz for good resonance performance and conversion efficiency (𝑇𝑠 = 5𝑇𝑒 = 2π). The

SM1 output voltage 𝑣𝑆𝑀1 and stack current 𝑖𝑆𝑇 are shown in Figure 4.13 (a). They demonstrate

that the capacitor of SM1 is switched into the stack (𝑣𝑆𝑀1 is high) for 90% period of a 2π cycle,


during which time this capacitor forms part of the resonant circuit, assisting the SM switches

to achieve soft-switching operation. For the remaining 10% of the 2π cycle (𝑣𝑆𝑀1 is low), SM1

is the bypassed and its SM capacitor is not in the conduction path. The stack voltage 𝑣𝑆𝑇 ,

presented in Figure 4.13 (b), is a square-wave voltage with minimum value at about 9 kV for

positive stages and maximum value at about 11 kV for negative stages, which verifies the

analysis in (4.1)–(4.3). The SM capacitances used in the simulation were also deliberately

given a ± 10% variation from the nominal capacitance to reflect manufacturing tolerances.

Figure 4.13 (c) shows that all the SM capacitor voltages are inherently balanced at 2.2 kV

without switching pattern adjustment. The SM capacitor voltage waveforms exhibit the phase-

shift of 0.4π between adjacent SMs. The voltage across dc bias capacitor is about 1.1 kV, which

is half of the SM capacitor average voltage as predicted by (4.4). The amplitude of the resonant

tank output voltage in Figure 4.13 (d) indicate the step-ratio is around 11:9 in this conversion

as expected from (4.5), and the amplitude of the resonant current is about 1000 A, which

demonstrates the total power through in this case is approximately 4 MW based on the analysis

in (4.12) and (4.18).

(a)

(b)


(c)

(d)


RMMC (𝑅 = 11: 9, 𝑃𝑇 = 4 MW). (a) SM1 output voltage 𝑣𝑆𝑀1 and stack current 𝑖𝑆𝑇. (b) Stack voltage

𝑣𝑆𝑇. (c) SM capacitor voltages 𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (d) Resonant tank output voltage 𝑣𝑆1, resonant

current 𝑖𝑟 and dc bias capacitor voltage 𝑣𝑏.

Simulation results for reverse power flow (high-side to low-side) is shown in Figure 4.14.

Operating principle is the same as that in positive power flow, but the stack current direction

and the voltage trend of each SM capacitor are in the opposite sense as those in Figure 4.13.

(a)


(b)

(c)

(d)


RMMC in reverse power flow (𝑅 = 11: 9, 𝑃𝑇 = −4 MW). (a) SM1 output voltage 𝑣𝑆𝑀1 and stack

current 𝑖𝑆𝑇. (b) Stack voltage 𝑣𝑆𝑇. (c) SM capacitor voltages 𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (d) Resonant tank

output voltage 𝑣𝑆1, resonant current 𝑖𝑟 and dc bias capacitor voltage 𝑣𝑏.

Figure 4.15 shows the conversion from 10 kV to 15 kV in which the number of SMs in the

positive stage is adjusted to 3 and the effective frequency is reduced to 2.6 kHz to match the

range of resonant frequencies in this operation (2𝑇𝑠 = 5𝑇𝑒 = 2π). The SM1 and SM2 output


voltage waveforms are given in Figure 4.15 (a) and Figure 4.15 (b) respectively. Comparing to

Figure 4.13, the phase-shift angle between the adjacent SMs is still 0.4π but the duty-cycle is

decreased to 80%. It means each SM capacitor is bypassed for two positive stages and there

are two SMs switched out of the stack for each positive stage. Figure 4.15 (c) verifies all the

SM capacitor voltages are self-balanced at about 2.5 kV. The amplitude value of 𝑣𝑆1 and 𝑖𝑟 in

Figure 4.15 (d) demonstrate that the voltage step-ratio is approximately 3:2 and power

throughput is 4 MW.

(a)

(b)

(c)


(d)


RMMC (𝑅 = 3: 2, 𝑃𝑇 = 4 MW). (a) SM1 output voltage 𝑣𝑆𝑀1 and stack current 𝑖𝑆𝑇. (b) SM2 output

voltage 𝑣𝑆𝑀2 and stack current 𝑖𝑆𝑇. (c) SM capacitor voltages 𝑣𝐶1, 𝑣𝐶2, 𝑣𝐶3, 𝑣𝐶4, 𝑣𝐶5. (d) Resonant tank

output voltage 𝑣𝑆1, resonant current 𝑖𝑟 and dc bias capacitor voltage 𝑣𝑏.

The step-ratio range of this example converter can be extended to about 7:3 within the rated

voltage and current of the selected power devices in Table 4.1, and the maximum power

throughput for this example converter is about 5 MW.

Table 4.2. Power device losses analysis for the lowest step-ratio conversion case

Constituents of Power Losses Value

SM Stack IGBT Conduction 7.195 kW

SM Stack IGBT Switching 2.189 kW

Rectifier IGBT Conduction 1.454 kW

Rectifier IGBT Switching 0.177 kW

Total Losses 11.015 kW

Percentage of Power Throughput 0.28%

The power device losses for the lowest conversion case of this low-step ratio RMMC (𝑅 =

11: 9, 𝑃𝑇 = 4 MW) are shown in Table 4.2. The SM IGBT conduction loss is still the largest

item as expected, and the soft-switching operation decreases both switching losses in SM

IGBTs and rectifiers. Because the majority of the power passes directly between two dc


terminals and only a small fraction is processed by the SM stack and rectifiers, the overall

losses of the power devices only consume 0.28% of the power throughput, which could make

this low step-ratio RMMC to be a very promising candidate for the high power throughput

interconnections of two MVDC links with similar but not identical voltages.

4.5.2 Simulation Results for Further Configurations

To demonstrate the larger power rating connection between two bipolar MVDC terminals, the

bipolar full-bridge topology in Figure 4.12, is configured for ±10 kV to ±12 kV conversion at

15 MW. Each of the four stacks has the same circuit parameters as Table 4.1. The four dc bias

capacitor and four resonant inductors are also subject to 10% variations to represent

manufacturing tolerances. Each stack is operated with the same principles as in the single

circuit operation, so the benefits of low stack rating, soft-switching and self-balancing can be

all inherited. The switching sequences for stack 2 (stack 1) and stack 4 (stack 3) have a half

effective cycle (0.2π) phase-shift angle from each other, forming a minus/plus symmetrical

rectifier input voltage, given in Figure 4.16 (a) and Figure 4.16 (b), which suits the full-bridge

rectifier architecture and also increases the current rating twice. In the meantime, the sequence

difference between stack 2 (stack 4) and stack 1 (stack 3) is set with a quarter of effective cycle

(0.1π), which reduces the ripple on bipolar dc link, shown in Figure 4.16 (c), and also increases

the voltage rating twice. Lastly, the four dc bias capacitor voltages are also self-balanced at the

theoretical value of (4.4), which are demonstrated in Figure 4.16 (d). The voltage and current

stress on each power device of this derivative configuration keep the same value as those in

original single circuit, but its power rating has been increased to four times greater.

(a)


(b)

(c)

(d)

Figure 4.16. Simulation results for the bipolar full-bridge configuration. (a) Positive full-bridge rectifier

input voltage 𝑣𝑟𝑝 (𝑣𝑟𝑝 = 𝑣𝑆21−𝑣𝑆41), resonant currents 𝑖𝑟2 and 𝑖𝑟4. (b) Negative full-bridge rectifier

input voltage 𝑣𝑟𝑛 (𝑣𝑟𝑛 = 𝑣𝑆31−𝑣𝑆11 ), resonant currents 𝑖𝑟1 and 𝑖𝑟3 . (c) Positive and negative dc

terminal voltage 𝑣𝐻𝑆+ and 𝑣𝐻𝑆−. (d) DC bias capacitor voltages 𝑣𝑏1, 𝑣𝑏2, 𝑣𝑏3, 𝑣𝑏4.

4.6 Experimental Results Analysis 135

4.6 Experimental Results Analysis

To verify the theoretical and simulation results of this low step-ratio RMMC, a down-scaled

prototype (see Figure A.2 in Appendix) was built with the parameters of Table 4.3. It also uses

TMS320F28335 as the controller and choose Infineon FF150R12ME3G as the SM power

switches. The stack capacitive energy storage of this prototype is limited less than 3.0 kJ/MVA

in the full range low step-ratio operation, which is in the reasonable range of the mathematical

calculation in Section 4.3.2 and also matches the simulation parameters in Section 4.5.1.

Table 4.3. Experimental prototype parameters of the basic low step-ratio RMMC


𝑃𝑇 Power Throughput 1.5 kW–2.5 kW

𝑣𝐻𝑆 Low-side Terminal Voltage 300 V

𝑣𝐿𝑆 High-side Terminal Voltage 300 V–600 V


𝐶𝑏 DC Bias Capacitor 330 µF

𝐿𝑟 Resonant Inductance 102 µH

𝑁 SM Number 5




4.6.1 Lowest Ratio Conversion

Experimental results for the lowest step-ratio operation (𝑦 = 4, 𝑥 = 5) of this prototype are

shown in Figure 4.17. The switching frequency is chosen as 400 Hz to generate a 2.0 kHz

effective frequency (𝑇𝑠 = 5𝑇𝑒 = 2π), which approximates the resonant frequencies of (4.6)

and (4.7), and the SM duty-cycle and phase-shift value are set with 90% and 0.4π respectively.

It can be seen from Figure 4.17 (a) and Figure 4.17 (b) that each SM capacitor joins the

resonance for 90% period of a 2π cycle and their voltages are self-balanced at about 65 V. The


stack current is a combination of a dc term and a sinusoidal waveform while the stack voltage

contains a square-wave shape with the peak-to-peak value of 66 V, which validates the

theoretical analysis in Figure 4.3. The high-voltage side waveforms are given in Figure 4.17

(c). The resonant tank output voltage is a positive-biased square wave with the amplitude of 64

V and the resonant current is a symmetrical sinusoidal waveform without dc offset. The high-

side voltage of 364 V evident in Figure 4.17 (c) gives a step-ratio of 1.21 which is

approximately 11:9. These experimental results reaches good agreement with the simulation in

Figure 4.13. Additionally, Figure 4.17 (d) shows the switching details of Figure 4.17 (a) and

Figure 4.17 (b). The waveforms confirm that the SM switches achieve zero-voltage-switching

(ZVS) operation at turn-on and the rectifiers achieve zero-current-switching (ZCS) operation

at turn-off.

(a)

(b)

vC1(50V/div)

iST(10A/div)

vSM1(50V/div)

vST(100V/div)

500 μs/div

vC2(50V/div)

iST(10A/div)

vSM2(50V/div)

vST(100V/div)

500 μs/div


(c)

(d)

Figure 4.17. Experimental results for the modulation with 𝑦 = 4 and 𝑥 = 5. (a) Stack voltage 𝑣𝑆𝑇, SM1

capacitor voltage 𝑣𝐶1, SM1 output voltage 𝑣𝑆𝑀1 and stack current 𝑖𝑆𝑇. (b) SM2 capacitor voltage 𝑣𝐶2

and SM2 output voltage 𝑣𝑆𝑀2. (c) High-side voltage 𝑣𝐻𝑆, resonant current 𝑖𝑟 and resonant tank output

voltage 𝑣𝑆1. (d) Switching waveforms of SM1 and rectifier 𝑆1.

4.6.2 Flexible Modulation

The flexibility of modulation and operation is demonstrated by testing conversion between 300

V and 450 V with 𝑦 = 3, 𝑥 = 5 ( 2𝑇𝑠 = 5𝑇𝑒 = 2π ). The duty-cycle is adjusted to 80%

accordingly while the phase-shift value remains at 0.4π. Figure 4.18 (a) and Figure 4.18 (b)

illustrate that two SM capacitors are bypassed in each positive stage and each SM is bypassed

vHS(100V/div)

vS1(20V/div)

ir(5A/div)

500 μs/div

iST(10A/div)

vS1(50V/div)

vSM1(50V/div)

ir(10A/div)

200 μs/div


for two consecutive positive stages. The SM capacitor voltages settle in a balanced fashion at

around 75 V and the ac stack voltage is therefore 150 V peak-to-peak, which verifies the

analysis in Figure 4.5. The amplitude of the resonant tank output voltage in Figure 4.18 (c)

becomes double of the SM capacitor voltage because the voltage across dc bias capacitor is

also 150 V. A high-side voltage of 448 V is seen in Figure 4.18 (c) giving a step-ratio of 1.49

which is very close to the theoretical value of 3:2 for this case. These experimental results

further validate the simulation example in Figure 4.15. Again, the soft-switching operation is

also achieved for both SM switches and rectifiers, shown in Figure 4.18 (d).

(a)

(b)

vC1(50V/div)

iST(10A/div)

vSM1(50V/div)

vST(100V/div)

500 μs/div

vC2(50V/div)

iST(10A/div)

vSM2(50V/div)

vST(100V/div)

500 μs/div


(c)

(d)

Figure 4.18. Experimental results for the modulation with 𝑦 = 3 and 𝑥 = 5. (a) Stack voltage 𝑣𝑆𝑇, SM1

capacitor voltage 𝑣𝐶1, stack current 𝑖𝑆𝑇 and SM1 output voltage 𝑣𝑆𝑀1. (b) SM2 capacitor voltage 𝑣𝐶2

and SM2 output voltage 𝑣𝑆𝑀2. (c) High-side voltage 𝑣𝐻𝑆, resonant current 𝑖𝑟 and resonant tank output

voltage 𝑣𝑆1. (d) Switching waveforms of SM1 and rectifier 𝑆1.


The inherent voltage-balancing capability is demonstrated in Figure 4.19. In the modulation

cases of 𝑥 = 5, shown in Figure 4.19 (a), all the SM capacitor voltages are self-balanced well

around the theoretical results regardless of the value of the positive stage number 𝑦. In the

modulation cases of 𝑥 = 4, shown in Figure 4.19 (b), the SM capacitors can be still inherently

vHS(200V/div)

vS1(50V/div)

ir(5A/div)

500 μs/div

iST(10A/div)

vS1(50V/div)

vSM1(50V/div)

ir(10A/div)

200 μs/div


balanced when 𝑦 = 1 and 𝑦 = 3, but this capability is lost in the specific modulation case of

𝑦 = 2 as expected.

(a)

(b)

Figure 4.19. Experimental results of average voltages of each SM capacitor during 2π cycles under

different modulation cases. (a) 𝑦 = 1,2,3,4, 𝑥 = 5. (b) 𝑦 = 1,2,3, 𝑥 = 4.


4.6.4 Linearity of Step-ratio Values

The relationships between high-side voltage and low-side voltage in various low step-ratio

operation tests are shown in Figure 4.20. The step-ratio values in experiments present good

linearity under different modulation schemes and they also reach good agreement with the

theoretical results of (4.5).

Figure 4.20. Experimental results of high-side voltages versus low-side voltage for different modulation

cases.

As a whole, the down-scaled prototype is seen to operate in close accord with the theory and

simulation presented for these low step-ratio conversion examples.

4.7 Chapter Summary

This chapter described a proposed low step-ratio RMMC that realises bidirectional

interconnection between MVDC links with similar but not identical voltages. It is evolved from

the basic high step-ratio RMMC in Chapter 3. The connection of these two RMMCs has been

given based on circuit analysis, and a step-by-step circuit evolution was also provided.

It has shown that this low step-ratio RMMC inherits all the key operational advantages that

were present in high step-ratio RMMC version including soft-switching operation for SM


switches, inherent balancing of the SM capacitor voltages and high effective switching

frequency for exciting the internal resonance. Noting that the flexibility of the SM stack

modulation ratio is sufficient on its own to fulfil the low-ratio voltage transformation and that

galvanic isolation is not always a requirement, the internal transformer used in high step-ratio

RMMC family was removed with a consequential reduction in volume and increase in

efficiency. Moreover, this low step-ratio RMMC has a significant advantage in required stack

rating over other MMC-based dc-dc circuits for low-step ratio conversion. The SM stack in

this converter is shared between the low-voltage and high-voltage terminals (i.e. it carries only

the difference between the low-side and high-side currents) and consequently it is only required

to process a small fraction of the power throughput because the bulk of the power pass directly

between the two dc terminals. The fraction of power processed, rather than directly passed

through, is small if the voltage ratio is small. Detailed analysis has shown that the required

ratings of this stack in terms of semiconductor volt-ampere rating and capacitive energy storage

are substantially lower than those for the alternative converters using front-to-front and direct-

chain-link MMC configurations. These advantages in terms of component ratings are expected

to make significant savings in footprint and cost for this converter in low step-ratio

applications. This low step-ratio RMMC can also serve as a building block for a variety of

further configurations including bipolar, full-bridge push-pull and bipolar full-bridge

configurations. These derivative configurations and topologies form a family of low step-ratio

RMMCs which can accommodate various configurations of MVDC distribution systems and

achieve higher overall power rating conversion.

The theoretical analysis and principles are verified by both full-scale simulation examples and

down-scaled experimental prototype. The results demonstrate that this low-step ratio RMMC

and its derivatives, have good potential for operation as highly-compact and low-cost dc

transformers for MVDC link interconnection.

Chapter 5 High Step-ratio Modular Multilevel DC-

AC-DC Converter for HVDC Applications

The previous two chapters (Chapter 3 and Chapter 4) discussed circuits, operating principles

and modulation schemes for resonant modular multilevel dc converters. However, both the

high step-ratio and low step-ratio variants would face technical difficulty if the dc link voltage

were increased to typical HVDC values. For a single circuit RMMC, the difficulties for stack

modulation design and effective frequency choice increase quickly as the SM total number

rises. The multi-module configuration of a single circuit RMMC could alleviate these concerns,

but it needs to address the additional insulation and reliability issues of the many module

transformers. When the dc link voltage extends beyond 100 kV, an RMMC would need either

a large number of SMs or a large number of circuit modules to support the dc link voltage and

the challenges in design and operation of the RMMCs become too great. To rise to the

challenge of high voltage level dc interconnection, two non-resonant modular multilevel dc

converters are proposed and developed in Chapter 5 for high step-ratio conversion, and Chapter

6 for low step-ratio conversion.

This chapter presents a modular multilevel dc converter for high step-ratio low power

throughput connection between an HVDC transmission terminal and an MVDC network. It is

a single-active-bridge (SAB) / dual-active-bridge (DAB) dc-ac-dc converter using modular

multilevel structure, and the detailed descriptions will be given in Section 5.1. It inherits the

medium-frequency operation and soft-switching benefits from the original SAB/DAB

converter which facilitate the reduction of physical volume and good efficiency, and it also

inherits the modularity and high reliability features of the MMC structure that are important

for HVDC applications. High step-ratio conversion is accomplished by a combination of the

inherent ratio of 2 of the half-bridge configuration, the SM stack modulation ratio and

144 High Step-ratio Modular Multilevel DC-AC-DC Converter for HVDC Applications

transformer turns-ratio. Together these are expected to offer flexibility in both design and

operation to provide a wide choice of overall step-ratio values.

Operation with near-square-wave current is proposed for this converter in Section 5.2. Near-

square-wave current is chosen over sinusoidal in the expectation of decreasing the required

volt-ampere rating of the semiconductor power devices and also reducing the capacitive energy

requirement for both SM stack capacitors and dc link capacitors. This will be assessed through

circuit operation analysis and relevant sizing equations. An energy balance method and a

control strategy for this mode of operation are also provided in Section 5.3. It will be shown

that the converter can be controlled in current source mode to interface dc links with different

voltage levels and it can be also operated in voltage source mode to collect the power from

offshore wind farms or feed power to an isolate grid in a remote area.

The circuit performance is analysed in Section 5.4, and the main advantages and disadvantages

of this converter are discussed in detail. The full-scale simulation examples and down-scaled

prototype experiments are provided in Section 5.5 and Section 5.6 respectively, and the results

verify the theoretical analysis and demonstrate the capability of this converter for the

interconnection between an HVDC terminal and an MVDC network.

5.1 Topology Derivation and Description

The schematic of this high step-ratio modular multilevel dc-ac-dc converter is illustrated in

Figure 5.1. The overall step-ratio between high–side (HVDC side) terminal voltage and low-

side terminal voltage (MVDC side) is defined as 𝑅 = 𝑣𝐻𝑆/𝑣𝐿𝑆. On the high-voltage side, the

circuit is derived from the single-phase half-bridge inverter with SM stacks replacing each of

the switch positions. It processes all the power by only two SM stacks, so the total volume

required by SM stacks and isolation clearances can be kept low. The two half-bridge SMs

stacks, SMT and SMB, in the top and bottom arm respectively, form a single phase MMC

configuration with arm inductors 𝐿𝑇 and 𝐿𝐵 . There are 𝑁 SMs in total, divided equally

between top and bottom stacks. The primary winding of the transformer (𝑟𝑇 = 𝑁1/𝑁2) is

connected between the phase midpoint and a neutral point created by two dc link capacitors 𝐶𝑇

and 𝐶𝐵. Considering the high step-ratio conversion, the low-voltage side use a diode/active

5.2 Operating Principle and Near-square-wave Modulation 145

bridge rectifier arrangement for unidirectional/bidirectional power flow, simplifying the

configuration and also achieving soft-switching operation. For illustration, a simple full-bridge

diode rectifier (formed of series connected diodes appropriate to the voltage rating) is chosen

to connect the transformer secondary winding to a smoothing capacitor 𝐶𝐿𝑆 on the low-voltage

side. Controllable devices can be used in rectifier for bidirectional power flow. 𝐹𝐻𝑆 and 𝐹𝐿𝑆 are

filters on the high-voltage and low-voltage sides, formed of parallel inductors and resistors to

confine ac current components to circulate within the converter.

Figure 5.1. High step-ratio modular multilevel dc-ac-dc converter.

5.2 Operating Principle and Near-square-wave Modulation

Figure 5.2 shows that there are six stages in one operation cycle 𝑇𝑜, and the specific equivalent

circuits for each stage are given in Figure 5.3. The first three stages over 𝑡0–𝑡3 constitute the

first half of the operational cycle and the last three stages over 𝑡4–𝑡6 are symmetrical to 𝑡0–𝑡3.

The arrows in Figure 5.1 define the voltage and current reference directions for the waveforms

of Figure 5.2 (and the rest of this chapter), and the arrows in Figure 5.3 display the expected

current flow in each stage.

LT

LB

vHS

vLS

N1

N2

CT

CB

D1 D3

D2 D4

CLS

vSTT

vSTBiSTB

iSTT

iHS

vS

iSvD1

vLT

vLB

iLS

FHS

FHS

FLS

FLS

vP

vCT

vCBSMB

SMB

SMB

SMB

SMT

SMB

SMT

SMT

SMT

SMT


Figure 5.2. Voltage and current waveforms in one operation cycle.

In Figure 5.2, the following symbols are used: 𝑣𝐻𝑆 and 𝑖𝐻𝑆, 𝑣𝐿𝑆 and 𝑖𝐿𝑆 are the voltage and

current on high-voltage side and low-voltage side; 𝑛𝑇 and 𝑛𝐵 are used to describe the number

of SMs in the on-state (meaning that the upper switch is on and the lower is off) for the top

stack and bottom stack respectively; 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵, 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵 are the voltages across and

currents through the top stack and bottom stack; 𝑣𝐿𝑇 and 𝑣𝐿𝐵 are the voltage across arm

inductors 𝐿𝑇 and 𝐿𝐵 ; 𝑣𝐷1 to 𝑣𝐷4 and 𝑖𝐷1 to 𝑖𝐷4 are the voltages and currents of the rectifier

diodes 𝐷1 to 𝐷4; 𝑣𝑃 and 𝑖𝑃, 𝑣𝑆 and 𝑖𝑆 are the voltage and current on the transformer primary

side and secondary side.

In Figure 5.3, the bold black box for SM means this SM is in the on-state and its capacitor is

inserted into the circuit while the pink box for SM means this SM is in the off-state (meaning

vSTT vSTB

iSTB iSTT

vLB vLT

nT-smanB-lar

t0 t1 t3t2 t4 t5 t6 t7(t1)(t0)

nT-larnB-sma

nT-al lnB-non

vD1,D4 iD1,D4

vD2,D3iD2,D3

t

nT-nonnB-al l

nT-smanB-lar

nT-larnB-sma

nT-al lnB-non

nT-nonnB-al l

nT-smanB-lar


that the upper switch is off and the lower is on) and its capacitor is bypassed. It is also worth

noting that the total number of SMs inserted between positive terminal and negative terminal

of the high-voltage dc link is not constant, and the sum of 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵 varies in different

operation stages. The operating principles for each stage will be analysed in detail in the

following subsections.

(a)

(b)

LT

LB

N1

N2

CT

CB

D1 D3

D2 D4

CL

vHS

vLS

FHS

FHS

FLS

FLSSMB

SMB

SMB

SMB

SMT

SMT

SMT

SMT

LT

LB

N1

N2

CT

CB

D1 D3

D2 D4

CL

vHS

vLS

FHS

FHS

FLS

FLSSMB

SMB

SMB

SMB

SMT

SMT

SMT

SMT


(c)

(d)

LT

LB

N1

N2

CT

CB

D1 D3

D2 D4

CL

vHS

vLS

FHS

FHS

FLS

FLSSMB

SMB

SMB

SMB

SMT

SMT

SMT

SMT

LT

LB

N1

N2

CT

CB

D1 D3

D2 D4

CL

vHS

vLS

FHS

FHS

FLS

FLSSMB

SMB

SMB

SMB

SMT

SMT

SMT

SMT


(e)

(f)

Figure 5.3. Equivalent circuits and operation analysis. (a) Stage 1 (𝑡0–𝑡1). (a) Stage 2 (𝑡1–𝑡2). (a) Stage

3 (𝑡2–𝑡3). (d) Stage 4 (𝑡3–𝑡4). (e) Stage 5 (𝑡4–𝑡5). (f) Stage 6 (𝑡5–𝑡6).

Stage 1: Positive Steady-State (𝒕𝟎–𝒕𝟏)

In this stage, a small number of the SMs in the top stack (𝑛𝑇−𝑠𝑚𝑎) and a large number of the

SMs in the bottom stack (𝑛𝐵−𝑙𝑎𝑟 ) are in the on-state, generating steady voltage values of

LT

LB

N1

N2

CT

CB

D1 D3

D2 D4

CL

vHS

vLS

FHS

FHS

FLS

FLSSMB

SMB

SMB

SMB

SMT

SMT

SMT

SMT

LT

LB

N1

N2

CT

CB

D1 D3

D2 D4

CL

vHS

vLS

FHS

FHS

FLS

FLSSMB

SMB

SMB

SMB

SMT

SMT

SMT

SMT


𝑣𝑆𝑇𝑇(𝑡0) and 𝑣𝑆𝑇𝐵(𝑡0). Summed together they match the high-side dc link voltage 𝑣𝐻𝑆 but the

split is such that a positive voltage is applied to the transformer winding. The stack voltages

are described in (5.1) and (5.2) under the assumptions that the dc link capacitor voltage 𝑣𝐶𝑇

and 𝑣𝐶𝐵 are balanced and all the SM capacitor voltages are well-controlled at their reference

value 𝑣𝐶∗ . The sum of 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵 equals to 𝑣𝐻𝑆, shown in (5.3), and the voltages across the

top arm inductor and bottom arm inductor are both 0. This stage is considered to be the positive

steady-state. The stack currents through the arm inductors maintain at values of 𝑖𝑆𝑇𝑇(𝑡0) and

𝑖𝑆𝑇𝐵(𝑡0), expressed in (5.4) and (5.5). Diodes 𝐷1 and 𝐷4 are in conduction whereas 𝐷2 and 𝐷3

are reverse-biased.

𝑣𝑆𝑇𝑇(𝑡) = 𝑣𝑆𝑇𝑇(𝑡0) =𝑣𝐻𝑆

2− 𝑟𝑇𝑣𝐿𝑆 = 𝑛𝑇−𝑠𝑚𝑎 ∙ 𝑣𝐶

∗ (5.1)

𝑣𝑆𝑇𝐵(𝑡) = 𝑣𝑆𝑇𝐵(𝑡0) =𝑣𝐻𝑆

2+ 𝑟𝑇𝑣𝐿𝑆 = 𝑛𝐵−𝑙𝑎𝑟 ∙ 𝑣𝐶

∗ (5.2)

𝑣𝑆𝑇𝑇(𝑡) + 𝑣𝑆𝑇𝐵(𝑡) = (𝑛𝑇−𝑠𝑚𝑎+𝑛𝐵−𝑙𝑎𝑟) ∙ 𝑣𝐶∗ = 𝑣𝐻𝑆 (5.3)

𝑖𝑆𝑇𝑇(𝑡) = 𝑖𝑆𝑇𝑇(𝑡0) = 𝑖𝐻𝑆 +𝑖𝐿𝑆

2𝑟𝑇 (5.4)

𝑖𝑆𝑇𝐵(𝑡) = 𝑖𝑆𝑇𝐵(𝑡0) = 𝑖𝐻𝑆 −𝑖𝐿𝑆

2𝑟𝑇 (5.5)

Stage 2: Force Current Reversal (𝒕𝟏–𝒕𝟐)

A rapid current reversal is required for the near-square-wave operation and to achieve this all

of the SMs in the top stack are turned on (𝑛𝑇−𝑎𝑙𝑙) at 𝑡1 and all SMs in the bottom are turned off

(𝑛𝐵−𝑛𝑜𝑛) to impose the largest possible negative voltage across the arm inductor. Figure 5.3

(b) shows the commutation of the stack currents during this short stage. The stack voltage and

current relationship over this period are given in (5.6)–(5.9). It needs to note that the controller

can pre-set a slope limiter for the transient currents in (5.8) and (5.9), especially for the low

current operation. The inserted SM number in transient stages and transient waveform are also

adjustable according to the controller capability and practical requirements.


𝑣𝑆𝑇𝑇(𝑡) = 𝑛𝑇−𝑎𝑙𝑙 ∙ 𝑣𝐶 = 𝑛𝑇 ∙ 𝑣𝐶 =𝑁

2∙ 𝑣𝐶

∗ (5.6)

𝑣𝑆𝑇𝐵(𝑡) = 𝑛𝐵−𝑛𝑜𝑛 ∙ 𝑣𝐶∗ = 0 (5.7)

𝑖𝑆𝑇𝑇(𝑡) = 𝑖𝑆𝑇𝑇(𝑡1) +1

𝐿𝑇[𝑣𝐻𝑆

2− 𝑣𝑆𝑇𝑇(𝑡) − 𝑟𝑇𝑣𝐿𝑆] (𝑡 − 𝑡1) (5.8)

𝑖𝑆𝑇𝐵(𝑡) = 𝑖𝑆𝑇𝐵(𝑡1) +1

𝐿𝐵[𝑣𝐻𝑆

2− 𝑣𝑆𝑇𝐵(𝑡) + 𝑟𝑇𝑣𝐿𝑆] (𝑡 − 𝑡1) (5.9)

The control headroom 𝐶ℎ shown in (5.10), is the additional negative voltage available over and

above that which will be needed to maintain the negative steady-state current. A larger value

allows a faster transition of current and a waveform closer to square.

𝐶ℎ =𝑛𝑇−𝑎𝑙𝑙,𝐵−𝑎𝑙𝑙 − 𝑛𝑇−𝑙𝑎𝑟,𝐵−𝑙𝑎𝑟

𝑛𝑇−𝑎𝑙𝑙,𝐵−𝑎𝑙𝑙=

𝑁 − (𝑛𝑇−𝑙𝑎𝑟 + 𝑛𝐵−𝑙𝑎𝑟)

𝑁 (5.10)

The sum of 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵 in this stage can be expressed as (5.11). Compared with (5.3), it can

be found this value would be smaller than 𝑣𝐻𝑆 in the normal operation unless the control

headroom 𝐶ℎ is very large in the design.

𝑣𝑆𝑇𝑇(𝑡) + 𝑣𝑆𝑇𝐵(𝑡) =𝑁

2∙ 𝑣𝐶

∗ =𝑛𝑇−𝑙𝑎𝑟

1 − 𝐶ℎ∙ 𝑣𝐶

∗ = (𝑛𝑇−𝑙𝑎𝑟+𝐶ℎ

1 − 𝐶ℎ𝑛𝑇−𝑙𝑎𝑟) ∙ 𝑣𝐶

∗ (5.11)

This stage ends when 𝑖𝐷1 and 𝑖𝐷4 reduce to zero at 𝑡2. Note that 𝑣𝐷1 and 𝑣𝐷4 enter reverse-bias

after 𝑖𝐷1 and 𝑖𝐷4 drop to zero and thus the soft-switching turn-off operation is achieved.

Stage 3: Establish Negative Steady-State (𝒕𝟐–𝒕𝟑)

Having commuted the diodes, it is now necessary to establish the steady negative current. The

SMs are kept the same states until 𝑡3, at which point the stack currents reach the new steady

values of 𝑖𝑆𝑇𝑇(𝑡3) and 𝑖𝑆𝑇𝐵(𝑡3) and the transient period is finished. As Figure 5.3(c) illustrates,

after the transformer current changed direction at 𝑡2 , the slopes of 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵 become


shallower for 𝑡2–𝑡3 because 𝐷2 and 𝐷3 are in conduction and the low-side voltage appears in

the opposite sense.

Stage 4: Negative Steady-State (𝒕𝟑–𝒕𝟒)

At 𝑡3, with the new currents established, the controller turns off some of SMs in the top stack

(the number turned on reduces from 𝑛𝑇−𝑎𝑙𝑙 to 𝑛𝑇−𝑙𝑎𝑟) and turns on a small number in the

bottom stack (𝑛𝐵−𝑠𝑚𝑎). This is a symmetrical case to Stage 1, and the descriptions of stack

voltage and current are similar to (5.1)–(5.5) but with the top and bottom stack value replacing

each other.

Stage 5 (𝒕𝟒–𝒕𝟓) and Stage 6 (𝒕𝟓–𝒕𝟔)

All of the SMs in the top stack are turned off (𝑛𝑇−𝑛𝑜𝑛) and all SMs in the bottom are turned on

(𝑛𝐵−𝑎𝑙𝑙) at t4 to rapidly reduce the negative current to zero. The diodes commutate at 𝑡5 (the

end of Stage 5) and the current continues its transition toward the positive steady value. The

operating principles of Stage 5 and Stages 6 are the same as Stage 2 and Stage 3. The control

headroom is used again to accelerate the current transition. When stack currents reach their

steady-state values, 𝑖𝑆𝑇𝑇(𝑡6) and 𝑖𝑆𝑇𝐵(𝑡6), the converter returns to Stage 1 and the next cycle

of operation begins.

5.3 Energy Management and Control Solution

The capacitor voltage of the kth SM in the top stack (𝑘 = 1,2, … ,𝑁/2) is represented by 𝑣𝐶𝑇𝑘,

and 𝑣𝐶𝐵𝑘 is the equivalent for the bottom stack. In line with the definition in (3.27), the

normalized value of the capacitive energy stored in each stack, 𝐸𝑆𝑇𝑇 and 𝐸𝑆𝑇𝐵, is expressed as

(5.12) under the assumption that all the SM capacitances are equal to 𝐶𝑆𝑀, and the reference

value for the total stack energy storage is given in (5.13).

𝐸𝑆𝑇𝑇,𝑆𝑇𝐵 =∑

12

𝑁2𝑘=1 𝐶𝑆𝑀𝑣𝐶𝑇𝑘,𝐶𝐵𝑘

2

𝑃𝑇

(5.12)

5.3 Energy Management and Control Solution 153

𝐸𝑆𝑇∗ =

12𝐶𝑆𝑀𝑣𝐶

∗2 ∙ 𝑁

𝑃𝑇 (5.13)

The objective of energy management is twofold: maintain the sum of 𝐸𝑆𝑇𝑇 and 𝐸𝑆𝑇𝐵 equal 𝐸𝑆𝑇∗ ,

shown in (5.14), and keep the difference between them to zero, given in (5.15).

𝐸𝑆𝑇𝑇 + 𝐸𝑆𝑇𝐵 = 𝐸𝑆𝑇∗ (5.14)

𝐸𝑆𝑇𝑇 − 𝐸𝑆𝑇𝐵 = 0 (5.15)

The analysis in Stage 1 and Stage 4 of the two steady-state stages revealed that the stack

voltages comprise a dc offset 𝑣𝐻𝑆/2 and an ac component ± 𝑟𝑇𝑣𝐿𝑆. The stack currents also

comprise a dc component 𝑖𝐻𝑆 and an ac current ± 𝑖𝐿𝑆/2𝑟𝑇. The energy deviation ∆𝐸𝑆𝑇𝑇,𝑆𝑇𝐵 in

one operation cycle can be approximated as (5.16) by neglecting the very short transient period.

∆𝐸𝑆𝑇𝑇,𝑆𝑇𝐵 = (𝑣𝐻𝑆

2∓ 𝑟𝑇𝑣𝐿𝑆) (𝑖𝐻𝑆 ±

𝑖𝐿𝑆

2𝑟𝑇) ∙

𝑇𝑜

2+ (

𝑣𝐻𝑆

2± 𝑟𝑇𝑣𝐿𝑆) (𝑖𝐻𝑆 ∓

𝑖𝐿𝑆

2𝑟𝑇) ∙

𝑇𝑜

2

=(𝑣𝐻𝑆𝑖𝐻𝑆 − 𝑣𝐿𝑆𝑖𝐿𝑆) ∙ 𝑇𝑜

2 = 0 (5.16)

It can be seen that energy deviations from the ac and dc terms are zero over an operation cycle

without extra balancing control. The stack energy of this converter is naturally balanced if the

original state satisfies the conditions in (5.14) and (5.15). A transient energy drift or an initially

unbalanced state can be corrected by adding an extra dc component ∆𝑖𝑑𝑐 and an ac component

± ∆𝑖𝑑𝑐/2𝑟𝑇 into the stack currents and thereby the stack energy deviations are adjusted

according to (5.17).

∆𝐸𝑆𝑇𝑇,𝑆𝑇𝐵, = (

𝑣𝐻𝑆

2∓ 𝑟𝑇𝑣𝐿𝑆) ∙ [(𝑖𝐻𝑆 + ∆𝑖𝑑𝑐) ±

𝑖𝐿𝑆 ± ∆𝑖𝑎𝑐

2𝑟𝑇] ∙

𝑇𝑜

2+ (

𝑣𝐻𝑆

2± 𝑟𝑇𝑣𝐿𝑆) ∙

[(𝑖𝐻𝑆 + ∆𝑖𝑑𝑐) ∓𝑖𝐿𝑆 ± ∆𝑖𝑎𝑐

2𝑟𝑇] ∙

𝑇𝑜

2=

[𝑣𝐻𝑆(𝑖𝐻𝑆 + ∆𝑖𝑑𝑐) − 𝑣𝐿𝑆(𝑖𝐿𝑆 ± ∆𝑖𝑎𝑐)] ∙ 𝑇𝑜

2 (5.17)


The sum and difference of the energy deviation for the two stacks are given in (5.18) and (5.19),

which reveal the adjustments for sum and difference of the stack energies are decoupled in this

converter: ∆𝑖𝑑𝑐 alone sets the change in the sum and ∆𝑖𝑎𝑐 sets the change in the difference.

∆𝐸𝑆𝑇𝑇, + ∆𝐸 𝑆𝑇𝐵

, = 𝑣𝐻𝑆∆𝑖𝑑𝑐𝑇𝑜 (5.18)

∆𝐸𝑆𝑇𝑇, − ∆𝐸 𝑆𝑇𝐵

, = −𝑣𝐻𝑆∆𝑖𝑎𝑐𝑇𝑜

𝑅 (5.19)

The use of proportional–integral (PI) controllers for the energy management of the sum and

difference of stack energies are illustrated in Figure 5.4 and Figure 5.5.

Figure 5.4. Energy management of dc components.

Figure 5.5. Energy management of ac components.

Figure 5.4 shows three terms combining to the dc components of stack current references,

𝑖𝑆𝑇𝑇−𝑑𝑐∗ and 𝑖𝑆𝑇𝐵−𝑑𝑐

∗ , namely: an adjustment for stack energy sum ∆𝑖𝑑𝑐; the high-voltage side

current reference 𝑖𝐻𝑆∗ and an adjustment for the dc link capacitor voltage balance ∆𝑖𝐶𝑇,𝐶𝐵 .

Figure 5.5 shows three terms combining to form the ac components of stack current references,

+

−

ESTT + ESTB

+−

vCT,CB

PI

PI

++−

,

dc-link capacitor voltage controller

stack energy sum controller

dc components of stack current reference

*STBdci*

STTdci

*STTdc,STBdci*

HSiΔ dci

Δ CT,CBi2*HSv

EST *

+

−

+−

± +

0

0

ESTT − ESTB

sqw(t),

transformer average current controller

PI

PI

stack energy difference controller

ac components of stack current reference

*STTaci *

STBaci*STTac,STBaci

2rT

Δ aci

2rT

LSi*

ΔD

Si

5.3 Energy Management and Control Solution 155

𝑖𝑆𝑇𝑇−𝑎𝑐∗ and 𝑖𝑆𝑇𝐵−𝑎𝑐

∗ , namely: an adjustment for the stack energy difference ∆𝑖𝑎𝑐/2𝑟𝑇; the low-

voltage side current reference 𝑖𝐿𝑆∗ /2𝑟𝑇 and a duty-cycle adjustment ∆𝐷 for transformer average

current neutralization. The complete stack current references for top and bottom, 𝑖𝑆𝑇𝑇∗ and 𝑖𝑆𝑇𝐵

∗ ,

including all the balancing terms, are summarised in (5.20), in which the square-wave function

𝑠𝑞𝑤(𝑡) for each operation cycle 𝑇𝑜, is defined as (5.21).

𝑖𝑆𝑇𝑇,𝑆𝑇𝐵∗ = 𝑖𝑆𝑇𝑇𝑑𝑐,𝑆𝑇𝐵𝑑𝑐

∗ + 𝑖𝑆𝑇𝑇𝑎𝑐,𝑆𝑇𝐵𝑎𝑐∗

= 𝑖𝐻𝑆∗ + ∆𝑖𝑑𝑐 − ∆𝑖𝐶𝑇,𝐶𝐵 ±

𝑖𝐿𝑆∗ ± ∆𝑖𝑎𝑐

2𝑟𝑇∙ 𝑠𝑞𝑤(𝑡) (5.20)

𝑠𝑞𝑤(𝑡) = {1, 00 < 𝑡 ≤

𝑇𝑜

2+ 𝑇𝑜 ∙ ∆𝐷

−1,0 𝑇𝑜

2+ 𝑇𝑜 ∙ ∆𝐷 < 𝑡 ≤ 𝑇𝑜

(5.21)

The entire control scheme is shown in Figure 5.6. It comprises an outer loop to regulate 𝑣𝐿𝑆

which sets the principal reference for the inner current loop to which the balancing terms are

added according to the energy management algorithms from Figure 5.4 and Figure 5.5. The

detailed expression for stack current references is shown in (5.20) and (5.21). The inner loop

can be used for the current source mode (CSM) operation, in which the converter is controlled

to interface dc networks at different voltage levels (HVDC and MVDC). By adding the outer

loop for voltage control, this converter is operated in voltage source mode (VSM) to collect the

power from offshore wind farms or feed the power to some remote area loads.

Figure 5.6. Control scheme for this high step-ratio modular multilevel dc-ac-dc converter.

+*STTi

iSTT

+−

PI

vCT

1/sLT+

SMT

*STTv

+*STBi

iSTB

PI

vCB

1/sLB+

SMB

*STBv

vSTT

vSTB

+

−1/sCLrT

iLS vLS

+

−PI

vLSiLS/vHS

1/2rT

+−

*LSi

vN1

+

−

−

−

Inner Current Loop

Outer Voltage Loop

energy management of top stack

current reference of top stack

current reference of bottom stack

current controller of top stack

SMT voltage sorting and selection

low-side voltage Controller

vN1

iN1

energy management of bottom stack

current controller of bottom stack

Nearest Level Modulation (NLM)

Nearest Level Modulation (NLM)

*HSi

Sort and Select

SMB voltage sorting and selection

Sort and Select

*STTdci*STTaci

*STBaci

*STBdci

*STTi

*STBi

*LSv


The modulation scheme in Figure 5.6 is a classic nearest level modulation (NLM) [157] to

balance all SM capacitor voltages close to the reference voltage 𝑣𝐶∗ . The stack sorts the SMs in

the order of SM capacitor voltage, and the first 𝑁𝑁𝐿𝑀 SMs with lowest voltages are inserted

into the stack when the stack current direction is charging SM capacitors while the highest

𝑁𝑁𝐿𝑀 SMs are switched into the stack when the current direction is discharging (𝑁𝑁𝐿𝑀 =

⌊𝑣𝑆𝑇𝑇,𝑆𝑇𝐵∗ /𝑣𝐶

∗⌋).

5.4 Circuit Performance Analysis

The circuit performance of this high step-ratio modular multilevel dc-ac-dc converter is

presented in this section, and its advantages and disadvantages in operation will be also

analysed and discussed.

5.4.1 SM Stack Rating

The near-square-wave current operation can benefit in both stack semiconductor volt-ampere

rating and stack capacitive energy storage over the standard sinusoidal operation.

5.4.1.1 Stack Semiconductor Volt-ampere rating

With the analysis in (5.1)–(5.5), the stack voltage and current can be approximately expressed

as (5.22) and (5.23) respectively neglecting the short transient period and small control

adjustments.

𝑣𝑆𝑇𝑇,𝑆𝑇𝐵(𝑡) =𝑣𝐻𝑆

2∓ 𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡)


𝑅 (5.22)

𝑖𝑆𝑇𝑇,𝑆𝑇𝐵(𝑡) = 𝑖𝐻𝑆 ± 𝑠𝑔𝑛 (𝑠𝑖𝑛2𝜋

𝑇𝑜𝑡)

𝑅𝑖𝐻𝑆

2𝑟𝑇 (5.23)

Substituting (5.22) and (5.23) into (3.15), the operation required volt-ampere rating for SM

stacks with the proposed near-square-wave modulation is expressed in (5.24).


𝑅𝑆𝑆𝑇−𝑠𝑞𝑤𝑠 =𝑅2 + 4𝑅𝑟𝑇 + 4𝑟𝑇

2

𝑅𝑟𝑇 (5.24)

The maximum voltage and current on secondary-side rectifiers with the near-square-wave

operation are expressed in (5.25) and (5.26) respectively, and their operation required volt-

ampere rating is given in (5.27). It is assumed here the rectifiers are implemented with

controllable devices in order to have a fair calculation together with the SM stacks.

𝑣𝑆1−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑣𝑆2−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑣𝑆3−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑣𝑆4−𝑠𝑞𝑤𝑚𝑎𝑥 =𝑣𝐻𝑆

𝑅 (5.25)

𝑖𝑆1−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑖𝑆2−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑖𝑆3−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑖𝑆4−𝑠𝑞𝑤𝑚𝑎𝑥 = 𝑅𝑖𝐻𝑆 (5.26)

𝑅𝑆𝑆1−𝑠𝑞𝑤 = 𝑅𝑆𝑆2−𝑠𝑞𝑤 = 𝑅𝑆𝑆3−𝑠𝑞𝑤 = 𝑅𝑆𝑆4−𝑠𝑞𝑤 = 1 (5.27)

So, the overall required volt-ampere rating (including both SM stacks and rectifiers) with the

near-square-wave modulation is obtained in (5.28).

𝑅𝑆𝑆𝑇−𝑠𝑞𝑤 = 𝑅𝑆𝑆𝑇−𝑠𝑞𝑤𝑠 + 4𝑅𝑆𝑆1−𝑠𝑞𝑤 =𝑅2 + 8𝑅𝑟𝑇 + 4𝑟𝑇

2

𝑅𝑟𝑇 (5.28)

If this converter is implemented with the traditional single-phase sinusoidal modulation, the

stack voltage and current expressions are given in (5.29) and (5.30), and the maximum rectifier

voltage and current are presented in (5.31) and (5.32). Thus, the operation required volt-ampere

rating is provided in (5.33).

𝑣𝑆𝑇𝑇,𝑆𝑇𝐵−𝑠𝑖𝑛(𝑡) =𝑣𝐻𝑆

2∓


𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡 (5.29)

𝑖𝑆𝑇𝑇,𝑆𝑇𝐵−𝑠𝑖𝑛(𝑡) = 𝑖𝐻𝑆 ±𝑅𝑖𝐻𝑆

𝑟𝑇𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡 (5.30)

𝑣𝑆1−𝑠𝑖𝑛𝑚𝑎𝑥 = 𝑣𝑆2−𝑠𝑖𝑛𝑚𝑎𝑥 = 𝑣𝑆3−𝑠𝑖𝑛𝑚𝑎𝑥 = 𝑣𝑆4−𝑠𝑖𝑛𝑚𝑎𝑥 =𝑣𝐻𝑆

𝑅 (5.31)


𝑖𝑆1−𝑠𝑖𝑛𝑚𝑎𝑥 = 𝑖𝑆2−𝑠𝑖𝑛𝑚𝑎𝑥 = 𝑖𝑆3−𝑠𝑖𝑛𝑚𝑎𝑥 = 𝑖𝑆4−𝑠𝑖𝑛𝑚𝑎𝑥 = 2𝑅𝑖𝐻𝑆 (5.32)

𝑅𝑆𝑆𝑇−𝑠𝑖𝑛 =2𝑅2 + 14𝑅𝑟𝑇 + 4𝑟𝑇

2

𝑅𝑟𝑇 (5.33)

The comparison results between the proposed near-square-wave modulation and traditional

sinusoidal modulation are shown in Figure 5.7. Since the transformer turns-ratio value 𝑟𝑇 has

almost the same effect for these two modulation schemes, it has been set as 1 in the comparison.

The result indicates that the near-square-wave scheme has a clear advantage over the sinusoidal

operation because the root-means-square (RMS) values of voltage and current in sinusoidal

operation that set the power are both a factor of √2 less than the maximum values which are

used in near-square-wave operation for power calculation.


This advantage could reduce semiconductor cost in the practical high step-ratio interconnection

between an HVDC terminal and an MVDC network, but it also needs to note that this benefit

would be partially offset by the need for about 15% extra power devices in the SM stack to

create the control headroom for the rapid reversal of the near-square-wave current.

Step-Ratio R

Ope

ratio

n R

equi

red

Vol

t-am

pere

Rat

ing

RS S

T

6 107 8 9

RSST-sqw

RSST-sin

25

12.5

50

0

37.5


5.4.1.2 Stack Capacitive Energy Storage

Based on the analysis in (3.30), the operation required capacitive energy storage of this high

step-ratio modular multilevel dc-ac-dc converter can be expressed in (5.34).

𝑅𝐸𝑆𝑇 =1

4𝛾(𝑚𝑎𝑥

∆𝐸𝑆𝑇𝑇


∆𝐸𝑆𝑇𝑇

𝑃𝑇) +

1

4𝛿(𝑚𝑎𝑥

∆𝐸𝑆𝑇𝐵


∆𝐸𝑆𝑇𝐵

𝑃𝑇)

=1

4𝛾(𝑚𝑎𝑥

2∆𝐸𝑆𝑇𝑇


2∆𝐸𝑆𝑇𝑇

𝑃𝑇) (5.34)

With (5.22) and (5.23), the time-domain expression of the SM stack energy deviation with the

proposed near-square-wave operation is obtained in (5.35), and the deviation expression with

the traditional sinusoidal operation is given in (5.36).

2∆𝐸𝑆𝑇𝑇−𝑠𝑞𝑤

𝑃𝑇=

2

𝑣𝐻𝑆𝑖𝐻𝑆∫ [

𝑣𝐻𝑆

2− 𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡)


𝑅] [𝑖𝐻𝑆 + 𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡)

𝑅𝑖𝐻𝑆

2𝑟𝑇] 𝑑𝑡

𝑡

0

= ∫ [1 − 𝑠𝑔𝑛 (𝑠𝑖𝑛2𝜋

𝑇𝑜𝑡)

2𝑟𝑇

𝑅] [1 + 𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡)

𝑅

2𝑟𝑇] 𝑑𝑡

𝑡

0

(5.35)

2∆𝐸𝑆𝑇𝑇−𝑠𝑖𝑛

𝑃𝑇=

2


𝑣𝐻𝑆

2−


𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡) (𝑖𝐻𝑆 +

𝑅𝑖𝐻𝑆


2𝜋

𝑇𝑜𝑡) 𝑑𝑡

𝑡

0

= ∫ (1 −2𝑟𝑇

𝑅𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡) (1 +

𝑅


2𝜋

𝑇𝑜𝑡) 𝑑𝑡

𝑡

0

(5.36)

The comparison results of these two modulation schemes for various high step-ratio values

(𝑅 = 10 and 𝑅 = 5) with operation frequency 𝑓𝑜 = 50 Hz and maximum ripple 𝛾 = 10% are

shown in Figure 5.8. The waveforms for near-square-wave operation are seen to be isosceles

triangles with their peaks occurring mid cycle, and its maximum value is a clearly smaller value

than that in sinusoidal operation, which means that the physical volume and cost for SM

capacitors with square-wave-operation modulation would be also less than that with sinusoidal

scheme.



with different modulation schemes ( 𝑟𝑇 = 1, 𝑓𝑜 = 50 Hz, 𝛾 = 10%,𝑅𝐶𝐸−𝑠𝑞𝑤 ≈ 118 kJ/MVA for 𝑅 =

10, 𝑅𝐶𝐸−𝑠𝑞𝑤 ≈ 51 kJ/MVA for 𝑅 = 5, 𝑅𝐸𝑆𝑇−𝑠𝑖𝑛 ≈ 155 kJ/MVA for 𝑅 = 10, 𝑅𝐸𝑆𝑇−𝑠𝑖𝑛 ≈ 75 kJ/

MVA for 𝑅 = 5).


with different operation frequencies ( 𝑟𝑇 = 1, 𝛾 = 10%,𝑅𝐸𝑆𝑇−𝑠𝑞𝑤 ≈ 11.8 kJ/MVA for 𝑅 =

10 and 𝑓𝑜 = 500 Hz, 𝑅𝐸𝑆𝑇−𝑠𝑞𝑤 ≈ 5.1 kJ/MVA for 𝑅 = 5 and 𝑓𝑜 = 500 Hz).

In the meantime, because the ac stage is entirely internal to the converter, the operation

frequency can be increased to 250–500 Hz [87], [88] for a further reduction in volume and

weight of the SM capacitors. As Figure 5.9 shows, the stack energy deviations for 500 Hz

Stac

k E

nerg

y D

evia

tion

(kJ/

MV

A)

Time (ms)0 4 8 12 16 20

70

50

30

10

-10, R = 5

, R = 5

, R = 10

, R = 10

2ΔESTT-sqw/PT 2ΔESTT-sqw/PT

2ΔESTT-sin/PT 2ΔESTT-sin/PT

Stac

k E

nerg

y D

evia

tion

(kJ/

MV

A)

Time (ms)0 4 8 12 16 20

70

50

30

10

-10

, R = 10fo =50 Hz, R = 5fo =50 Hz

, R = 10fo =500 Hz, R = 5fo =500 Hz


operation (𝑓𝑜 = 500 Hz) are, as expected, ten times smaller for 50 Hz operation, and the

required stack capacitive energy storage is about 11.8 kJ/MVA for the case of 𝑅 = 10 and 5.1

kJ/MVA for the case of 𝑅 = 5, which are much smaller than that in standard transformer-

coupled three-phase or single-phase front-to-front configuration when operated with the same

step-ratio and ac frequency, shown in Figure 3.9. Furthermore, this converter is a single-phase

half-bridge configuration with only one phase SM stack in the system and so the total space

occupied by providing isolation distances between SM stacks would be significantly smaller

than three-phase or single-phase full-bridge configuration. In addition, this 500 Hz medium

frequency operation would also benefit other passive components volume in the conversion

system, such as the internal transformer, arm inductors and dc link capacitors. The operation

frequency could be also pushed higher [203], [204] for some specific applications but switching

losses and transformer limitations need to be considered.

5.4.2 DC Link Capacitor Sizing

The voltage and current for high-voltage side dc link capacitor 𝐶𝑇 and 𝐶𝐵 are given in (5.37)

and (5.38), and the energy deviations for 𝐶𝑇 and 𝐶𝐵 are expressed in (5.39).

𝑣𝐶𝑇,𝐶𝐵(𝑡) =𝑣𝐻𝑆

2 (5.37)

𝑖𝐶𝑇,𝐶𝐵(𝑡) = ∓𝑠𝑔𝑛 (𝑠𝑖𝑛2𝜋

𝑇𝑜𝑡)

𝑅𝑖𝐻𝑆

2𝑟𝑇 (5.38)

∆𝐸𝐶𝑇,𝐶𝐵

𝑃𝑇=

1

𝑣𝐻𝑆𝑖𝐻𝑆∫

𝑣𝐻𝑆

2[∓𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡)

𝑅𝑖𝐻𝑆

2𝑟𝑇] 𝑑𝑡 = ∓

1

2∫ 𝑠𝑔𝑛 (𝑠𝑖𝑛

2𝜋

𝑇𝑜𝑡)

𝑅

2𝑟𝑇𝑑𝑡

𝑡

0

𝑡

0

(5.39)

The energy deviation waveforms for 𝐶𝑇 and 𝐶𝐵 are plotted in Figure 5.10, and the results are

similar to those of the stacks but with the deviations in the opposite sense. Near-square-wave

operation is also advantageous in achieving a small energy deviation and small capacitor stack

for 𝐶𝑇 and 𝐶𝐵 compared to the sinusoidal operation.


On the low-voltage side, the instantaneous power flow is near-constant because of the near-

square-wave current operation in this single-phase converter, so the required capacitance value

and physical volume of 𝐶𝐿 can be very small since it needs only absorb the ripple arising from

the imperfect square-wave current transitions.

Figure 5.10. DC link capacitor energy deviation (𝑟𝑇 = 1, 𝑓𝑜 = 500 Hz).

5.4.3 Wide Step-Ratio Range in Operation

The step-ratio of this converter is achieved by combination of the inherent ratio of 2 of the half-

bridge configuration, the stack modulation and transformer turns-ratio. This combination gives

this converter flexibility in design and operation to meet a wide range of requirements, and this

dc-ac-dc conversion process also provides this converter with dc fault management.

Starting from the voltage relationships in (5.1) and (5.2), the overall step-ratio can be derived

in (5.40), where 𝑟𝑆 = 𝑣𝐻𝑆/2𝑣𝑁1 , known as the stack modulation ratio, sets the voltage

conversion achieved within the SM stack itself.

𝑅 =𝑣𝐻𝑆

𝑣𝐿𝑆= 2𝑟𝑆𝑟𝑇 =

2(𝑛𝑇−𝑙𝑎𝑟 + 𝑛𝑇−𝑠𝑚𝑎)

𝑛𝑇−𝑙𝑎𝑟 − 𝑛𝑇−𝑠𝑚𝑎∙ 𝑟𝑇 (5.40)

The minimum and maximum values of (5.40) that can be achieved for a given number of SMs

and a given control headroom are presented in (5.41) and (5.42).

Time (ms)

Ene

rgy

Dev

iatio

n (k

J/M

VA

)

0.0 0.4 0.8 1.2 1.6 2.0

3.6

2.4

0

-2.4

-3.6, R = 5ΔECT/PT

, R = 10 ΔECB/PT

, R = 10 ΔECT/PT

, R = 5ΔECB/PT

1.2

-1.2


𝑅𝑚𝑖𝑛 =2(𝑛𝑇−𝑙𝑎𝑟 + 1)

𝑛𝑇−𝑙𝑎𝑟 − 1∙ 𝑟𝑇 =

2[(1 − 𝐶ℎ)𝑁 + 2]

(1 − 𝐶ℎ)𝑁 − 2∙ 𝑟𝑇 (5.41)

𝑅𝑚𝑎𝑥 = 2(2𝑛𝑇−𝑙𝑎𝑟 − 1) ∙ 𝑟𝑇 = 2[(1 − 𝐶ℎ)𝑁 − 1] ∙ 𝑟𝑇 (5.42)

During the design process, the ratio between 𝑟𝑆 and 𝑟𝑇 can be adjusted to achieve various

optimal objectives such as minimizing the physical volume, maximizing efficiency or reducing

total cost. To illustrate the flexibility during operation the range of the minimum and maximum

𝑅 with a turns-ratio of 1 are plotted in Figure 5.11 with various choices of control headroom

value. Varying the combinations for 𝑛𝑇−𝑠𝑚𝑎 and 𝑛𝑇−𝑙𝑎𝑟 makes available 𝑁(𝑁 − 2)/4 choices

of step-ratio which for converters with tens or hundreds of SMs gives a large degree of

operational flexibility.

Figure 5.11. Step-ratio range (𝑟𝑇 = 1).

5.4.4 Soft-Switching Operation

Analysis of the current-reversal stages (Stage 2 and Stage 5 in Section 5.2) has shown that the

rectifier current can be reduced to zero before the commutation happens so that zero-current-

switching (ZCS) turn-off operation can be achieved for all the rectifier diodes. For Stage 3 and

Stage 6 where the new current is established by turning on the alternate diodes, soft-switching

operation is obtained inherently since rectifier diodes have the natural zero-voltage-switching

Step

-Rat

io R

ange

(R)

25

100

50

75

125

5 20 35 50 65 80

150

SM Number (N)

Rmax Ch=0.10Rmax Ch=0.15 Rmax Ch=0.20 Rmin Ch=0.10 Rmin Ch=0.15 Rmin Ch=0.20

0


(ZVS) capability. In the case where the rectifier is formed by active devices, both ZVS turn-on

and ZCS turn-off operation can still be achieved when the power flow is from the high-voltage

side to the low-voltage side. If the power flow is reversed, ZCS turn-off capability is maintained

by the control scheme but ZVS turn-on may not be possible in all situations.

5.4.5 Challenges and Limitations

This high step-ratio modular multilevel dc-ac-dc converter with near-square-wave current

modulation also faces some operational challenges and limitations, and so some precaution

managements and adjustments should be considered before the practical applications.

First, the high-side dc link capacitor of this converter may bring about fault current in the event

of a dc-side fault, but it is also worth noting that the fault current caused by the dc link capacitor

will not go through any power device of this converter, which is different from the situation in

classic two-level dc-ac converter or MMC dc-ac converter. It could allow for using slow

protection means [205], [206] to deal with the dc fault event, and this is inevitable in most

medium-voltage and high-voltage converters for multi-terminal dc network applications. In the

meantime, the dc link capacitance in this converter can be relatively small thanks to the near-

square-wave current modulation and medium frequency operation, and so the energy stored in

these capacitors can keep at a small value to reduce the negative effect in the dc fault event.

Second, the near-square-wave current modulation can pose challenges in transformer design of

this converter. The main application case for this converter would be a dc tap between an

HVDC terminal and an MVDC network, and so the overall step-ratio should be very high and

the power throughput is expected to be less than 10% of the transmission link power [96], [98],

[207]. For this application, the transformer power rating and voltage rating (less than 30 kV)

will be much smaller than that in the front-to-front configuration for interconnecting two

different HVDC terminals (more than 400 kV) [101], [103], [181]. Although the near-square-

wave operation will create difficulty on transformers, the benefits of reduced conversion

volume and higher power utilisation have stimulated rapid development in transformer design

in recent years, including the optimization of core/winding material and structure [208]–[210].

A laboratory prototype of medium frequency and medium voltage near-square-wave

5.5 Assessment of Simulation Analysis 165

transformer is newly announced up to 7.5 MW demonstration [211]. Alternatively, the

experience and technology of small 𝑑𝑣/𝑑𝑡 filter, which has been widely used in high-power

medium voltage motor drives [212], [213], could be also utilised here in practical

considerations. Lastly, as analyzed in Section 5.2, the inserted SM number in transient stages

and transient waveform are both adjustable according to different conversion requirements in

practical applications. For low step-ratio high power throughput application cases, the

trapezoidal or triangle voltage modulation [178], [180] can be also implemented in the stacks

of this converter as the preferred choice to fulfil this specific conversion.

5.5 Assessment of Simulation Analysis

This section presents a set of full-scale simulations of this high step-ratio modular multilevel

dc-ac-dc converter with near-square-wave current operation to validate the theoretical analysis

and explore an application example of making a connection between HVDC and MVDC.

Redrawing the multi-voltage network of Figure 1.11 for illustration in Figure 5.12, this

converter can play the interface role to realise the interconnection between an HVDC terminal

and an MVDC network, shown as the pink boxes of Figure 5.12.

Figure 5.12. Multi-voltage dc network with HVDC and MVDC infrastructures.

The converter is rated at 30 MW for conversion between a 300 kV HVDC and a 30 kV MVDC.

The SMs in high-voltage side have a reference voltage of 1.8 kV. Control headroom of 18% is

Low Step-Ratio High Power Rating

DC-DC

Low Step-Ratio High Power Rating

DC-DC

AC-DC

AC-DC

DC-AC

DC-AC

HVAC Grid

HVAC Grid

HVAC Grid

HVAC Grid

MVDC Collection

Multi-voltage DC Network with HVDC and MVDC infrastructures

MVDC Distribution

High Step-Ratio Low Power rating

DC-DC

High Step-Ratio Low Power Rating

DC-DC

300-500 kV 10-30 kV

10-30 kV 300-500 kV

10-30 kV

10-30 kV


provided and therefore 144 SMs are used in each stack. In the low-voltage side, diodes are

series connected to support 𝑣𝐿𝑆. The operation frequency is set at 500 Hz as a trade-off between

the physical volume and the power losses. As an illustration, the overall step-ratio of 10:1 is

composed of the inherent ratio of 2:1 of the half-bridge, a stack modulation ratio of 5:2 and a

transformer turns-ratio of 2:1. The simulation parameters for this example are summarised in

Table 5.1. The stack configuration has implemented a compact design, in which the normalised

semiconductor volt-ampere rating 𝑆𝑆𝑇 is 46.5 (including both SM stack and rectifiers) and the

SM capacitive energy storage 𝐸𝑆𝑇 is 15.5 kJ/MVA.

Table 5.1. Simulation parameters of the high step-ratio modular multilevel dc-ac-dc converter


𝑃𝑇 Power Throughput 30 MW

𝑣𝐻𝑆 High-side Terminal Voltage 300 kV (±150 kV)

𝑣𝐿𝑆 Low-side Terminal Voltage 30 kV

𝐿𝑇 𝐿𝐵 Arm Inductance 1.2 mH


𝐶ℎ Control Headroom 18%

𝑛𝑇 𝑛𝐵 SM Number in Each Stack 144

𝐶𝑆𝑀 SM Capacitance 1.0 mF


𝑟𝑠 Stack Modulation Ratio 5:2

𝑓𝑜 Operation Frequency 500 Hz

𝑓𝑟 SM Sorting Frequency 9.7 rot/cycle


𝑆

Power Switches Selected Type MITSUBISHI CM1200HA-66H





5.5.1 Near-square-wave and Soft-switching

Simulation results for stack voltages and currents are shown in Figure 5.13. In Figure 5.13 (a)

and Figure 5.13 (a), it can be seen that both stack voltages and currents are near-square-waves

with dc offsets as expected from (5.1)–(5.5). The top stack voltage in positive steady state

(Stage 1) is about 90 kV and its current is about 350 A while the bottom stack voltage is around

210 kV and its current is around -150 A. The negative steady state (Stage 4) is symmetrical to

the positive steady state with the top stack and bottom stack values replacing each other. Figure

5.13 (c) and Figure 5.13 (d) show one operation cycle in more detail and illustrates the use of

the control headroom to commutate the stack currents and synchronize them with the stack

voltages. The modulation scheme implemented in this full-scale simulation is a classic NLM

with SM voltage sorting and selection algorithm, illustrated in Figure 5.6. Since there is a large

number of SMs in the stack, the voltage error between 𝑣𝑆𝑇𝑇,𝑆𝑇𝐵∗ and 𝑁𝑁𝐿𝑀𝑣𝐶

∗ is negligible

compared to the relatively large value of 𝑣𝑆𝑇𝑇,𝑆𝑇𝐵∗ , and NLM is accurate enough for tracking.

The ripples in Figure 5.13 are caused by SM sorting and selection.

(a)

(b)


(c)

(d)

Figure 5.13. Simulation results of the stack voltage and current. (a) Stack voltages 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵. (a)

Stack currents 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵 . (c) Stack voltages in one operation cycle. (d) Stack currents in one

operation cycle.

The rectifier waveforms in Figure 5.14 (a) and Figure 5.14 (b) show that the near-square-wave

current from the high-voltage side is rectified and appears in the low-voltage terminal as a near-

continuous current with brief dips toward zero.

(a)


(b)

(c)

(d)

Figure 5.14. Simulation results of the rectifier voltage and current. (a) Rectifier voltages 𝑣𝐷1𝑆 and 𝑖𝐷1𝑆.

(a) Rectifier currents 𝑖𝐷1𝑆 and 𝑖𝐷3𝑆. (c) Rectifier voltages in one operation cycle. (d) Rectifier currents

in one operation cycle.

In Figure 5.14 (c) and Figure 5.14 (d), it can be observed that the diodes that are being

commutated off have currents that drop to zero before their voltage enters reverse-bias and that

those turning on have currents that rise after their voltage reaches forward-bias. Both ZCS turn-

off and ZVS turn-on are achieved in this example.


5.5.2 Energy Management and Voltage Balancing

The efficacy of the energy balancing is examined in Figure 5.15. Figure 5.15 (a) shows that the

high-side dc link capacitor voltages 𝑣𝐶𝑇 and 𝑣𝐶𝐵 are well-balanced within 5% of the nominal

value with only 60 μF capacitance on the dc link. It would be possible to further reduce the

voltage deviation range and dc link capacitance if additional control headroom is provided

allowing the rate-of-change of current during commutation to be increased. The maximum,

mean and minimum voltage values of the SM capacitors in each stack are shown in Figure 5.15

(b) and Figure 5.15 (c). It can be seen that the set of SM capacitor voltages are well-controlled

and all are within 10% of the nominal value of 1.8 kV.

(a)

(b)


(c)

Figure 5.15. Simulation results of the energy balance. (a) Voltage deviation of high-side dc link

capacitors, 𝑣𝐶𝑇 and 𝑣𝐶𝐵. (b) Voltage deviation of SM capacitors in top stack, 𝑣𝐶−𝑇−𝑚𝑎𝑥 , 𝑣𝐶−𝑇−𝑚𝑒𝑎𝑛

and 𝑣𝐶−𝑇−𝑚𝑖𝑛. (c) Voltage deviation of SM capacitors in bottom stack, 𝑣𝐶−𝐵−𝑚𝑎𝑥, 𝑣𝐶−𝐵−𝑚𝑒𝑎𝑛 and

𝑣𝐶−𝐵−𝑚𝑖𝑛.

5.5.3 Reversal Power Flow Operation

As mentioned in Section 5.2, this converter can pass power in the reverse direction if the low-

voltage side rectifier diodes are replaced by IGBTs. Results for reverse power flow results are

shown in Figure 5.16. The dc offset and ac component of stack voltages in Figure 5.16 (a) are

identical to those in Figure 5.13 (a), but the dc and ac components of stack currents in Figure

5.16 (b) have changed direction comparing to Figure 5.13 (b).

(a)


(b)

Figure 5.16. Simulation results of the stack voltage and current in reverse power flow. (a) Stack voltages

𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵. (a) Stack currents 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵.


To validate the theoretical analysis and support the simulation results, a down-scaled laboratory

prototype (see Figure A.3 in Appendix) was built with the parameters listed in Table 5.2.

Table 5.2. Experimental prototype parameters of the high step-ratio dc-ac-dc converter


𝑃𝑇 Power Throughput 4.5 kW

𝑣𝐻𝑆 High-side Terminal Voltage 1500 V (±750 V)

𝑣𝐿𝑆 Low-side Terminal Voltage 150 V

𝐿𝑇 𝐿𝐵 Arm Inductance 1.64 mH


𝐶ℎ Control Headroom 22%

𝑛𝑇 𝑛𝐵 SM Number in Each Stack 9

𝐶𝑆𝑀 SM Capacitance 0.8 mF with ±10% variation


𝑟𝑠 Stack Modulation Ratio 5/2

𝑓𝑜 Operation Frequency 500 Hz

𝑓𝑟 SM Sorting Frequency 15.2 rot/cycle


It chooses real-time system OP5600 from OPAL-RT Technologies as the controller, and it

utilises MITSUBISHI IGBT modules CM300DX-24S as the SM power switches. The volt-

ampere ratings of power devices are also oversized in this prototype, but the maximum stack

capacitive energy storage in the full range operation is restricted at about 35 kJ/MVA, which

is in the reasonable margin of the theoretical value in Section 5.4.1 and simulation parameters

in Section 5.5.

Noting that there are only 9 SMs in each stack, the nearest level modulation (NLM) is not

sufficient for accurate tracking and so additional pulse width modulation (PWM) is applied to

one extra SM which will be the 𝑁𝑁𝐿𝑀 + 1 SM in the voltage order. It provides the voltage

difference between 𝑣𝑆𝑇𝑇,𝑆𝑇𝐵∗ and 𝑁𝑁𝐿𝑀𝑣𝐶

∗ .

5.6.1 Near-square-wave and Soft-switching

Experimental result in Figure 5.17 (a) shows the stack voltage and current are both, as expected,

near-square-wave with dc offset of 𝑣𝐻𝑆/2 and 𝑖𝐻𝑆 respectively. The high frequency ripple that

can be seen is the result of PWM of the 𝑁𝑁𝐿𝑀 + 1 SM. Figure 5.17 (b) demonstrates the use of

control headroom to create voltage pulses across the arm inductors which force the stack

current commutation and reduce the transition time. The rectifier waveforms in Figure 5.17 (c)

show the positive-biased square-wave voltage and current after the rectification, which leads

to a near-continuous current on the low-side dc link. In the meantime, it can be also observed

that the ZVS turn-on and ZCS turn-off are also achieved in this experimental operation.

(a)

vSTB(500V/div)

vSTT(500V/div)

iSTB(10A/div)

iSTT(10A/div)

500 μs/div


(b)

(c)

Figure 5.17. Experimental results of the SM stack, arm inductor and rectifier voltages and currents. (a)

Stack voltages and currents, 𝑣𝑆𝑇𝑇,𝑆𝑇𝐵 and 𝑖𝑆𝑇𝑇,𝑆𝑇𝐵. (b) Arm inductor voltages and currents, 𝑣𝐿𝑇,𝐿𝐵 and

𝑖𝐿𝑇,𝐿𝐵. (c) Rectifier voltages and currents, 𝑣𝐷1,𝐷3 and 𝑖𝐷1,𝐷3.

5.6.2 Energy Management and Voltage Balancing

To illustrate the energy balancing results, the voltages and currents at both terminals are shown

in Figure 5.18 (a) and the average voltages of each SM capacitor during ten operation cycles

are summarised in Figure 5.18 (b). The voltages across CT and CB, in Figure 5.18 (a), are seen

to be well-balanced at 750 V. It also verifies the voltage step-ratio in this test is 10:1 and current

vLT(1000V/div)

vLB(1000V/div)

iSTB(10A/div)

iSTT(10A/div)

500 μs/div

vD1(100V/div)

vD3(100V/div)

iD1(20A/div)

iD3(20A/div)

500 μs/div


ratio between two terminals is 1:10. The average voltages for each SM capacitor in Figure 5.18

(b) confirm that the balancing is within 10% of the nominal value of 150 V.

(a)

(b)

Figure 5.18. Experimental results of the energy balance. (a) Voltage and current at both terminals,

𝑣𝐻𝑆,𝐿𝑆 and 𝑖𝐻𝑆,𝐿𝑆. (b) Average voltages of each SM capacitors during ten operation cycles.

vCT(1000V/div)

vCB(1000V/div)

iHS(5A/div)

vLS(100V/div)

iLS(20A/div)


5.6.3 CSM Operation and VSM Operation

To illustrate current source mode operation, the low-voltage terminal was connected to a

voltage source (set variously at 150V, 225 V and 300 V), and the circuit is controlled by the

current loop of Figure 5.6. By adjusting the current references, the power absorbed by the low-

voltage terminal was varied as shown in Figure 5.19 (a).

(a)

(b)

Figure 5.19. Experimental results of different operation schemes. (a) Current-source-mode operation.

(b) Voltage-source-mode operation.


To illustrate voltage source mode operation, a variable resistor was connected to the low-

voltage side and the outer voltage loop of Figure 5.6 was employed. Figure 5.19 (b) shows that

𝑣𝐿𝑆 was well-controlled at steady values (voltage reference set variously at 150 V, 225 V and

300 V) as the variable resistor was changed from light to heavy load.

These experimental results in Figure 5.17–Figure 5.19 reach good agreement with the

theoretical analysis in Section 5.2 and further validate the simulation results in Section 5.5.

5.7 Chapter Summary

This chapter has presented a single-phase modular multilevel dc-ac-dc converter for high step-

ratio low power throughput conversion between an HVDC terminal and an MVDC network.

This topology can be seen as a SAB/DAB dc-ac-dc converter using modular multilevel

structure. High step-ratio was achieved by a combination of the inherent ratio of 2 of the half-

bridge configuration, the SM stack modulation and transformer turn-ratio thereby giving a high

degree of design and operation flexibility. It has shown that this converter inherits the benefits

of medium-frequency operation and soft-switching operation from the original SAB/DAB

circuits which facilitate the reduction of system footprint and power losses, and it also inherits

the features of high modularity, high reliability and high controllability from the MMC

structure that are important for HVDC applications.

The high-voltage side circuit is a single-phase half-bridge inverter with stacks of SMs in each

of the switch positions to withstand the high-side voltage stress. The high-voltage side

processes all the power through only two SM stacks, so the total volume required by SM stacks

and isolation clearances can be kept low. The low-voltage side can use a diode or active bridge

rectifier arrangement for unidirectional or bidirectional power flow, simplifying the

configuration and also achieving soft-switching operation. Compactness is further advanced

by using near-square-wave current operation which has been shown to yield a lower rating

requirement for semiconductor devices and SM capacitors than traditional sinusoidal

operation. The near-square-wave current operation in single-phase configuration leads to near-

constant instantaneous power flow such that the dc smoothing capacitors can be also very

small. An energy balance method and a control strategy for this mode of operation were also


proposed. The rapid current reversal required for near-square-wave operation was aided by

providing control headroom in the form of additional SM over those required for steady-state.

The theoretical analysis for operating principles and near-square-wave modulation is verified

against simulations of a full-scale example and further verified against experiments on a down-

scaled prototype. The results show that this high step-ratio modular multilevel dc-ac-dc

converter with near-square-wave operation could become a compact and low-cost candidate

for power connection between an HVDC terminal and an MVDC network.

Chapter 6 Low Step-ratio Modular Multilevel DC-

DC Converter for HVDC Applications

The previous chapter (Chapter 5) discussed the high step-ratio modular multilevel dc-ac-dc

converter to connect an HVDC terminal to an MVDC network. The internal ac stage provided

the converter with the benefit of using a transformer and its turns-ratio to decrease the burden

on stack modulation ratio and thereby achieve high step-ratio conversion. However, this multi-

stage conversion would invariably increase the overall cost, power losses and system footprint

since the converter needs two separate steps (ac-dc and dc-ac) to accomplish the dc-dc

conversion.

This chapter presents a buck-boost circuit based single-stage direct-chain-link modular

multilevel dc-dc converter which is suitable for low step-ratio high power throughput

conversion between two dc terminals with similar but not identical voltages. To introduce the

topology and operation of this direct-chain-link dc-dc converter, its connection to and

comparison with the standard single-phase dc-ac MMC are described in Section 6.1.

As noted in Section 2.3.2, all of the direct-chain-link modular multilevel dc-dc configurations

[176], [184] rely on an internal-circulating ac current to balance the stack energies and this

circulating current inevitably adds to the current amplitude stresses and power losses for both

the SM switches and passive components in the circuit. In Section 6.2, an analysis method is

created to support the choice of the circulating current frequency. Using this, the current

stresses and reactive power losses can be minimised while also meeting the SM stack balancing

requirements and limits on the SM voltage ripple.

The analysis method for the circulating current frequency can be applied to other direct-chain-

link dc-dc converters and derived topologies which covers various conversion requirements,

the detailed description and discussion of which are given in Section 6.3 of this chapter.

180 Low Step-ratio Modular Multilevel DC-DC Converter for HVDC Applications

Simulations and experiments are presented in Section 6.4 and Section 6.5 respectively, the

results of which validate the operation principles of the presented direct-chain-link dc-dc

converter and also verify the analysis method for the choice of circulating current frequency.

6.1 Circuit Operation and Current Loop Analysis

Figure 6.1 shows a standard single-phase dc-ac MMC circuit with a passive ac load placed

centrally [157], [158]. The black arrows define the reference directions of the branch currents,

and the black signs of “+ − ” define the voltage direction. The blue arrow and red arrows

denote the expected loop paths of the dc and ac current.

If the converter is properly controlled, the dc input currents, 𝑖𝑖𝑛𝑇−𝑑𝑐 and 𝑖𝑖𝑛𝐵−𝑑𝑐, flow through

the outer blue loop, 𝐼𝑑𝑐, as a common component for the top and bottom stack currents. The ac

output current, 𝑖𝑜𝑢𝑡−𝑎𝑐, divides into two equal parts, and these two ac components, 𝑖𝑎𝑐

2, flow in

the two red loops and have different directions with respect to the stack current references.

They can be seen as differential stack currents. Since the stack energy must be balanced, the

net energy deviation over an ac cycle, 𝑇𝑎𝑐, caused by the combination of ac and dc voltages

and currents of the stacks should be zero, as expressed in (6.1) and (6.2),

∫ 𝑣𝑆𝑇𝑇(𝑡)𝑖𝑆𝑇𝑇(𝑡)𝑑𝑡𝑇𝑎𝑐

0

= ∫ [𝑉𝑑𝑐 + 𝑣𝑖𝑛𝑇−𝑟𝑖𝑝 − 𝑣𝑎𝑐(𝑡) − 𝑣𝐿𝑇(𝑡)] [𝐼𝑑𝑐 +𝑖𝑎𝑐(𝑡)

2] 𝑑𝑡

𝑇𝑎𝑐

0

= 0 (6.1)

∫ 𝑣𝑆𝑇𝐵(𝑡)𝑖𝑆𝑇𝐵(𝑡)𝑑𝑡𝑇𝑎𝑐

0

= ∫ [𝑉𝑑𝑐 + 𝑣𝑖𝑛𝐵−𝑟𝑖𝑝 + 𝑣𝑎𝑐(𝑡) − 𝑣𝐿𝐵(𝑡)] [𝐼𝑑𝑐 −𝑖𝑎𝑐(𝑡)

2] 𝑑𝑡

𝑇𝑎𝑐

0

= 0 (6.2)

where 𝑣𝑆𝑇𝑇 and 𝑖𝑆𝑇𝑇 are the voltage and current of top stack, 𝑣𝑆𝑇𝐵 and 𝑖𝑆𝑇𝐵 are the voltage and

current of bottom stack, 𝑣𝐿𝑇 and 𝑣𝐿𝐵 are the arm inductor voltage of top stack and bottom stack,

𝑉𝑑𝑐 and 𝐼𝑑𝑐 are the dc component voltage and current from the input dc sources 𝑣𝑖𝑛𝑇 and 𝑣𝑖𝑛𝐵

(𝑣𝑖𝑛𝑇−𝑑𝑐 = 𝑣𝑖𝑛𝐵−𝑑𝑐 = 𝑉𝑑𝑐 , 𝑖𝑖𝑛𝑇−𝑑𝑐 = 𝑖𝑖𝑛𝐵−𝑑𝑐 = 𝐼𝑑𝑐 ), 𝑣𝑖𝑛𝑇−𝑟𝑖𝑝 and 𝑣𝑖𝑛𝐵−𝑟𝑖𝑝 are the small ac

component voltage on the input dc sources 𝑣𝑖𝑛𝑇 and 𝑣𝑖𝑛𝐵 (𝑣𝑖𝑛𝑇−𝑎𝑐 = 𝑣𝑖𝑛𝑇−𝑟𝑖𝑝, 𝑣𝑖𝑛𝐵−𝑎𝑐 =

𝑣𝑖𝑛𝐵−𝑟𝑖𝑝), 𝑣𝑎𝑐 and 𝑖𝑎𝑐 are the ac component voltage (𝑣𝑜𝑢𝑡−𝑎𝑐(𝑡) = 𝑣𝑎𝑐(𝑡) = 𝑉𝑎𝑐 𝑠𝑖𝑛 𝜔𝑡) and

current (𝑖𝑜𝑢𝑡−𝑎𝑐(𝑡) = 𝑖𝑎𝑐(𝑡) = 𝐼𝑎𝑐 𝑠𝑖𝑛(𝜔𝑡 + 𝜃)) through the ac load 𝑍𝑙𝑜𝑎𝑑. 𝑉𝑎𝑐 and 𝐼𝑎𝑐 are the

6.1 Circuit Operation and Current Loop Analysis 181

amplitude value of ac load voltage and current, 𝜔 is the angular frequency of the ac components

(𝜔 = 2𝜋𝑓 =2𝜋

𝑇) and 𝜃 is the phase difference between them. The illustrative waveforms for

these voltages and currents have been also provided in Figure 6.1 at appropriate locations.

Figure 6.1. Current loops in the standard single-phase dc-ac MMC.

Evaluating the dc and ac components of (6.1) and (6.2) leads to (6.3), which is the required

relationship between the ac and dc terms for energy balance. A modulation index 𝑚 has been

defined between 𝑉𝑎𝑐 and 𝑉𝑑𝑐 such that 𝑉𝑎𝑐 = 𝑚𝑉𝑑𝑐 and for half bridge SM stacks 𝑚 ≤ 1.

𝑉𝑑𝑐𝐼𝑑𝑐 =1

4𝑉𝑎𝑐𝐼𝑎𝑐 𝑐𝑜𝑠 𝜃 =

1

4𝑚𝑉𝑑𝑐𝐼𝑎𝑐 𝑐𝑜𝑠 𝜃 (6.3)

This standard single-phase MMC achieves dc-ac conversion. It can be modified and developed

into a modular multilevel dc-dc converter, as shown in Figure 6.2. Here, 𝑣𝑖𝑛𝑇 still serves as the

input dc source voltage, designated as 𝑣𝑖𝑛, but 𝑣𝑖𝑛𝐵 of Figure 6.1 has become the output dc

load voltage, 𝑣𝑜, which leads to the dc current divided into two loops (the blue arrows) with

different directions (with respect to the stack current reference). The voltage step-ratio between

LT

LB

Zload

Idc

vout-ac=vac

vSTB=Vdc+vinB-rip+vac vLB iout-ac=iac

vinT-dc=Vdc

vinT

vinB

vout

SMT1

SMTN

SMB1

SMBN

iinT-dc=Idc

vinT-ac=vinT-rip

vinB-dc=Vdc

iinB-dc=Idc

vinB-ac=vinB-rip

iout-dc=0

vout-dc=0

vout=vac

iac

2

iac

2

vSTT=Vdc+vinT-rip vac vLT

iinT-ac= iac

2iSTT=Idc+

iac

2

iSTB=Idc iac

2iinB-ac=

2iac


the dc component values of 𝑣𝑜 and 𝑣𝑖𝑛 is defined as 𝑅 (𝑅 =𝑣𝑜−𝑑𝑐

𝑣𝑖𝑛−𝑑𝑐, 𝑣𝑖𝑛−𝑑𝑐 = 𝑉𝑑𝑐, 𝑣𝑜−𝑑𝑐 =

𝑉𝑑𝑐𝑅, 𝑣𝑖𝑛−𝑎𝑐 = 𝑣𝑖𝑛−𝑟𝑖𝑝, 𝑣𝑜−𝑎𝑐 = 𝑣𝑜−𝑟𝑖𝑝).

Figure 6.2. Current loops in the proposed modular multilevel dc-dc conversion.

To keep both stacks balanced in the operation, it still needs ac components in the stack voltages

and also an ac current through the stacks. The sum of the stack voltages in conventional dc-ac

MMC conversion only needs to support the dc link voltage stress, but the sum of the stack

voltages in this dc-dc conversion has to support the dc link voltage and also provides an extra

ac voltage to drive a common ac current through the two stacks for energy balancing. This ac

current works with the ac components of the stack voltages to offset the dc net energy in each

ac cycle. The arm inductor voltages 𝑣𝐿𝑇(𝑡) and 𝑣𝐿𝐵(𝑡) in this dc-dc conversion will always

have the same voltage drop directions due to the common ac current, which is different with

that in standard dc-ac MMC conversion. Because of the ac component in stack voltage, the

voltage at middle point of the two stacks, 𝑣𝑓 , is still an ac voltage (𝑣𝑓(𝑡) = 𝑣𝑎𝑐(𝑡) =

𝑉𝑎𝑐 𝑠𝑖𝑛 𝜔𝑡) as that in dc-ac conversion, and term 𝑚 is still used to show the ratio between 𝑉𝑎𝑐

and 𝑉𝑑𝑐. The ac load 𝑍𝑙𝑜𝑎𝑑 in Figure 6.1 becomes an inductive filter 𝐿𝑓 in this dc-dc converter

and is expected to supress ac current in a path that is intended to be dc only.

LT

LB

vf-ac =vac

if-dc =Idc+

Co

Idc

Lf

vin

vo

vf

iSTB= +

iSTT=Idc+

Idc

R

vin-dc=Vdc

iin-dc=Idc

vin-ac=vin-rip

iin-ac=

vo-dc=VdcR

io-dc=

vo-ac=vo-rip

if-ac 0

vf-dc=0

vf=vac

iac

2

iac

2

iac

2

iac

2

io-ac=iac

2Idc

R

Idc

R

Idc

R

vSTB=VdcR+vo-rip+vac vLB

vSTT=Vdc+vin-rip vac vLT SMT1

SMTN

SMB1

SMBN

6.2 Equivalent Circuit and Choice of Frequency 183

Compared to the dc and ac current loops in dc-ac conversion, the roles of dc current and ac

current in this dc-dc conversion have been exchanged. The ac current, designated as 𝑖𝑎𝑐

2, flow

in an outer loop and is common to the top and bottom stacks, whereas there are different dc

currents, 𝐼𝑑𝑐 and 𝐼𝑑𝑐

𝑅, through the two stacks, flowing in opposite direction and returning via the

ground connection. The requirement for energy balance for top and bottom stacks in this dc-dc

conversion are given in (6.4) and (6.5) respectively. The dc and ac components in this dc-dc

conversion also need comply the relationship as (6.3) to keep the both stacks balanced.

∫ 𝑣𝑆𝑇𝑇(𝑡)𝑖𝑆𝑇𝑇(𝑡)𝑑𝑡𝑇𝑎𝑐

0

= ∫ [𝑉𝑑𝑐 + 𝑣𝑖𝑛−𝑟𝑖𝑝 − 𝑣𝑎𝑐(𝑡) − 𝑣𝐿𝑇(𝑡)] [𝐼𝑑𝑐 +𝑖𝑎𝑐(𝑡)

2] 𝑑𝑡 = 0

𝑇𝑎𝑐

0

(6.4)

∫ 𝑣𝑆𝑇𝐵(𝑡)𝑖𝑆𝑇𝐵(𝑡)𝑑𝑡𝑇𝑎𝑐

0

= ∫ [𝑉𝑑𝑐𝑅 + 𝑣𝑜−𝑟𝑖𝑝 + 𝑣𝑎𝑐(𝑡) − 𝑣𝐿𝐵(𝑡)] [−𝐼𝑑𝑐

𝑅+

𝑖𝑎𝑐(𝑡)

2] 𝑑𝑡

𝑇𝑎𝑐

0

= 0 (6.5)

In the case of a dc-ac MMC conversion, the frequency, amplitude and phase of the ac

components of the stack voltages and currents are usually decided by the external utility grid

and power reference. For this dc-dc conversion, there is freedom to choose the amplitude,

frequency and phase of ac components of the stack voltages to suit design purposes. The

amplitude, frequency and phase of the ac current can be set by the choice of the ac components

of the stack voltages (the sum of the two stack voltages) acting on the internal passive

component network. This freedom of choice provides an opportunity, but also raises the

challenge, to manage the component stresses and power losses within this single-stage dc-dc

conversion. To design this dc-dc circuit properly, it requires detailed circuit analysis as

undertaken in next section.

6.2 Equivalent Circuit and Choice of Frequency

The approach taken is to exploit superposition and create separate equivalent circuits to analyse

the dc and ac components of Figure 6.2.


6.2.1 Equivalent circuit of DC Component

Considering the dc components in the first place, the equivalent circuit has much similarity to

an average-value circuit of the classic bidirectional buck-boost converter. A specific dc

component analysis and comparison of the two cases are presented in Figure 6.3. The dc

components of the stack voltages and currents ( 𝑣𝑆𝑇𝑇−𝑑𝑐 = 𝑉𝑑𝑐, 𝑖𝑆𝑇𝑇−𝑑𝑐 = 𝐼𝑑𝑐 , 𝑣𝑆𝑇𝐵−𝑑𝑐 =

𝑉𝑑𝑐𝑅, 𝑖𝑆𝑇𝐵−𝑑𝑐 = −𝐼𝑑𝑐

𝑅) in Figure 6.3 (a) are analogous to the average values of the switch

voltages and currents (𝑣𝑆𝑊𝑇̅̅ ̅̅ ̅̅ = 𝑉𝑑𝑐, 𝑖𝑆𝑊𝑇̅̅ ̅̅ ̅̅ = 𝐼𝑑𝑐, 𝑣𝑆𝑊𝐵̅̅ ̅̅ ̅̅ ̅ = 𝑉𝑑𝑐𝑅, 𝑖𝑆𝑊𝐵̅̅ ̅̅ ̅̅ = −𝐼𝑑𝑐

𝑅) in switch-mode

buck-boost operation. Further, the dc components of the voltage and current of the reactor

(𝑣𝑓−𝑑𝑐 = 0, 𝑖𝑓−𝑑𝑐 = 𝐼𝑑𝑐 +𝐼𝑑𝑐

𝑅) in Figure 6.3 (a) are also analogous to the average values of the

voltage and current of the inductor ( 𝑣𝐿̅̅ ̅ = 0, 𝑖�̅� = 𝐼𝑑𝑐 +𝐼𝑑𝑐

𝑅) in switch-mode buck-boost

operation. Noting that the output voltage is below ground potential, the modular multilevel dc-

dc converter presented in Figure 6.2 is therefore described as a direct-chain-link negative-

output buck-boost converter in this chapter. Its equivalent dc component circuit is shown in

Figure 6.4 (a).

(a) (b)

Figure 6.3. DC component analysis and comparison. (a) Proposed modular multilevel dc-dc converter.

(b) Classic bidirectional buck-boost converter.

Lf

vin

Co

SWT

SWBvo

vin

Covo

STT

STB

vSWT

vSWB

vSTT

vSTB iSTB

iSTT

iSWB

iSWT

Lf

LT

LB


(a) (b)

Figure 6.4. Equivalent circuit analysis of the proposed direct-chain-link negative-output buck-boost

converter. (a) DC components. (b) AC components.

6.2.2 Equivalent circuit of AC Component

Turning now to the ac component of Figure 6.2, the equivalent circuit is shown in Figure 6.4

(b). It can be seen that there is no input ac voltage but the stacks act together and in sum they

will create an ac voltage that drives an ac current around a single loop comprising of the two

arm inductors, 𝐿𝑇 and 𝐿𝐵, and the input and output dc capacitor 𝐶𝑖𝑛 and 𝐶𝑜. This ac current

analysis is illustrated in Figure 6.5 (a) and for comparison the paths in the traditional single-

phase dc-ac MMC are shown in Figure 6.5 (b). The top stack voltage and bottom stack voltage

in dc-ac MMC also need to provide an extra ac voltage (besides 𝑣𝑎𝑐) to generate ac voltages at

points A and B to drive the two ac current components through the arm inductors. These two

ac currents flow with different direction when they go through their respective arm inductor

and SM stack, so the required extra ac voltages for top stack and bottom are opposite and the

sum of them should be 0 (i.e., the voltage difference between A and B is 0), which avoids

creation of internal circulating current. However, the ac current in the case of this dc-dc

LT

LB

vin-ac=vin-rip

= icir

Covo-ac=vo-rip

Lf

LT

LB

Idc

vin-dc=Vdc

Co

Lf

SWT

SWB

vSTT-ac

vSTB-acvo-dc=VdcR

if-dc=iL

vf-dc vf-ac

vf-ac=vac

if-ac 0

iac

2

Idc

R

iSTT-dc=iSWT=Idc

=Idc+ Idc

R

vf-dc=vL=0

vSTT-dc=vSWT=Vdc

vSTB-dc=vSWB=VdcR

iSTB-dc=iSWB= Idc

R


conversion has to circulate within the circuit in order to keep the stack energies balanced, so

the sum of the extra ac voltages of the top and bottom stack in this dc-dc conversion should not

be 0 (i.e., the voltage difference between A and B is not 0). The expression for these two stack

voltages can be expressed in terms of the SM capacitor voltages and modulation ratios. The ac

current, 𝑖𝑎𝑐

2, that flows around the main loop is also referred to as the circulating current (𝑖𝑐𝑖𝑟 =

𝑖𝑎𝑐

2).

(a) (b)

Figure 6.5. AC component analysis and comparison. (a) Direct-chain-link negative-output buck-boost

converter. (b) Standard single-phase dc-ac MMC.

6.2.3 Choice of Circulating Current Frequency

The stack energy expression is presented in (6.6) on the assumption that the term

𝑣𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡)2 is negligible compared to 𝑉𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝐵−𝑑𝑐.

𝑒𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡) = 𝐸𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝐵−𝑑𝑐 + 𝑒𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡)

=𝐶𝑆𝑀

2𝑛𝑇,𝐵𝑣𝑆𝑀𝑇,𝑆𝑀𝐵

2(𝑡) =𝐶𝑆𝑀

2𝑛𝑇,𝐵[𝑉𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝐵−𝑑𝑐 + 𝑣𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡)]

2

≈𝐶𝑆𝑀

2𝑛𝑇,𝐵𝑉𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝑇−𝑑𝑐

2 + 2𝐶𝑆𝑀

2𝑛𝑇,𝐵𝑉𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝑇−𝑑𝑐𝑣𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡) (6.6)

Lf

Co

LT

LB

iac2

vf=vac

vSTB-ac

vSTT-ac

A

B

Cin

LT

LB

Zload

iac2

iac2

vout=vac

vSTB-ac

vSTT-ac

A

B

CinB

CinT


where 𝑒𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡) and 𝑣𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡) are the sum of SM capacitor energy and voltage in top or

bottom stack, 𝐸𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝐵−𝑑𝑐 and 𝑉𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝐵−𝑑𝑐 are the dc components of 𝑒𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡) and

𝑣𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡) , 𝑒𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡) and 𝑣𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡) are the ac components of

𝑒𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡) and 𝑣𝑆𝑀𝑇,𝑆𝑀𝐵(𝑡), 𝐶𝑆𝑀 is the SM individual capacitance and 𝑛𝑇,𝐵 is the number of

SMs in the top or bottom stack.

The ac components of the sum of SM capacitor energy, 𝑒𝑆𝑀𝑇−𝑎𝑐,𝑆𝑀𝐵−𝑎𝑐(𝑡) are related to the

instantaneous power exchange of the stack during the circuit operation, and they can be

expressed as (6.7) and (6.8).

𝑒𝑆𝑀𝑇−𝑎𝑐(𝑡) = ∫ [𝑉𝑑𝑐 + 𝑣𝑖𝑛−𝑟𝑖𝑝 − 𝑣𝑎𝑐(𝑡) − 𝑣𝐿𝑇(𝑡)] [𝐼𝑑𝑐 +𝑖𝑎𝑐(𝑡)

2] 𝑑𝑡

𝑡

0

(6.7)

𝑒𝑆𝑀𝐵−𝑎𝑐(𝑡) = ∫ [𝑉𝑑𝑐𝑅 + 𝑣𝑜−𝑟𝑖𝑝 + 𝑣𝑎𝑐(𝑡) − 𝑣𝐿𝐵(𝑡)] [−𝐼𝑑𝑐

𝑅+

𝑖𝑎𝑐(𝑡)

2] 𝑑𝑡

𝑡

0

(6.8)

Substituting the expression of (6.7) and (6.8) into (6.6), yields the ac components of the sum

of SM capacitor voltage, 𝑣𝑆𝑀𝑇−𝑎𝑐(𝑡) and 𝑣𝑆𝑀𝐵−𝑎𝑐(𝑡), as noted in (6.9) and (6.10) where the

small energy deviation within the passive network has been neglected.

𝑣𝑆𝑀𝑇−𝑎𝑐(𝑡) =𝑛𝑇

𝐶𝑆𝑀𝑉𝑆𝑀𝑇−𝑑𝑐𝑒𝑆𝑀𝑇_𝑎𝑐(𝑡) =

𝑛𝑇𝑉𝑑𝑐𝐼𝑑𝑐

2𝜔𝐶𝑆𝑀𝑉𝑆𝑀𝑇−𝑑𝑐

(4

𝑚𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 𝜔𝑡 +

2𝑚2 − 4

𝑚𝑐𝑜𝑠 𝜔𝑡 + 𝑠𝑖𝑛 2𝜔𝑡 + 𝑡𝑎𝑛 𝜃 𝑐𝑜𝑠 2𝜔𝑡) (6.9)

𝑣𝑆𝑀𝐵−𝑎𝑐(𝑡) =𝑛𝐵

𝐶𝑆𝑀𝑉𝑆𝑀𝐵−𝑑𝑐𝑒𝑆𝑀𝐵−𝑎𝑐(𝑡) =

𝑛𝐵𝑉𝑑𝑐𝐼𝑑𝑐

2𝜔𝐶𝑆𝑀𝑉𝑆𝑀𝐵−𝑑𝑐

(4𝑅


2𝑚2 − 4𝑅

𝑚𝑅𝑐𝑜𝑠 𝜔𝑡 − 𝑠𝑖𝑛 2𝜔𝑡 − 𝑡𝑎𝑛 𝜃 𝑐𝑜𝑠 2𝜔𝑡) (6.10)

The dc components of the sums of the SM capacitor voltages in the top and bottom stacks,

𝑉𝑆𝑀𝑇−𝑑𝑐,𝑆𝑀𝐵−𝑑𝑐, should be sufficient to match the externally imposed dc voltages (𝑉𝑑𝑐in the


top loop and 𝑉𝑑𝑐𝑅 in the bottom loop) and through modulation of the stack create the required

𝑉𝑎𝑐, as shown in (6.11) and (6.12). Terms 𝛿𝑇 and 𝛿𝐵 are defined as the redundancy ratio for the

dc components of stack voltages (𝛿𝑇 ≤ 1, 𝛿𝐵 ≤ 1).

𝛿𝑇𝑉𝑆𝑀𝑇_𝑑𝑐 = 𝑉𝑑𝑐 + 𝑉𝑎𝑐 = (1 + 𝑚)𝑉𝑑𝑐 (6.11)

𝛿𝐵𝑉𝑆𝑀𝑇_𝑑𝑐 = 𝑉𝑑𝑐𝑅 + 𝑉𝑎𝑐 = (𝑅 + 𝑚)𝑉𝑑𝑐 (6.12)

The ratio between 𝑉𝑑𝑐 and 𝑉𝑆𝑀𝑇−𝑑𝑐 and the ratio between 𝑉𝑑𝑐𝑅 and 𝑉𝑆𝑀𝐵−𝑑𝑐 are defined as the

dc modulation index of the SM stacks, noted as 𝑚𝑑𝑐𝑇 and 𝑚𝑑𝑐𝐵, shown in (6.13) and (6.14). It

is also worth noting here that 𝑚 is the ratio between 𝑉𝑎𝑐 and 𝑉𝑑𝑐, which can be seen as the ac

modulation index of the SM stacks.

𝑚𝑑𝑐𝑇 =𝑉𝑑𝑐

𝑉𝑆𝑀𝑇−𝑑𝑐=

𝛿𝑇

1 + 𝑚 (6.13)

𝑚𝑑𝑐𝐵 =𝑉𝑑𝑐𝑅

𝑉𝑆𝑀𝐵−𝑑𝑐=

𝛿𝐵𝑅

𝑅 + 𝑚 (6.14)

Thus, the stack voltages can be expressed in (6.15) and (6.16) by SM stack capacitor voltages

and modulation ratios, and the sum of the ac components of these two stack voltages are given

in (6.17). The relationship between this ac voltage sum and the circulating current shown in

Figure 6.3 (b) is provide in (6.18), and the amplitude of the circulating current is given in (6.19),

where 𝐶𝐷𝐶 is the equivalent dc link capacitance (𝐶𝐷𝐶 =𝐶𝑖𝑛𝐶𝑜

𝐶𝑖𝑛+𝐶𝑜).

𝑣𝑆𝑇𝑇(𝑡) = (𝑚𝑑𝑐𝑇 − 𝑚𝑑𝑐𝑇𝑚 𝑠𝑖𝑛 𝜔𝑡)[𝑉𝑆𝑀𝑇−𝑑𝑐 + 𝑣𝑆𝑀𝑇−𝑎𝑐(𝑡)] (6.15)

𝑣𝑆𝑇𝐵(𝑡) = (𝑚𝑑𝑐𝐵 +𝑚𝑑𝑐𝐵

𝑅𝑚 𝑠𝑖𝑛 𝜔𝑡) [𝑉𝑆𝑀𝐵−𝑑𝑐 + 𝑣𝑆𝑀𝐵−𝑎𝑐(𝑡)] (6.16)

𝑣𝑠𝑢𝑚−𝑎𝑐(𝑡) = 𝑣𝑆𝑇𝑇−𝑎𝑐(𝑡) + 𝑣𝑆𝑇𝐵−𝑎𝑐(𝑡)

= (𝑚𝑑𝑐𝑇 − 𝑚𝑑𝑐𝑇𝑚 𝑠𝑖𝑛 𝜔𝑡)𝑣𝑆𝑀𝑇−𝑎𝑐(𝑡) + (𝑚𝑑𝑐𝐵 +𝑚𝑑𝑐𝐵

𝑅𝑚 𝑠𝑖𝑛 𝜔𝑡) 𝑣𝑆𝑀𝐵−𝑎𝑐(𝑡) (6.17)


𝑖𝑐𝑖𝑟̇ =1

2𝑖𝑎𝑐̇ =

−𝑗𝜔𝐶𝐷𝐶

1 − 𝜔2(𝐿𝑇 + 𝐿𝐵)𝐶𝐷𝐶𝑣𝑠𝑢𝑚−𝑎𝑐̇ (6.18)

𝐼𝑐𝑖𝑟 =1

2𝐼𝑎𝑐 = |

−𝑗𝜔𝐶𝐷𝐶

1 − 𝜔2(𝐿𝑇 + 𝐿𝐵)𝐶𝐷𝐶| ∙ 𝑚𝑎𝑥[𝑣𝑆𝑇𝑇−𝑎𝑐(𝑡) + 𝑣𝑆𝑇𝐵−𝑎𝑐(𝑡)] (6.19)

Substituting the results of (6.9) and (6.10) into (6.17) and (6.19), the general expression for this

circulating current amplitude can be found (as shown (6.25) in the Appendix Section 6.6.1).

Analysis specific to the case of symmetrical voltage conversion without redundancy (𝑣𝑖𝑛−𝑑𝑐 =

𝑣𝑜−𝑑𝑐 = 𝑉𝑑𝑐, 𝑛𝑇,𝐵 = 𝑛𝑎𝑟𝑚, 𝐿𝑇,𝐵 = 𝐿𝑎𝑟𝑚, 𝑚𝑑𝑐𝑇,𝑑𝑐𝐵 =1

1+𝑚) is shown in (6.20) as an example.

𝐼𝑐𝑖𝑟 =1

2𝐼𝑎𝑐 = |

−𝑗𝐶𝐷𝐶𝑛𝑎𝑟𝑚𝐼𝑑𝑐

2𝐶𝑆𝑀(1 − 2𝜔2𝐿𝑎𝑟𝑚𝐶𝐷𝐶)(1 + 𝑚)2|

𝑚𝑎𝑥 (𝑚2 + 8


3𝑚2 − 8

𝑚𝑐𝑜𝑠 𝜔𝑡 + 𝑚 𝑐𝑜𝑠 3𝜔𝑡 − 𝑚 𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 3𝜔𝑡) (6.20)

Considering the effect of harmonics is negligible, (6.20) can be simplified as (6.21), and this

term needs to satisfy the energy balancing condition in (6.3). The required frequency of the

circulating ac current can be determined according to (6.22) (It is also the frequency at which

the SM stacks are modulated).

𝐼𝑐𝑖𝑟 =1

2𝐼𝑎𝑐 =

𝑛𝑎𝑟𝑚𝐼𝑑𝑐𝐶𝐷𝐶

2𝐶𝑆𝑀(2𝜔2𝐿𝑎𝑟𝑚𝐶𝐷𝐶 − 1)(1 + 𝑚)2𝑚∙ 𝐴 (6.21)

𝑓 =𝜔

2𝜋=

1

2𝜋√

1

2𝐿𝑎𝑟𝑚𝐶𝐷𝐶+

𝑛𝑎𝑟𝑚 𝑐𝑜𝑠 𝜃

8𝐿𝑎𝑟𝑚𝐶𝑆𝑀(1 + 𝑚)2∙ 𝐴 (6.22)

where 𝐴 = √(𝑡𝑎𝑛2 𝜃 + 9)𝑚4 + (16 𝑡𝑎𝑛2 𝜃 − 48)𝑚2 + 64 𝑡𝑎𝑛2 𝜃 + 64.

The expression (6.21) has a minimum value which for the case 𝜃 = 0 is expressed in (6.23) in

terms of the passive component values and the voltage modulation index. This minimum occurs

at the frequency given in (6.24).


𝐼𝑐𝑖𝑟−𝑚𝑖𝑛 =𝑛𝑎𝑟𝑚𝐼𝑑𝑐𝐶𝐷𝐶(8 − 3𝑚2)

2𝐶𝑆𝑀(2𝜔2𝐿𝑎𝑟𝑚𝐶𝑜 − 1)(1 + 𝑚)2𝑚 (6.23)

𝑓 =1

2𝜋√

1


𝑛𝑎𝑟𝑚(8 − 3𝑚2)

8𝐿𝑎𝑟𝑚𝐶𝑆𝑀(1 + 𝑚)2 (6.24)

In the design process for this direct-chain-link modular multilevel buck-boost converter, which

is broadly the same as that for the classic dc-ac MMC [199], [200], the SM number will be

chosen based on the dc terminal voltages and SM power device rating and the SM capacitance

will be decided by the allowed capacitor voltage deviation given the stack energy deviation.

However, the arm inductor and dc capacitor values of this dc-dc converter should be chosen

with reference to (6.24) in order to maintain the stack modulation frequency at a relatively low

value, but the choice is also a design trade-off because large values for the arm inductances and

the dc capacitance would increase system footprint (and associated cost) and also bring about

some fault current risk in the event of dc fault.

During the operation phase (once the design is determined), the voltage modulation index

should keep at a high value to decrease the current amplitude and frequency. The modulation

frequency needs to follow the result in (6.24) to achieve the minimum ac current stress and

reactive power losses. A poor choice of frequency could result in a high amplitude of ac current

than that is necessary and this will increase the current stresses and conduction losses for both

the SM switches and the passive components. Also, a deviation of the frequency from the value

of (6.24) can also lead to undesirable reactive power flow around the loop which would further

decrease the overall power efficiency. It should be noted that the ac frequency and modulation

index can both be adjusted during operation to achieve the required variable step-ratio and also

to accommodate circuit parameter changes from temperature drift or aging.

6.3 Further Application for Derivative Topologies 191

6.3 Further Application for Derivative Topologies

The direct-chain-link topology in Figure 6.2 is a negative-output buck-boost converter but the

design philosophy and analysis developed in Sections 6.1 and 6.2 can be applied for other

direct-chain-link modular multilevel dc-dc converters.

If the dc source in the upper position exchanges places with the output capacitor in the bottom

position, as shown in Figure 6.6, the converter becomes the symmetrical counterpart to the

original converter and produces positive output. Equivalent circuits for dc and ac components

are given in Figure 6.7. Although the dc and ac current directions are in the opposite sense

compared to Figure 6.2 and Figure 6.3, the operating principle is same and the analytical results

in (6.23), (6.24) and (6.25) still apply.

Figure 6.6. Current loops in the direct-chain-link positive-output buck-boost converter

LT

LB

Co

Idc

Xfilt

vfilt

vin

vo

vin-dc=Vdc

iin-dc=Idc

vin-ac=vin-rip

iin-ac=

vo-dc=VdcR

io-dc=

vo-ac=vo-rip

io-ac= vf-ac =vac

if-ac 0

vf-dc=0

iac

2

Idc

R

iSTB=Idc iac

2

iSTT= Idc

R

iac

2

if-dc = Idc Idc

R

Idc

R

iac

2

iac

2

vf=vac

vSTB=Vdc +vin-rip+vac vLB

vSTT=VdcR+vo-rip vac vLT

SMT1

SMTN

SMB1

SMBN


(a) (b)

Figure 6.7. Equivalent circuit analysis of the direct-chain-link positive-output buck-boost converter. (a)

DC components. (b) AC components.

A further variation is created if the dc input source is connected across the pair of stacks rather

than across the top stack only, as shown in Figure 6.8. The converter is now a direct-chain-link

modular multilevel buck converter, and the equivalent circuits are given in Figure 6.9. The dc

circuit is analogous to a standard switch-mode buck converter, and the ac circuit is comprised

of two controllable ac voltage sources, two arm inductors and the input dc capacitor. With the

dc and ac equivalent circuits, the minimum current amplitude and the required frequency can

be derived by the same step-by-step process as presented in Sections 6.1 and 6.2, and the

general analytical results are provided in Section 6.6.3.

If the input dc source and output dc capacitor in Figure 6.8 are exchanged with each other, the

circuit is then developed to a direct-chain-link modular multilevel boost converter, but the

analysis is still the same as the buck configuration.

LT

LB

Idc

vin-dc=Vdc

Co

Xfilt

SWT

SWB

vo-dc=VdcR

= Idc

Idc

R

Idc

R

vf-dc=vL=0

if-dc=iL

vf-dc

iSTT-dc=iSWT= Idc

R

iSTB-dc=iSWB=Idc

vSTB-dc=vSWB=Vdc

vSTT-dc=vSWT=VdcR

LT

LB

vin-ac=vin-rip

Covo-ac=vo-rip

Xfilt

vSTT-ac

vSTB-ac

vf-ac

vf-ac=vac

if-ac 0

= iciriac

2

Cin


Figure 6.8. Current loops in the direct-chain-link buck converter

(a) (b)

Figure 6.9. Equivalent circuit analysis of the direct-chain-link buck converter. (a) DC components. (b)

AC components.

LT

LB

Co

Idc

Xfiltvin

vo

vf

if-dc=

vin-dc=Vdc

iin-dc=Idc

vin-ac=vin-rip

iin-ac=

vo-dc=VdcR

io-dc=

vo-ac=vo-rip

Idc

R

(1 R)iac

2

(1 R)iac

2

vf-ac =vac

if-ac 0

vf-dc=0

Idc

R

Idc

R

io-ac 0

(1 R)Idc

R

vSTB=VdcR+vo-rip +vac

iSTT=Idc+ (1 R)iac

2

(1 R)iac

2+(1 R)Idc

RiSTB=

SMT1

SMTN

SMB1

SMBN

vSTT=Vdc(1 R)+vin-ripvacvo-rip vLBvLT

LT

LB

vf-ac=vac

vin-ac=vin-rip Xfilt

LT

LB

Idc

Xfilt

vf-dc vf-ac

vSTT-ac

vSTB-ac

if-dc=iL=

Co

if-ac 0

(1 R)Idc

R

SWT

SWB

Idc

R

= icir(1 R)iac

2

vo-ac=vo-rip

vf-dc=vL=0

vin-dc=Vdc

vo-dc=VdcR

Idc

R


Turning attention to how these direct-chain-link dc-dc converters might be applied in dc

networks, the negative-output buck-boost configuration could be used to connect a monopolar

dc system to a bipolar dc system (𝑣𝑏𝑖+ = 𝑣𝑏𝑖− = 𝑣𝑚𝑜), shown in Figure 6.10 (a). The positive-

output configuration presented in Figure 6.10 (b) can be utilized to accomplish the low step-up

conversion (𝑣𝑚𝑜2/𝑣𝑚𝑜1 ≤ 3) between two monopolar dc systems of similar but not identical

voltages. The buck configuration in Figure 6.10 (c) is a good candidate for the low step-down

ratio conversion.

(a) (b) (c)

Figure 6.10. Application examples for different direct-chain-link dc-dc converters. (a) Negative-output

buck-boost configuration. (b) Positive-output buck-boost configuration. (c) Buck configuration.

Moreover, the single converters in Figure 6.10 are all suitable to serve as the building blocks

for further arrangements.

The positive-output configuration or negative configuration can have their outputs placed in

parallel to achieve higher current ratings in similar way to push-pull or interleaved topologies,

shown in Figure 6.11 (a). Each individual converter circuit is operated with the switching

sequence a fraction of cycle phase-shift (half-cycle in the case of two converters) with respect

to the next converter which gives a reduced voltage ripple on the dc link capacitors. Series

connection is also possible, as shown in Figure 6.11 (b), to form the bipolar topology. The

positive leg and negative leg are also modulated with half-cycle phase-shift between their

switching sequences. In this manner, the top stack current of the positive leg will approximately

equal the bottom stack current of the negative leg (𝑖𝑆𝑇2𝑇 ≈ 𝑖𝑆𝑇1𝐵), and the currents passing

Lmvo(vbi)

Co

vin(vmo)

vo(vmo2)Lm

Co

vin(vmo1)

vin(vmo1)Lm

Covo(vmo2)vbi

vbi+

LT

LB

SMBN

SMB1

SMTN

SMT1

LT

LB

LT

LB

SMBN

SMB1

SMTN

SMT1

SMBN

SMB1

SMTN

SMT1


through the bottom stack of the positive leg all flows into the top stack of the negative leg

(𝑖𝑆𝑇2𝐵 = 𝑖𝑆𝑇1𝑇). The inner two neighboring stacks can be regarded as a unified stack and the

grounding of that stack can be removed. The bipolar circuit creates twice the voltage rating and

can also accommodate low step-ratio power connection between two bipolar dc systems

(𝑣𝑏𝑖2/𝑣𝑏𝑖1 ≤ 3).

These direct-chain-link modular multilevel structures can also be connected in a cascade

arrangement and the derivative topologies can serve as high step-ratio dc-dc converter to

interface high voltage network to lower voltage in-feeds or offtakes albeit with the power loss

penalty expected. Two-stage cascade connections of the buck-boost and buck configurations

are shown in Figure 6.11 (c) and Figure 6.11 (d) respectively as examples for high-ratio step-

up and step-down conversion. The output voltage of one stage (Module 1) serves as the input

voltage of the next stage (Module 2), and the step-ratio can be further extended with more

stages.

(a) (b)

vo

Lm2

vin+(vbi1+)

Co2

Lm1

Co1

vo+

Positive Leg

Negative Leg

(vbi2 )

(vbi2+)

Lm1Lm2

vin(vmo)

vo(vbi)

Negative Push-pull

Co

Lm1Lm2

vo(vmo2)

Positive Push-pull

Co

vin(vmo1)

vdc2

vdc1

vin (vbi1 )

L1T

L1B

SM1BN

SM1B1

SM1TN

SM1T1

L2T

L2B

SM2BN

SM2B1

SM2TN

SM2T1

L1T

L1B

SM1BN

SM1B1

SM1TN

SM1T1

L2T

L2B

SM2BN

SM2B1

SM2TN

SM2T1

L2T

L2B

SM2BN

SM2B1

SM2TN

SM2T1

L1T

L1B

SM1BN

SM1B1

SM1TN

SM1T1


(c) (d)

Figure 6.11. Derivative arrangements and topologies. (a) Parallel arrangement: push-pull topology. (b)

Series arrangement: bipolar topology. (c) Cascade arrangement: high step-up topology. (d) Cascade

arrangement: high step-down topology.

These derivative direct-chain-link modular multilevel dc-dc converters and their further

arrangements satisfy various kinds of dc interconnection requirements, and all of them can still

utilize the same principle and method developed in Sections 6.1 and 6.2 to select their

respective internal circulating current frequency and achieve the minimum current amplitude

stresses and reactive power losses in the direct dc-dc conversion.

6.4 Assessment of Simulation Analysis

This section presents a set of simulations to verify the theoretical analysis above, and the

parameters for the negative-output buck-boost configuration (specifically Fig. 10 (a)) are

recorded in Table 6.1. The terminal voltage and power device rating lead to a choice of 9 SMs

for each stack and a SM capacitance of 1.0 mF to achieve a 10% range for capacitor voltage

variation, which together result in a 14 kJ/MVA of the stack energy storage. The choice of

modulation index is a trade-off between voltage stresses and current stresses, and its value

Lm1

vo(vHS)

Lm2

Co1

Co2

vin(vLS)

High Step-up

vin(vHS)

Lm2

Lm1

Co1

vo(vLS)Co2

High Step-Down

Module 2

Mod

ule

1 M

odule 2

Mod

ule

1

L2T

L2B

SM2BN

SM2B1

SM2TN

SM2T1

L1T

L1B

SM1BN

SM1B1

SM1TN

SM1T1

L1T

L1B

SM1BN

SM1B1

SM1TN

SM1T1

L2T

L2B

SM2BN

SM2B1

SM2TN

SM2T1


varies according to the step-ratio needed to match the specific negative-pole voltage. The SM

capacitances are varied from their nominal values by up to 10% to represent manufacturing

variation of components in a practical converter.

Table 6.1. Simulation parameters of the low step-ratio direct-chain-link negative-output buck-boost

converter


𝑃𝑇 Power Throughput 3 MW

𝑣𝑖𝑛(𝑣𝑚𝑜) Input Positive-pole Voltage 11 kV

𝑣𝑏𝑖− Negative-pole Voltage 7 kV–11 kV

𝑅 Step-ratio 0.5:1–1:1

𝑣𝑜(𝑣𝑏𝑖) Output Bipolar Voltage 18 kV–22 kV (±11 kV)

𝐶𝐷𝐶 DC Link Capacitance 300 µF

𝐿𝑎𝑟𝑚(𝐿𝑇 𝐿𝐵) Arm Inductance 150 µH

𝑛𝑎𝑟𝑚(𝑛𝑇 𝑛𝐵) SM Number in Each Stack 9

𝐶𝑘 SM Capacitance (𝑘 = 1…9) 1.0 mF with ±10% variation


𝑆

Power Switches Selected Type MITSUBISHI CM1200HA-66H



6.4.1 Symmetrical Conversion

The symmetrical voltage conversion (𝑅 = 𝑣𝑏𝑖−/𝑣𝑚𝑜 = 1) is discussed first. The modulation

index is chosen at 0.8 in this study. The ac modulation frequency is set at 800 Hz to achieve

the minimum circulating current according to the analysis in (6.24) given the circuit parameters

in Table 6.1. Figure 6.12 (a) shows the simulated stack voltages and it confirms that the ac

components of the top stack voltage 𝑣𝑆𝑇𝑇 and bottom stack voltage 𝑣𝑆𝑇𝐵 are phase-shifted by

approximately 180° but their dc components are the same. The stack currents are shown in

Figure 6.12 (b) and illustrate that the ac components of the two stack currents 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵 are


almost the same but their dc components are opposite polarity. It can be seen that the phase

difference between voltage and current for top stack is approximately 180° and the phase

difference for bottom stack is approximately 0°, so there is nearly no reactive power in the ac

energy loop and the ac components have been fully utilized for stack energy balancing. The

amplitude of the circulating ac current observed in Figure 6.12 (b) is about 690 A which agrees

reasonably well with the theoretical value of 679 A obtained from (6.23) and this demonstrates

that 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵 are both almost at their minimum values in this case. Further, it can be seen

that the SM voltages in top stack and bottom stack are both well controlled. The maximum

voltage deviation is limited within 10% of the nominal SM voltage of 2.2 kV, shown in Figure

6.12 (c) and Figure 6.12 (d), and the sum of the dc components of SM capacitor voltages in

each stack is 19.8 kV, which nearly matches the maximum value of the stack voltage envelope.

(a)

(b)


(c)

(d)

Figure 6.12. Simulation results in the symmetrical conversion. (a) Stack voltages 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵. (b)

Stack currents 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵. (c) SM voltages in top stack 𝑣𝐶𝑇𝑘 , 𝑘 = 1…9. (c) SM voltages in bottom

stack 𝑣𝐶𝐵𝑘 , 𝑘 = 1…9.

6.4.2 Asymmetrical Conversion

An asymmetrical voltage conversion (𝑅 = 𝑣𝑏𝑖−/𝑣𝑚𝑜 = 0.67) was chosen for the next example

to verify the ac frequency analysis in a general case. Simulation results are shown in Figure

6.13. Since the dc component of the bottom stack voltage is lower than the 𝑅 = 1 case (to

create the smaller negative-pole voltage), the modulation index is changed to 0.54. The power

conversion is reduced to 1.33 MW, and the ac frequency is set at 925 Hz in line with the analysis

of (6.26) in Appendix Section 6.6.2. Figure 6.13 (a) and Figure 6.13 (b) confirm that the ac

components of stack voltages are phase-shifted by nearly half cycle and the stack ac currents

are equal for the two stacks, but the dc components are different because of this asymmetrical

conversion. The value of dc and ac components observed agree with the theoretical analysis in

Section 6.2. Again, there is also almost no ac reactive power in the energy loop. The circulating


current is about 460 A, which further validates the analysis in (6.27) which gives a theoretical

value of 446 A. In Figure 6.13 (c) and Figure 6.13 (d), the SM voltages in the top stack are

balanced around an average value of 1.9 kV whereas the SM voltages in the bottom stack are

balanced around 1.5 kV. The sum of their dc components also approximately matches the

maximum value of their respective stack voltage.

(a)

(b)

(c)


(d)

Figure 6.13. Simulation results in the asymmetrical conversion. (a) Stack voltages 𝑣𝑆𝑇𝑇 and 𝑣𝑆𝑇𝐵. (b)

Stack currents 𝑖𝑆𝑇𝑇 and 𝑖𝑆𝑇𝐵. (c) SM voltages in top stack, 𝑣𝐶𝑇𝑘, 𝑘 = 1…9. (c) SM voltages in bottom

stack, 𝑣𝐶𝐵𝑘 , 𝑘 = 1…9.

6.4.3 Bipolar Conversion

Lastly, the simulation results for the bipolar direct-chain-link buck-boost converter are

provided in Figure 6.14 as an example for the derivative topologies discussed in Section 6.3.

(a)

(b)


(c)

(d)

Figure 6.14. Simulation results in the bipolar conversion. (a) DC Terminal voltages and dc capacitor

voltages, 𝑣𝑏𝑖2+, −𝑣𝑏𝑖2−, 𝑣𝑑𝑐2, −𝑣𝑑𝑐1 . (b) Stack currents, 𝑖𝑆𝑇2𝑇 , 𝑖𝑆𝑇2𝐵, 𝑖𝑆𝑇1𝑇 , −𝑖𝑆𝑇1𝐵 . (c) Voltage

deviation of SM capacitors in the positive leg, 𝑣𝐶2𝑇−𝑚𝑎𝑥, 𝑣𝐶2𝑇−𝑚𝑖𝑛, 𝑣𝐶2𝐵−𝑚𝑎𝑥, 𝑣𝐶2𝐵−𝑚𝑖𝑛. (d) Voltage

deviation of SM capacitors in the negative leg, 𝑣𝐶1𝑇−𝑚𝑎𝑥, 𝑣𝐶1𝑇−𝑚𝑖𝑛, 𝑣𝐶1𝐵−𝑚𝑎𝑥, 𝑣𝐶1𝐵−𝑚𝑖𝑛.

The positive leg and negative leg utilize the same parameters as in Table 6.1 and the switching

sequence uses a half-cycle phase-shift between the legs. The bipolar terminal voltages

(𝑣𝑏𝑖2+, −𝑣𝑏𝑖2− ) and dc capacitor voltages (𝑣𝑑𝑐2, −𝑣𝑑𝑐1 ) in Figure 6.14 (a) confirm the

symmetrical bipolar conversion, and the stack currents in Figure 6.14 (b) illustrated that the

current amplitudes are all operated at the predicted minimum values (the dc current is about

270 A and the ac current is about 690 A). The maximum and minimum value of the SM

capacitor voltages in each stack are presented in Figure 6.14 (c) and Figure 6.14 (d), which

illustrate that the set of SM capacitor voltages are also well-controlled.



To further validate the theoretical analysis and simulation results, a down-scaled prototype of

the direct-chain-link negative-output buck-boost converter was designed and built (see Figure

A.4 in Appendix), and the circuit parameters are listed in Table 6.2. It also uses OPAL-RT

OP5600 as the controller and choose MITSUBISHI CM300DX-24S as the SM power switches.

Table 6.2. Experimental prototype parameters of the low step-ratio direct-chain-link negative-output

buck-boost converter.


𝑃𝑇 Power Throughput 1 kW

𝑣𝑖𝑛(𝑣𝑚𝑜) Input Positive-pole Voltage 150 V

𝑣𝑏𝑖− Negative-pole Voltage 100 V–150 V

R Step-ratio 0.5:1–1:1

𝑣𝑜(𝑣𝑏𝑖) Output Bipolar Voltage 250 V–300 V (±150 V)

𝐶𝐷𝐶 DC Link Capacitance 300 µF

𝐿𝑎𝑟𝑚(𝐿𝑇 𝐿𝐵) Arm Inductance 150 µH

𝑛𝑎𝑟𝑚(𝑛𝑇 𝑛𝐵) SM Number per Stack 9

𝐶𝑘 SM Capacitance (𝑘 = 1…9) 1.0 mF with ±10% variation

𝛾 Maximum Ripple for SM Capacitor Voltage

Tolerance

10%

The key passive parameters in this prototype choose the same values as those in simulation,

and the stack energy storage are configured at an approximate value around 14 kJ/MVA, so the

internal ac frequency is also operated at 800 Hz in the symmetrical conversion ( 𝑅 =

𝑣𝑏𝑖−/𝑣𝑚𝑜 = 1) to achieve minimum current amplitude. The experimentally observed stack

voltages and currents are presented in Figure 6.15. It should be noted that the current distortion

is caused by the on-state voltage drop of the SM IGBTs which are disproportionately large in

the low-voltage rating laboratory experiment. This distortion is negligible in a practical high-

voltage rating application because the on-state voltage drop is very small compared to the high

voltage link. It can be seen that the ac component of top stack voltage has a phased-shift value


of approximately 180° with respect to that of bottom stack voltage and that the ac currents are

equal for the two stacks. The phase-shift between top stack voltage and current is nearly 180°

and the phase-shift between bottom stack voltage and current is nearly 0°, so the reactive power

is very small. The dc components of voltage have the same value in this symmetrical case but

the dc currents are in the opposite directions as expected. Importantly, the dc and ac values of

the stack voltages and currents follow the theoretical analysis in Section 6.2.2 and 6.2.3. The

ac current amplitude is about 18 A, which is approximately matched with the theoretical results

of 16.6 A from (6.23) and this means that the stack currents have almost achieved the minimum

value for the conditions set. Further, the top stack and bottom stack SM capacitor voltages are

all well balanced in this symmetrical conversion, as shown in Figure 6.16, and the sum of the

SM voltage capacitor voltages in each stack also match the maximum value of the stack

voltage.

Figure 6.15. Experimental results of the stack voltages and currents in the symmetrical conversion.


symmetrical conversion.

vSTT(200V/div)

vSTB(200V/div)

iSTB(20A/div)

iSTT(20A/div)

500 μs/div


The results in Figure 6.15 and Figure 6.16 further verify the theoretical derivation in Figure 6.2

and simulation assessment in Figure 6.12 for the interconnection between a monopolar and a

bipolar dc pair of systems.

The variation of step-ratio is tested in Figure 6.17–Figure 6.19 covering the asymmetrical

conversion and the controllability of the output voltage. In Figure 6.17, the input positive-pole

voltage 𝑣𝑖𝑛(𝑣𝑚𝑜) was kept constant at 150 V, and the reference value for the output voltage

𝑣𝑜(𝑣𝑏𝑖) was set at 250 V (𝑅 = 𝑣𝑏𝑖−/𝑣𝑚𝑜 = 0.67) initially for asymmetrical conversion and

increased abruptly to 300 V (𝑅 = 𝑣𝑏𝑖−/𝑣𝑚𝑜 = 1) halfway through the observation period for

symmetrical conversion. The result shows that 𝑣𝑜(𝑣𝑏𝑖) follows the regulation command

accurately both before and after the change of the reference value, and the stack currents also

respond quickly to match the load power. In the asymmetrical conversion period, the amplitude

of the bottom stack current is larger than that of the top stack as expected because of the step-

down voltage conversion. After the change of the step-ratio, the amplitudes of the two stack

currents return back to an equal value at about 25 A as the results shown in Figure 6.15 for the

symmetrical conversion. Figure 6.18 shows individual SM voltages during the asymmetrical

conversion period and confirms that the SM are well-balanced within each stack. Compared

with the symmetrical conversion results in Figure 6.16, the SM voltages in top stack are

decreased to around 30 V because the modulation index is adjusted for the negative-pole

voltage, and the SM voltages in bottom stack are balanced around 25 V. The full range

operation of this converter at various step-ratio conversion is presented in Figure 6.19. The

output voltage 𝑣𝑜(𝑣𝑏𝑖) varies linearly with the input voltage 𝑣𝑖𝑛(𝑣𝑚𝑜) as expected, and their

relationships also match very well with the theoretical values. The results illustrate that, on the

one hand, this dc-dc converter is capable of serving as a fixed ratio dc transformer in the full

voltage range, in which the output voltage tracks the increase or decrease of the input voltage,

and, on the other hand, the step-ratio value of this converter is also adjustable across a relatively

wide range to satisfy various operating conditions.


Figure 6.17. Experimental results of the variation of step-ratio.


asymmetrical conversion period.

Figure 6.19. Experimental results of full range operation at various step-ratio conversion.

500 ms/div

vo(vbi)(200V/div)

iSTB(20A/div)

iSTT(20A/div)

6.6 Appendix 207

6.6 Appendix

6.6.1 General Analysis for Buck-Boost Configuration

Substituting the results of (6.9) and (6.10) into (6.17) and (6.19), the general expression of the

internal circulating current amplitude is expressed in (6.25).

𝐼𝑐𝑖𝑟 =1

2𝐼𝑎𝑐 = 𝑚𝑎𝑥 {|

−𝑗𝐶𝐷𝐶𝑛𝑇𝐼𝑑𝑐𝛿𝑇2

2𝐶𝑆𝑀[1 − 𝜔2(𝐿𝑇 + 𝐿𝐵)𝐶𝐷𝐶](1 + 𝑚)2| [

𝑚2 + 8

2𝑚𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 𝜔𝑡

+3𝑚2 − 8

2𝑚𝑐𝑜𝑠 𝜔𝑡 + (3 − 𝑚2) 𝑠𝑖𝑛 2𝜔𝑡 + 3 𝑡𝑎𝑛 𝜃 𝑐𝑜𝑠 2𝜔𝑡 −

𝑚

2𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 3𝜔𝑡 +

𝑚

2𝑐𝑜𝑠 3𝜔𝑡

−2 𝑡𝑎𝑛 𝜃] + |−𝑗𝐶𝐷𝐶𝑛𝐵𝐼𝑑𝑐𝛿𝐵

2

2𝐶𝑆𝑀[1 − 𝜔2(𝐿𝑇 + 𝐿𝐵)𝐶𝐷𝐶](𝑅 + 𝑚)2| [

𝑚2 + 8𝑅2


+3𝑚2 − 8𝑅

2𝑚𝑐𝑜𝑠 𝜔𝑡 +

𝑚2 − 2𝑅 − 𝑅2

𝑅𝑠𝑖𝑛 2𝜔𝑡 − 3𝑅 𝑡𝑎𝑛 𝜃 𝑐𝑜𝑠 2𝜔𝑡 −

𝑚

2𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 3𝜔𝑡

+𝑚

2𝑐𝑜𝑠 3𝜔𝑡 + 2𝑅 𝑡𝑎𝑛 𝜃]} (6.25)

6.6.2 Asymmetrical Voltage Conversion for Buck-Boost Configuration

The minimum current amplitude in the asymmetrical voltage conversion ( 𝑣𝑜−𝑑𝑐 =

𝑣𝑖𝑛−𝑑𝑐𝑅, 𝑛𝑇,𝐵 = 𝑛𝑎𝑟𝑚, 𝐿𝑇,𝐵 = 𝐿𝑎𝑟𝑚, 𝑚𝑑𝑐𝑇 =1

1+𝑚, 𝑚𝑑𝑐𝐵 =

𝑅

𝑅+𝑚) is given in (6.26), and the

corresponding ac frequency is presented in (6.27).

𝐼𝑐𝑖𝑟−𝑎𝑠𝑦−𝑚𝑖𝑛 =𝑛𝑎𝑟𝑚𝐼𝑑𝑐𝐶𝐷𝐶[(8 − 3𝑚2)(𝑅 + 𝑚)2 + (8𝑅 − 3𝑚2)(1 + 𝑚)2]

4𝐶𝑆𝑀(𝑅 + 𝑚)2(1 + 𝑚)2𝑚(2𝜔2𝐿𝑎𝑟𝑚𝐶𝐷𝐶 − 1) (6.26)

𝑓𝑎𝑐−𝑎𝑠𝑦 =1

2𝜋√

1


𝑛𝑎𝑟𝑚[(8 − 3𝑚2)(𝑅 + 𝑚)2 + (8𝑅 − 3𝑚2)(1 + 𝑚)2]

16𝐿𝑎𝑟𝑚𝐶𝑆𝑀(𝑅 + 𝑚)2(1 + 𝑚)2 (6.27)


6.6.3 General Analysis for Buck Configuration

The general analysis of the circulating current amplitude for the direct-chain-link modular

multilevel buck configuration is expressed in (6.28). 𝛿𝑇 and 𝛿𝐵 are still the redundancy ratio

for the dc components of stack voltages, but the expressions for SM stack dc modulation index

𝑚𝑑𝑐𝑇 and 𝑚𝑑𝑐𝐵 have been changed in this buck configuration (𝑉𝑎𝑐 = 𝑚𝑉𝑑𝑐 ≤ 𝑚𝑖𝑛[𝑉𝑑𝑐(1 −

𝑅), 𝑉𝑑𝑐𝑅], 𝑅 ≤ 1,𝑚𝑑𝑐𝑇 =𝛿𝑇(1−𝑅)

1−𝑅+𝑚, 𝑚𝑑𝑐𝐵 =

𝛿𝐵𝑅

𝑅+𝑚, 𝛿𝑇,𝐵 ≤ 1 ). Also, 𝐶𝐷𝐶 still represents the

equivalent dc link capacitance, but it equals the input capacitance 𝐶𝑖𝑛 in this configuration

(𝐶𝐷𝐶 = 𝐶𝑖𝑛).

𝐼𝑐𝑖𝑟 = 𝑚𝑎𝑥 {|−𝑗𝐶𝐷𝐶𝑛𝑇𝐼𝑑𝑐𝛿𝑇

2(1 − 𝑅)

2𝐶𝑆𝑀[1 − 𝜔2(𝐿𝑇 + 𝐿𝐵)𝐶𝐷𝐶](1 − 𝑅 + 𝑚)2| [

𝑚2 + 8(1 − 𝑅)2


+3𝑚2 − 8(1 − 𝑅)2

2𝑚𝑐𝑜𝑠 𝜔𝑡 +

−𝑚2 + 3(1 − 𝑅)2

1 − 𝑅𝑠𝑖𝑛 2𝜔𝑡 + 3(1 − 𝑅) 𝑡𝑎𝑛 𝜃 𝑐𝑜𝑠 2𝜔𝑡

−𝑚

2𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 3𝜔𝑡 +

𝑚

2𝑐𝑜𝑠 3𝜔𝑡 − 2(1 − 𝑅) 𝑡𝑎𝑛 𝜃]

+ |−𝑗𝐶𝐷𝐶𝑛𝐵𝐼𝑑𝑐𝛿𝐵

2𝑅

2𝐶𝑆𝑀[1 − 𝜔2(𝐿𝑇 + 𝐿𝐵)𝐶𝐷𝐶](𝑅 + 𝑚)2| [

(𝑚2 + 8𝑅2)(1 − 𝑅)

2𝑚𝑅𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 𝜔𝑡

+(3𝑚2 − 8𝑅2)(1 − 𝑅)

2𝑚𝑅𝑐𝑜𝑠 𝜔𝑡 +

(𝑚2 − 3𝑅2)(1 − 𝑅)

𝑅2𝑠𝑖𝑛 2𝜔𝑡 − 3 (1 − 𝑅)𝑡𝑎𝑛 𝜃 𝑐𝑜𝑠 2𝜔𝑡

−𝑚

2𝑅(1 − 𝑅)𝑡𝑎𝑛 𝜃 𝑠𝑖𝑛 3𝜔𝑡 +

𝑚

2𝑅(1 − 𝑅)𝑐𝑜𝑠 3𝜔𝑡 + 2(1 − 𝑅) 𝑡𝑎𝑛 𝜃]} (6.28)

6.7 Chapter Summary

This chapter presented a single-stage direct-chain-link modular multilevel buck-boost

converter for low step-ratio high power throughput conversion between two dc terminals with

similar but not identical voltages. An analysis method for the choice of the circulating current

frequency was created, which minimizes the current stresses and reactive power losses in this


single-stage dc-dc conversion while also meeting the SM stack balancing requirements and

limits on the SM voltage ripple.

To introduce this direct-chain-link dc-dc converter, its connection to and comparison with the

standard single-phase dc-ac MMC were presented. The dc and ac components of voltage and

current in this direct-chain-link dc-dc converter were analysed. Then, a process for deriving the

circulating frequency was given in detail with the objective of minimising the current amplitude

in the conversion while also satisfying the SM stack balancing requirement.

This analysis method can be applied to other direct-chain-link modular multilevel dc-dc

converters and derived topologies for a variety of conversion requirements. It has been shown

that the original negative-output direct-chain-link buck-boost configuration can be designed to

interconnect a monopolar dc system to a bipolar dc system, and the symmetrical positive-output

configuration can be utilised to accomplish low step-up conversion between two monopolar dc

systems of similar voltages. The chain-link buck configuration was put forward as a good

candidate for low ratio step-down conversion.

The theoretical analysis of the internal circulating current and the choice for its frequency have

been verified by both simulation and experiments. The simulation and experimental results

closely matched with the mathematical analysis, and they demonstrated the validity of the

analysis method.

Chapter 7 Conclusion

In multi-terminal and multi-voltage dc networks, there are important roles for both high step-

ratio and low step-ratio dc-dc conversions to interface dc links at different voltages. The work in

this thesis has explored the possibility of combining the relatively recent modular multilevel

converter (MMC) technology with the classic dc-dc circuits and has gone on to propose several

modular multilevel dc converters, and their associated modulation methods and control

schemes, in order to achieve the low-cost, high-compactness, high-efficiency and high

reliability interconnection in dc networks.

Chapter 3 and Chapter 4 concern resonant modular multilevel dc converters (RMMC) (using

LLC structure) for MVDC network interconnection with high step-ratio and low step-ratio.

Chapter 5 and Chapter 6 concentrate on the non-resonant modular multilevel dc converters for

HVDC network interconnection, including a modular multilevel dc-ac-dc converter (using

single-active-bridge (SAB) or dual-active-bridge (DAB) structure) for high step-ratio

conversion and a direct-chain-link modular multilevel dc-dc converter (using buck-boost

structure) for low step-ratio conversion.

7.1 Resonant Modular Multilevel DC Converters for MVDC

Applications

A basic high step-ratio RMMC topology was proposed in Chapter 3 for bidirectional high step-

ratio conversion between MVDC and LVDC distribution networks. This converter was derived

from the classic LLC resonant circuit by introducing MMC-like stack of SMs in place of the

half-bridge or full-bridge inverter in the original configuration. It utilises the MMC-like

structure to support the MVDC stress and the modular structure can also incorporate

redundancy. It has also been shown to maintain the operational benefits of original LLC circuit

212 Conclusion

thereby decreasing switching losses and maintaining good power efficiency. The SM stack

generates a square-wave voltage across the resonant tank and excites energy exchange between

the SM capacitors and the resonant inductor. This resonant operation assists both upper and

lower switches of each SM to achieve soft-switching. A phase-shift modulation scheme was

developed for this converter that increases the effective operation frequency of circuit to

facilitate stack volume reduction and also provides inherent voltage balancing of all the SM

capacitors. It has been shown that there is flexibility in choices of phase-shift angle and SM

duty-cycle that can be used to cater for a wide range of step-ratio. Design guidelines and

modulation constraints were created that ensure that soft-switching and inherent voltage-

balancing are maintained for all the step-ratio cases. This basic high step-ratio RMMC was also

employed as a building block for variety of further configurations, and they form a family of

high step-ratio RMMCs, which addresses the limitations of step-ratio and power rating of the

basic RMMC and satisfies a wider range of specifications for MVDC and LVDC

interconnection. The approach to creating these derived configurations was also generalized

and applied to other classic dc-dc circuits for medium voltage level high step-ratio conversion.

Inspired by the success of the high step-ratio RMMC, a step-by-step evolution of the circuit

into a low step-ratio RMMC was established in Chapter 4, resulting a bidirectional low step-

ratio conversion between MVDC links with similar but not identical voltages. This basic low

step-ratio RMMCs inherited all the key operational advantages that were present in high step-

ratio RMMC version, including soft-switching operation for SM switches, inherent balancing

of the SM capacitor voltages and high effective switching frequency for exciting the internal

resonance. Noting that the flexibility of the SM stack modulation ratio is sufficient on its own

to fulfil the low ratio voltage transformation and that galvanic isolation is not always a

requirement, the internal transformer used in high step-ratio RMMC family was removed with

a consequential reduction in volume and increase in efficiency. Moreover, the SM stack of this

low step-ratio RMMC was shared between the low-voltage and high-voltage terminals (i.e. it

carries only the difference between the low-side and high-side currents) and consequently it is

only required to process a small fraction of the power throughput because the bulk of the power

pass directly between the two dc terminals. The fraction of power processed, rather than

directly passed through, is small if the voltage ratio is small. As a result, the required ratings

7.2 Non-Resonant Modular Multilevel DC Converters for HVDC Applications 213

of this SM stack in terms of semiconductor volt-ampere rating and capacitive energy storage

are substantially lower than those for the alternative converters using the front-to-front and

direct-chain-link MMC configurations. The required semiconductor volt-ampere rating of the

basic low step-ratio RMMC is generally below 11 normalised to the total power throughput

and the required stack energy storage is only about 1.4 kJ/MVA. These advantages in terms of

component ratings are expected to make significant savings in footprint and cost for this

converter for low step-ratio applications. Lastly, this basic low step-ratio can also serve as a

building block for a variety of further configurations, which form a family of low step-ratio

RMMCs to accommodate different configurations of MVDC distribution systems and to

achieve higher overall power rating conversion.

The theoretical analysis and operating principles of both high step-ratio and low step-ratio

RMMCs have been verified against full-scale simulation examples and further verified against

tests on down-scaled experimental prototypes.

7.2 Non-Resonant Modular Multilevel DC Converters for HVDC

Applications

Noting that the difficulties for stack modulation design and effective frequency choice increase

rapidly as the SM total number rises in a single circuit RMMC, and that the multi-module

configurations pose additional challenges for module transformers insulation and reliability, it

was realised that the RMMC family of circuits is more suited to cases requiring a small number

of SMs ( 𝑁 ≤ 10 ) or a small number of modules and is therefore probably limited to

interconnection of medium voltage dc systems. When the dc link voltage extends beyond 100

kV, an RMMC would need either a large number of SMs or a large number of circuit modules

to support the dc link voltage and the difficulties in design and operation of the RMMCs

become too great. To rise to the challenge of high voltage level dc interconnection, two non-

resonant modular multilevel dc converters were proposed and developed: for high step-ratio

conversion in Chapter 5 and for low step-ratio conversion in Chapter 6.

214 Conclusion

Chapter 5 presented a modular multilevel dc converter for high step-ratio low power throughput

connection such as between an HVDC transmission system and an MVDC network. It was

based on a two-stage dc-ac-dc conversion using the SAB or DAB configuration (giving

unidirectional or bidirectional power flow respectively). It inherited the medium-frequency

operation and soft-switching benefits from the original SAB/DAB structure which facilitate

reduction of physical volume and good efficiency, and it also inherited the modularity and high

reliability features of the MMC concept that are important for HVDC applications. High step-

ratio conversion was accomplished by a combination of the inherent ratio of 2 of the half-bridge

configuration, the SM stack modulation ratio and transformer turns-ratio. Together these are

expected to offer flexibility in both design and operation to provide a wide choice of overall

step-ratio. Operation with a near-square-wave current was proposed for this topology in order

to decrease the required volt-ampere rating for power devices and reduce the capacitive energy

requirement for SM stack capacitors. The analysis and simulation results have demonstrated

that compared to the traditional sinusoidal operation, the near-square-wave operation can lead

to a decrease of about 30% in the required volt-ampere rating for semiconductor devices and a

decrease of about 25% in energy storage requirement for SM capacitators. Furthermore, the

near-square-wave current operation in single-phase configuration leads to near-constant

instantaneous power flow such that the dc smoothing capacitors can be also very small. An

energy balance method and a control strategy for this mode of operation were proposed and

verified. The converter can be controlled in current source mode to interface dc links with

different voltage levels and it can be also operated in voltage source mode to collect the power

from offshore wind farms or feed power to an isolate grid in a remote area.

The dc-ac-dc configuration can benefit from the practical and commercial experience acquired

in ac-dc MMCs and thus is a low-risk pathway to dc-dc conversion in HVDC. However, this

multi-stage dc-dc conversion invariably increases the power losses and system footprint since

the converter needs two separate steps (ac-dc and dc-ac) to accomplish the dc-dc conversion.

Chapter 6 presented a single-stage direct-chain-link modular multilevel dc-dc converter which

is suitable for low step-ratio high power throughput conversion between two dc terminals with

similar but not identical voltages. This topology utilised only one MMC phase leg to realise

direct dc-dc conversion. This leads to good utilisation of the power semiconductors but also

7.3 Future Work 215

has no requirement for an ac transformer. Therefore, this direct-chain-link dc-dc converter is

expected to have advantages over the multi-stage dc-ac-dc alternatives in terms of power

losses, system footprint and overall cost.

Noting that all of the direct-chain-link modular multilevel dc-dc configurations rely on an

internal-circulating ac current to balance the stack energies and that this circulating current

inevitably adds to the current amplitude stresses and power losses for both the SM switches

and passive components in the circuit, an analysis method was created in Chapter 6 to support

the choice of the circulating current frequency. Using this, the current stresses and reactive

power losses can be minimised while also meeting the SM stack balancing requirements and

limits on the SM voltage ripple. This methodology can be applied to other direct-chain-link dc-

dc converters and derived configurations for a variety of conversion requirements.

The theoretical analysis and operating principles of these two non-resonant modular multilevel

dc converters have been also verified by both simulation results and down-scale experimental

tests.

7.3 Future Work

In addition to the work presented in this thesis, there are still a number of open questions and

research challenges remaining in the field of modular multilevel dc converters for MVDC and

HVDC applications.

The phase-shift modulation scheme in high step-ratio RMMC family provides the inherent

voltage-balancing capability for SM capacitors and also generate a high effective frequency for

resonance with relatively low switching frequency. However, the difficulties for stack

modulation design and effective frequency choice increase quickly as the SM total number

rises. As analysed in Section 3.3.5, these disadvantages inhibit extending the total number of

SMs in a single circuit RMMC and thus limits the voltage that can be processed. The input-

series-output-parallel multi-module configuration could alleviate this issue to some extent, but

it will bring about insulation challenge and reliability concern for module transformers as with

the classic modular DAB. Actually, the classic nearest level modulation method could be an

216 Conclusion

easier option when a large number of SMs are implemented into one stack, and an additional

small resonant capacitor can be inserted into the circuit to decrease the difference between

positive stage resonant frequency and negative stage resonant frequency. In this manner, the

difficulties for stack modulation design and effective frequency choice can be both effectively

reduced, but it will require an extra voltage sorting and selection process to realise voltage

balancing for all the SM capacitors and it may also need some specific effort to maintain the

soft-switching benefits for all the SM switches from resonant operation. Furthermore, the SM

switching frequency in nearest level modulation will be usually slightly higher than the

effective frequency of the square wave voltage, which is also in the disadvantageous position

compared to the phase-shift modulation. It would be valuable to have a thorough comparison

between the phase-shift modulation and nearest level modulation for the operation of high step-

ratio RMMC family and to identify the most suitable approach for specific conversion

applications.

A further question worthy of investigation is that the square-wave voltage on the high-voltage

side has the same phase as that on the low-voltage side and so the voltage and current control

of the high step-ratio RMMC family for a given modulation combination (𝑦 and 𝑥 has been

both decided) can only be realised by adjusting the effective frequency. However, the effective

frequency cannot deviate from either positive stage or negative stage resonant frequency far

away in order to keep the good resonant performance and overall conversion efficiency. In fact,

though, the phase-shift angle between the high-side and low-side voltages could be adjusted

during the operation and it would create an additional degree-of-freedom to be used to control

the power. This may open up a new research direction in the future work.

Since the basic low step-ratio RMMC has been evolved from the basic high step-ratio RMMC,

research on nearest level modulation and phase-shift angle could be also applied to the low

step-ratio RMMC family with similar objectives. Also, noting that the rectifiers in the low step-

ratio RMMC family have to withstand the voltage difference between high-side and low-side

terminals, the circuit structure for the rectification process would need some development and

improvement for the higher voltage rating conversion. When the dc terminal voltages are in

the medium voltage range, the single switch configuration or series connection with small

number of devices can be utilised to support the relatively small voltage difference that arises

7.3 Future Work 217

in low step-ratio conversion. However, if dc terminal voltage rating continues to grow as they

have in recent years then the voltage difference could become large despite that the voltage

step-ratio between them is being relatively low. The simple series connection would face

technical challenges to partition the voltage stress. Additionally, the anti-parallel diodes of the

rectifier switches could become problematic in the event of a high-side dc fault just as observed

with faults in classic ac-dc MMC. Therefore, the low step-ratio RMMC family would need

some advanced rectification topology with voltage balancing and reverse block capability to

solve or alleviative these issues, which could be the basis of some useful future work.

For the high step-ratio modular multilevel dc-ac-dc converter, the major drawback is the high-

side dc link capacitor, which will contribute fault current in the event of a dc fault and requires

extra control features to balance the voltage stress. The high-voltage side of this converter can

be developed to a full-bridge configuration with two MMC phase legs to avoid the dc link

capacitor, and the power throughput would also be doubled compared to the original half-

bridge configuration in this thesis. However, the half-bridge arrangement itself can contribute

an inherent voltage ratio of 2 to make it easier to achieve the high step-ratio conversion. Also,

the full-bridge configuration needs twice number of SMs in the stacks and would require more

isolation clearance space in a high voltage valve hall, which may increase the overall cost for

the converter itself as well as that of the associated ground station or offshore platform. A

detailed and comprehensive analysis and comparison for these two configurations would be

worthwhile to provide a clearer choice for this high step-ratio low power throughput

application.

The near-square-wave current modulation proposed in this thesis can effectively reduce the

required rating for SM semiconductors and SM capacitors, but it also poses a challenge for the

transformer design and implementation. As discussed in Section 5.4.5, the modulation

waveforms can be modified to trapezoid or triangle and the operation frequency can be reduced

to 200 Hz–300 Hz for some higher power throughput applications, but the non-standardized

transformer design and implementation can be another important future work of this thesis,

including the the analytical choice for voltage/current waveform, operation frequency and

turns-ratio value and the innovation and optimization on core/winding material and structure.

218 Conclusion

The circuit topology of the low step-ratio direct-chain-link modular multilevel buck-boost

converter in Chapter 6 is derived from the classic single-phase dc-ac MMC, and so it will also

face the challenge of blocking dc fault in the same way as the classic MMC. As was shown in

Figure 6.10, these direct-chain-link modular multilevel dc-dc converters can block the dc fault

in the low-side dc terminal, but in the event of high-side dc fault, the low-side dc terminal

would bring about large fault current through the anti-parallel diodes of the SM stack to the

fault point. It would need expensive dc circuit breaker to isolate the fault quickly and protect

the equipment, so the overall cost will be increased a lot. It would be valuable to explore the

possibility of whether the single-stage direct-chain-link concept could be also applied to other

modular multilevel dc-ac converters with the dc fault blocking capability because dc-dc

converters derived from it would inherit this benefit and reduce the requirement of, or

eliminate, dc circuit breakers in HVDC network interconnection. Further, it would be

interesting to explore other ac voltage and current waveforms (square wave, trapezoid, triangle,

etc.) for stack energy balancing and find an optimal choice for the direct-chain-link modular

multilevel dc-dc converters.

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Appendix

A.1 Resonate Modular Multilevel DC Converter Prototypes

The down-scaled experimental prototypes for the high step-ratio RMMC and low step-ratio

RMMC are shown in Figure A.1 and Figure A.2 respectively.

Figure A.1. High step-ratio RMMC prototype with TI-DXP controller system.

2 Appendix

Figure A.2. Low step-ratio RMMC prototype with TI-DXP controller system.

A.2 Non-Resonate Modular Multilevel DC Converter Prototypes

The down-scaled experimental prototypes for the high step-ratio modular multilevel dc-ac-dc

converter and low step-ratio modular multilevel dc-dc converter are shown in Figure A.3 and

Figure A.4 respectively.

Appendix 3

Figure A.3. High step-ratio modular multilevel dc-ac-dc converter prototype with OPAL-RT controller

system.

Figure A.4. Low step-ratio modular multilevel dc-dc converter prototype with OPAL-RT controller

system.

Documents

The Modular Multilevel DC Converters for MVDC and HVDC