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THE MICROPROCESSORVon Neumann’s Architecture Model
Input/Output unit Provides instructions and data
Memory unit Stores both instructions and data
Arithmetic and logic unit Processes everything
Control unit Controls execution of instructions
Central processing unit = ALU + CU
Stored program 7→ Program can be manipulatedas if it is data
1
System Bus Architecture Model
System bus
Data bus carries transmitted data
Address bus identifies location of transmitted
data
Control bus specifies how data is transmitted
Power bus supplies power to units
I/O bus identifies i/o devices
2
Instruction Cycle
Program counter (PC) contains address of the in-
struction being executed
Instruction register (IR) contains the instruction
being interpreted
Fetch-execute cycle: The steps that the control
unit carries out in executing a program are:
1. Fetch the next instruction to be executed
from memory
2. Decode the opcode
3. Read operand(s) from main memory, if any
4. Execute the instruction and store results
5. Go to step 1
Opcode: machine language code (syntax)
Decoding Determine the type, operation and ope-
rand(s) of an instruction
4
Instruction Types
Formats: Instructions are represented as sequenceof fields. ’Code’ is usually 1 byte long and lengthof the others depends on ’Code’
Format 1: Code (ex: HLT)
Format 2: Code Address (ex: JMP $0123)
Format 3: Code Data (ex: ADD R, $01)
Format 4: Code Address1 Address2(ex: MOV $0123, $0200)
Register Transfer Language (RTL) Instructionsare sequences of microinstructions that executewithin one clock pulse.
Types:
• Arithmetic: SUB R1, R2
• Logic: XOR R, $1010
• Transfer: MOV R1, R2
• Branching: JNE $3210
• Control: CLA5
Fetch-Execute Cycle
(Example)
Step 0: Actual state of CPU
MAR
MDR
Control
OpCode OpAddr
RW
DS
ALUHZN
MAIN
MEMORY
Program
$002E: ...$0030: ADD$0032: $0036$0034: HLT$0036: $0001$0038: ......
...$05
$0030
PC (Program Counter) = $0030, A = $0005
Step 1: Fetch the instruction
MAR=$0030, PC = $0030
Control
OpAddr
RW
DS
ALUHZN
MAIN
MEMORY
Program
$002E: ...$0030: ADD$0032: $0036$0034: HLT$0036: $0001$0038: ......
...
$0030
$0099
$0032
ADD $0005
MDR = $0099 (ADD), OpCode = $0099,
PC = $00326
Fetch-Execute Cycle
(Example)
Step 2: Decode the OpCode
$0099 = ADD, then needs one operand
Step 3a: Fetch the operand
MAR=$0032, PC = $0032
Control
RW
DS
ALUHZN
MAIN
MEMORY
Program
$002E: ...$0030: ADD$0032: $0036$0034: HLT$0036: $0001$0038: ......
...ADD $0005
$0032
$0036
$0036
$0034
MDR = $0036, OpAddr = $0036, PC = $0034
7
Fetch-Execute Cycle
(Example)
Step 3b: Fetch operand value
MAR=$0036
Control
RW
DS
ALUHZN
MAIN
MEMORY
Program
$002E: ...$0030: ADD$0032: $0036$0034: HLT$0036: $0001$0038: ......
...ADD $0005$0036
$0034
$0001
$0036
MDR = $0001
Step 4: Execute and store
A = $0005
Control
RW
DS
ALUHZN
MAIN
MEMORY
Program
$002E: ...$0030: ADD$0032: $0036$0034: HLT$0036: $0001$0038: ......
...ADD $0036
$0034
$0001
$0036
$0006
MDR = $0001, A = A + MDR = $00068
Control Unit and Status Register
Control Unit controls the instruction cycle. De-
codes the instructions: interpretes the opera-
tions (OpCode) to perform according to the in-
structions formats
Status Register: ALU is connected to CU through
the status register. Each bit (called status bit)
of the status register conveys information about
the last performed operation. Example
C H N Z . . . V
C: Carry bit (1 if carry generated, 0 otherwise)
H: Halt bit (1 if processor halted, 0 otherwise)
N: Sign bit (1 if result negative, 0 otherwise)
Z: Zero bit (1 if result is zero, 0 otherwise)
. . . . . . (1 if . . . true, 0 otherwise)
V: Overflow bit (1 if overflow, 0 otherwise)
etc.
9
Implementations of Control Unit
A control unit can be implemented in two ways: by
Hardwired control: A synchronous sequential
circuit that realizes all required control ac-
tions of the CPU. That is: all functions of
the CU are implemented in hardware. With
this method, the CPU is very fast but com-
plex, very expensive and difficult to modify.
Microprogrammed control: Binary control val-
ues of the CU are stored in a special memory
called control memory (CM). CM is usually
a PLD (ROM, PLA or PAL). Each word of
CM is a microinstruction and the set of mi-
croinstructions is called microprogram. The
microprogram implements operations on the
registers and other parts of the CPU. It may
contains program steps that collectively im-
plement a single (macro)instruction. That is:
all functions of the CU is defined in a micro-
program. With this method, the CPU is sim-
ple, cheap and easy to modify but slow. Most
current processors use microprogrammed con-
trol.
10
Microprogramming
Microprogram = sequence of microinstructions de-fined to execute an instruction written in ma-chine language
Example of microprogram: An addition instruc-tion (ADD) received by the CPU is reduced to asequence of 3 microinstructions and 4 microin-structions, respectively during the fetch cycleand the execute cycle.
Fetch cycle
1. Fetch the instruction (load in CPU)
2. Decode the instruction (interpret OpCode)
3. Increment Program Counter (PC++)
Execute cycle
1. Fetch the first operand of addition
2. Fetch the second operand of addition
3. Add the operands (in accumulator register)
4. Store the result in memory
11
Register Transfer Language (RTL)
Microoperations: A microinstruction is composed
of microoperations: elementary operations per-
formed on data stored in registers or memory.
For instance, microinstruction 3 of execute cycle
of instruction ADD is composed of 2 microop-
erations:
1. Addition in A: A ← A+ MDR
2. Update status bit N : N ← An−1
RTL is used to describe microoperations. Each
microoperation involves transfering data from a
source register S to a destination register R. In
RTL, a microoperation is of the form
D ← S
where ← copies content of S into D. D is mod-
ified and S is not.
12
Register Transfer Language (RTL)
(continued)
Basic symbols for RTL
Arithmetic microoperations
Logic microoperations
Shift microoperations (page 350)13
Registers
Addressing Modes
Specify rules for accessing operations’ operands that
are stored in memory or registers, or directly pro-
vided by the instructions.
Addressing modes should be designed to
• Increase the programming flexibility and ease
• Reduce the size of generated compiler code
• Adapt the program to the operating system
• Allow easy access to operands everywhere
Effective address = absolute address of the oper-
and obtained by the application of addressing
14
Addressing Modes
Implied mode: Operand is in a register implied by
the OpCode of the instruction. Example:
ADD #31
Immediate mode: Operand is a constant value spe-
cified in the instruction itself. Example:
ADD R, #10
Register mode: Operand is in register specified in
the instruction itself. Example:
ADD S, D
Register indirect mode: Operand are is in a mem-
ory address that is content of a register specified
by the instruction itself. Example:
ADD (D), #3
15
Addressing Modes
Direct mode: Absolute address of operand is ex-
plicitly specified in instruction. Example:
ADD @1234, S
Indirect mode: Absolute address of operand is con-
tent of a memory address. Example:
ADD [@1234], #10
Relative mode: Content of PC + OpAddr. Exam-
ple:
ADD D, $S
Indexed mode: Content of an index register + Op-
Addr. Example:
ADD D, @500(S)
16
Instruction Set Architecture
Machine language: Binary language that define in-
structions. Lowest level language. Very difficult
language. Example: in CISC architecture, the
addition of 2 and 37 in machine language is
100010 00000010 00100101
Assembly language: Symbolic language in which
codes of the machine language are replaced by
symbolic names. Example: in RISC architec-
ture, the addition of 2 and 37 (contents of reg-
ister D and S) is
ADD D, S
Instruction set is the complete set of machine lan-
guage instructions of a CPU. Two major types
of instruction set architectures:
Reduced Instruction Set Computers: Small
set of simple instructions. Hardwired control
Complex Instruction Set Computers: Large
set of complex instructions. Microprogram-
med control18
Elementary Instruction Set
(continued)
Typical Logical and Bit Manipulation Instructions
Typical Shift Instructions
20
Elementary Instruction Set
(continued)
Typical Program Control Instructions
Conditional Branch Instructions Relating to Status
Bits
21
Elementary Instruction Set
(continued)
Conditional Branch Instructions for Unsigned
Numbers
Conditional Branch Instructions for Signed
Numbers
22
RISC Architectures
1. Memory accesses are restricted to load and storeinstructions
2. Addressing modes are limited in number
3. Instruction formats are all of the same length
4. Small instruction set
5. Instructions perform elementary operations
6. Large number of registers
7. Size of a program is relatively large (memory)
8. Simple control unit
9. Hardwired control
10. Fast program execution
11. Data manipulation instructions are ”register toregister”
23
CISC Architectures
1. Memory access is directly available to most typesof instructions
2. Addressing modes are substantial in number
3. Instruction formats are of different lengths
4. Large instruction set
5. Instructions perform both elementary and com-plex operations
6. Small number of registers
7. Size of a program is relatively small (memory)
8. Complex control unit
9. Microprogrammed control
10. Slow program execution
25
Example of Assembly Language Programming
under CISC architecture
Example: Write a program that compare two pos-
itive numbers x and y. Output is −1 if x < y; 0
if x = y; +1 if x > y.
MOVE R1, xMOVE R2, yMOVE R3, #0SUB R1, R2BN LessBZ ZeroMOVE R3, #+1
Less:MOVE R3, #−1
Zero:MOVE R3, #0HLT
28