38
UHD:CS2401: A. Berrached 1 The Intel x86 Hardware Organization

The Intel x86 Hardware Organization

  • Upload
    clara

  • View
    46

  • Download
    1

Embed Size (px)

DESCRIPTION

The Intel x86 Hardware Organization. AX. CS. BX. DS. CX. SS. DX. SS. IP. BP. DI. SI. SP. ALU. Flags Reg. The 8086 Processor. Execution Unit. Bus Interface Unit. Bus Control Unit. System Bus. Internal Bus. Control Unit. Instruction Queue. 64K base memory ROM. - PowerPoint PPT Presentation

Citation preview

Page 1: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 1

The Intel x86 Hardware Organization

Page 2: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 2

The 8086 Processor

BusControlUnit

Execution Unit Bus Interface UnitCSDSSSSSIP

Internal Bus

ALU

Flags Reg.

AXBXCXDX

BPDISISP

Instruction

QueueControl Unit

System Bus

Page 3: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 3

Internal Memory

256 KB of ROM and 768 KB of RAM

Conventional Memory

Upper Memory

640K memory (RAM)

128k video display area (RAM)

192k memory expansionarea (ROM)

64K base memory ROM

0 00000

640K A0000 9FFFF

768K C0000

960K F0000

Starting Address

Page 4: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 4

The Internal memory of the 8086 can be up to

1 M bytes large. How many bits are needed to express memory

addresses ?

Answer:

1 Meg = 220

=> 20-bit addresses

Page 5: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 5

The 8086 Register Set

Segment Registers: CS, DS, SS, ES General-Purpose Registers: AX, BX, CX, DX Pointer Registers SP, BP Index Registers: SI, DI Instruction Pointer IP A Flags Register

For the 8086, all registers are 16-bits large

Bits in registers are numbered right to left, starting from 0.

Page 6: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 6

Registers

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Low-order byteHigh-order byte

Example: Store 17F6H in register

0 0 0 1 0 1 1 1 1 1 1 1 0 1 1 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 7 F 6

Page 7: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 7

General-Purpose Registers

AX, BX, CX, DX all 16-bits large

AX: Accumulator register

BX: Base register

CX: Count register

DX: Data register You can address them as one word or 1 byte. E.g.:

All other registers must be accessed as the 16-bit.

AH ALAX:

Page 8: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 8

MOV instruction: copies data from one location into another.

MOV Destination, Source ; Copy source to dest.

E.g. MOV DX, CXCopies contents of register CX into register DX. The MOV instruction does not effect the source operand But Source and destination must be of same size.

MOV AH, BH;MOV AH, BX ; Can’t do

Using General-Purpose Registers

Page 9: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 9

Unising General-Purpose Registers

MOV AX, 3D2BH ; load 3D2BH into AX

MOV BH, 42H ; load 42H in high byte of BX

ADD AL, 32H ; add 32H to AL

Note: 80386 and later processor have 32-bit extended versions: EAX, EBX, ECX, and EDX

MOV EAX, FF22AA00H ; (386 & up)

Page 10: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 10

Program Segments

A segment is an area in memory that includes up to 64K bytes and begins on a paragraph boundary; ie. on an address evenly divisible by 16.

Note: When an address is evenly divisible by 16 (i.e. 10H), its least significant four bits are 0s.

=> How many bits are needed for segment starting address?

16-bits A program usually has one code segment (for the code), a

data segment (for the data used by the program) and a stack segment.

Page 11: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 11

Program Segments

The three types of segments are – code segment: contains machine instructions that

make up the program. The starting address of the code segment is stored in the Code Segment (CS) register

– data segment: contains the data used by the program. The address of the data segment is stored in the Data Segment (DS) register.

– stack segment: the stack is used for temporary storage to save data temporarily or during subroutine calls. The address of the stack register is stored in the Stack Segment (SS) register.

Page 12: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 12

Segment Registers

So when writing a program you always need to:– load CS with the starting address of the code segment

– load DS with the starting address of the data segment

– load SS with the starting address of the stack segment

All addressing within the program is done relative to segment registers.

Page 13: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 13

Relative Addressing--Offset Address

The distance in bytes from a segment address to another location within the segment is called the offset address.

the first byte of a segment is at offset address 0 the second byte is at offset 1 An offset can range from 0 to 65,535 (0000-FFFF)=> offsets are expressed as 16-bit unsigned binary numbers.

Page 14: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 14

Relative Addressing--Logical Address

Generally, memory locations are expressed as

Segment_Register:Offset

meaning that the address is “Offset” bytes from the starting address of the segment. This is what is called the logical address.

Example:

DS:17H

Page 15: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 15

Relative Addressing--Physical Address

The physical address is the actual RAM or ROM address. In the 8086, it is a 20 bit address.

How to compute the physical address of Seg_Reg:Offset ?

– Shift the Seg_Reg left one Hex digit (pad with 0 at the right).

– Add the Offset.

Page 16: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 16

Relative Addressing: Example

Data segment starting address is 027A0H

=> DS register

Because segment starting addresses must be evenly divisible by 16, the leftmost hexadecimal digit is always 0.

=> The leftmost hex digit of a segment starting address is not stored in the segment register.

0 2 7 A

Page 17: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 17

Assume we need to access data stored in the 24th byte of data segment=> offset = 17H

Logical address: DS:17H

Physical address:Start with DS: 027A

Shift left DS: 027A0

Add offset + 17 -------------- 027B7 H

Page 18: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 18

Pointer Registers

Instruction Pointer (IP) register Stack Pointer (SP) register Base Pointer (BP) register

Page 19: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 19

Instruction Pointer

The IP register always Points to the next instruction to be executed.

I.e. its contains the offset address of the next instruction that is to execute.

The address of the next instruction to be executed is formed by adding the content of IP to that of CS.

CS:IP

The IP register is always associated with the CS register.

Page 20: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 20

Stack Pointer register

The SP contains the offset address of the top of the stack

The SP register is always associated with the SS (Stack Segment) register

SS:SP

Page 21: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 21

Base Pointer register

The BP register is used to facilitate referencing parameter (on function calls)

The BP register is also associated with the SS register.

Page 22: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 22

Flags Register

A 16-bit register 80386 and later processor have a 32-bit flags

register Each bit indicates a certain status:

example: Overflow, Carry, Interrupt

Many instructions change the status of the flags Some instruction test for certain bits of the flag

register before taking action– example: JO ; jump if overflow bit is set

Page 23: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 23

Addressing of operation and data

An instruction consists of– at least one operation (e.g., ADD, MOVE)

– zero, one or more operands (to reference the data)

– Generally, the first operand is the destination

example:

MOV AX, 25 ; Immediate operand

MOV BX, AX ; register to register

Page 24: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 24

Addressing of operation and data

More examples:

MOV AL, [0034] ; indexed addressing

– Physical address of operand = DS:34H

=> the [ ] indicate that the physical address of the operand is computed by taking what’s between the

[ ] as an offset and adding it to DS

Page 25: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 25

Addressing … - Cont.

An instruction may access more than one byte at a time

e.g., MOV AX, 35F3H

MOV [1500], AX

This instruction will copy the contents of AX (i.e. 35F3H) in two 2 memory locations starting at address DS:1500.

How are the two bytes arranged?

Little endian convention: low order byte in low order memory address

Page 26: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 26

Little endian convention

Assume DS = 3146[0]H

=> DS:1500 = 32960H

32960 32961

Memory

…. ….

AX:

AH AL

F3

35 F3

35

Page 27: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 27

Instruction Operands

Some More Examples:X1 DW 0 ; Define X1 as a word

…..

MOV CX, X1 ; Move X1 to CX

MOV CX, 25 ; Move 25 to CX

MOV CX, DX ; Move content of DX to CX

MOV CX, [DX] ; Indexed addressing

=> to get actual address of operand: use content of DX as an offset and add it to DS

=> actual address = DS + DX

Page 28: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 28

Debug program

A debugger program for x86 Assembly used to:

– enter machine code

– enter assembly code

– write small programs (.COM files)

– debug assembly programs

Page 29: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 29

DEBUG Commands

– A: Assemble assembler instructions into machine code

– D: Display contents of memory at a specific address

– E: Enter data/instruction into memory

– G: (Go) run the program

– T: Trace

– P: Proceed: execute a set of instruction

– R: display contents of Registers

– W: Write (I.e. save) a program into disk

– Q: Quit

See Appendix E of Text book.

Page 30: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 30

DEBUG

Few Basic Rules

– case insensitive

– uses the colon format (e.g., segment:offset)

– uses hexadecimal notation

– use a space to separate parameters

Page 31: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 31

Debug - Cont.

Examples:– D DS:200 <RTN>

– E CS:100 B8 23 01 01 05 25 00 <RTN>

– R <RTN>

• AX= BX= …………..

• …………..

• nnnn:0100 B82301 MOV AX, 0123

Page 32: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 32

D: Display Memory Content

Address | Hex representation | ASCII

xxxx:xx10 xx…....xx-xx..…..xx x…….x

xxxx:xx20 xx…....xx-xx..…..xx x…….x

xxxx:xx30 xx…....xx-xx..…..xx x…….x

…...

xxxx:xx80 xx…....xx-xx..…..xx x…….x

Page 33: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 33

Machine Language Example

Machine Lang Assembly Lang

B82301 MOV AX, 0123

052500 ADD AX, 0025

8BCB MOV CX, BX

90 NOP

Page 34: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 34

Debug Operations

Keying in program instructions Executing program instructions Displaying memory contents Correcting an entry

Page 35: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 35

ML Example: Defined data

E CS:100 A1 00 02 03 06 02 02

…….

E DS:0200 23 01 25 00 00 00

…….

To view code: D CS:100,105 <RTN>

To view data: D DS:200,205 <RTN>

Page 36: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 36

An assembly Language Example

Assemble Command:A 100 <RTN>

MOV CL, 42

MOV DL,2A

ADD CL, DL

NOP

Page 37: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 37

An assembly .. - Cont.

Unassemble commandU 100,106 <RTN>

xxxx:0100 B142 MOV CL, 42

xxxx:0102 B22A MOV DL, 2A

xxxx:0104 00D1 ADD CL,DL

xxxx:0106 90 NOP

Page 38: The Intel x86 Hardware Organization

UHD:CS2401: A. Berrached 38

More on Debug

If you are executing a program again within the DEBUG make sure to reset IP register to 100.– R IP

: 100

Saving a program from within debug• use A or E to key in the code

• N filename.COM

• clear BX

• replace CX with the size of the program

• W