The

Group

DN8000K10 Virtex-4 Based ASIC Prototyping Engine

1010 Pearl Street, Suite #6La Jolla, CA 92037-5165

Phone: 858.454.3419Fax: 858.454.1728

E-Mail: sales@dinigroup.comWeb: http://www.dinigroup.com

For Technical applications and Sales Support, Call 858.454.3419

The DINI Group reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.

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The

GroupDN8000K10 'Son of Monster'

Xilinx Virtex-4 Based ASIC Prototyping Engine

Product BriefFebruary 2006Ver. 1.1

Description

OverviewThe DN8000k10 is a complete logic emulation system that enables ASIC or IP designers a vehicle to prototype logic and memory designs for a fraction of the cost of existing solutions. The DN8000k10 is stand-alone or hosted via a USB interface. A single DN8000k10 configured with 14 Xilinx Virtex-4, XC4VLX200’s and 2 XC4VFX100’s can emulate up to 24 million gates of logic as measured by LSI. This number does not include the embedded memories and multipliers resident in each FPGA. The DN8000k10 achieves high gate density and allows for fast target clock frequencies by utilizing FPGA's from Xilinx's Virtex-4 FPGA family for logic and memory. All FPGA resources are available for the target application. Any subset of FPGA’s can be stuffed.

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• USB2.0-hosted logic prototyping system with 2- 16 Xilinx Virtex-4 FPGA's - 14 'LX' (FF1513): • 4VLX100-10,-11,-12 • 4VLX160-10,-11,-12 • 4VLX200-10,-11 - 2 'FX' family (FF1152): • 4VFX40-10,-11,-12, -11x • 4VFX60-10,-11,-12, -11x • 4VFX100-10,-11,-12, -11x - 100% FPGA resources available for user application• Nearly 23.7M ASIC gates (LSI measure) with 14 LX200’s and 2 FX100’s• FPGA to FPGA interconnect is single-ended or LVDS - 350Mhz differential chip to chip DDR (700Mb/s) - Reference designs for integrated I/O pad ISERDES/OSERDES • 10x pin multiplexing per LVDS pair - Greatly simplified logic partitioning - Source synchronous clocking for LVDS - Main Bus (MBUS) connects all LX FPGA’s (80 +64 = 144 signals) • Single-ended • Reduced capacitance via quickswitches • 80 of these MBUS signals connected to FX FPGA’s• Synplicity Certify™ models for partitioning assistance• 4 separate DDR2 SODIMMs (200MHz) - 1 DIMM each connected to LX FPGA’s: 1,2,13,14 - 64-bit data width, 200MHz operation - PC2-3200/PC2-4200 - Addressing/power to support 4GB in each socket - DDR2 Verilog/VHDL reference design provided (no charge) - DDR2 SODIMM data transfer rate: 25.6Gb/s - Alternate pin compatible memory cards available (consult factory for availability): • QDR SSRAM, Mictor • RLDRAM, SSRAM

• Two PowerPC 405 Cores per FX FPGA (4 total with both FX FPGA’s stuffed) - Embedded 350 MHz Harvard Architecture - Hardware Multiply/Divide Unit - Thirty-Two 32-bit General Purpose Registers - 16 KB 2-Way Set-Assoc. Instruction Cache - 16 KB 2-Way Set-Associative Data Cache - Memory Management Unit (MMU) - Timer Facilities• 3 board-level global clock networks (GCLK0, GCLK1, GCLK2) - Separate programmable synthesizers for each network • User configurable via SmartMedia or USB - Separate global reference clock network for IDELAY chain delay resolution (REFCLK) - Global clocks networks distributed differentially and balanced - Single-step clocking available on each global clock network - 3 external differential clock inputs can be multiplexed in to global clock networks (via SMA’s)• 4 independent clock sources for each FX chip - 2 fixed low-jitter oscillators - 2 programmable synthesizers• Gigabit serial I/O interfaces: - 2, 10G, small form factor XFP modules per FX FPGA (4 total) • 10.3 Gb/s (when available from Xilinx) - 2, Small form factor SFP modules per FX FPGA (4 total) - SMA connectors for off-board cabling to 4 channels of rocketI/O per FX FPGA (8 total) • 10.3 Gb/s (when available from Xilinx) - Samtec cables for off-board cabling of 8 channels of rocketI/O per FX FPGA (16 total) - Clocking options available for standard communications data rates for RocketIO: • OIF 10G BP, 10G Ethernet • OC-192, 1x, 2x, 4x Fibre Channel • 10G Fibre Channel, XAUI

• Serial Rapid IO Type 1,2,3, Serial ATA Type 1,2 • PCI Express, Infiniband • OIF SxI-5, OIF SFI-4.2 • OC-48, 1000BaseX, OC-12, Aurora - Ability to use embedded Ethernet MAC with SFP and XFP modules (FX FPGA)• Flexible customization via daughter cards - Signal voltage set by daughter card • 2(or 3) independent banks, +1.5V to +3.3V - 4, 400-pin Meg-Array connectors (FCI) • FPGA’s 3,7,11,15 • 93 LVDS pairs + clocks (or 186 single-ended) - 4, 300-pin Meg-Array connectors (FCI) • FPGA’s 3,4,8,15 • 62 LVDS pairs + clocks (or 124 single-ended) - 350MHz on all signals with LVDS - Reset, presence detect - Supplied power rails (fused): • +12V (24W max) • +5V (10W max) • +3.3V (10W max) - Pin multiplexing to/from daughter cards using ISERDES/OSERDES and LVDS (up to 10x)• Fast and Painless FPGA configuration - SmartMedia, Compact FLASH, and/or USB - Integrated sanity checks on configuration files - Accelerated configuration readback • 4 separate parallel readback busses• Custom base plate (standard) and optional rackmount chassis - Protection from those drooling engineers• 4, RS232 ports for PowerPC or embedded uP debug - Accessible from all FPGA’s via Config FPGA• Full support for embedded logic analyzers via JTAG interface - ChipScope, ChipScope Pro - IdentifyTM from Synplicity• Enough status LED’s to blind an OX

Features

DN8000K10 Virtex-4 Based ASIC Prototyping Engine

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DN8000K10 Virtex-4 Based ASIC Prototyping Engine

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Virtex-4 FPGA’s from XilinxHigh I/O-count, 1513-pin, flip-chip BGA packages for the LX chips and 1152-pin flip-chip BGA’s for the FX chips are utilized. Abundant fixed interconnects are provided between the FPGA's. All pins of all banks of each FPGA are utilized. FPGA to FPGA busses are routed and tested LVDS, run at 350MHz+ but can be used single-ended at a reduced speed. Example designs utilizing the integrated ISERDES/OSERDES with DDR for pin multiplexing are included. A 144-pin main bus (MBUS) is connected to all FPGA’s, excepting the FX FPGA’s, which have connectivity to 80 of these main bus signals.

Daughter cardsNine separate 300/400-pin FCI MEG-Array connectors allow for customization with daughter cards. Signals to/from these cards are routed differentially, and can run at the limit of the FPGA: 350MHz. Clocks, resets, and presence detection, along with abundant power are included in each connector.

MemoryFour separate DDR2 SODIMM sockets are connected to FPGA’s 1, 2, 13, 14. Each socket is tested to 200MHz with a DDR2 SODIMM. Standard, off-the-shelf DDR2 memory DIMM’s (PC2-3200/PC2-4200) work nicely and we can provide these for a small charge. We have developed alternative SODIMM’s that can be stuffed into these positions. Consult the factory for more details, but the list includes FLASH, SSRAM, QDR SSRAM, RLDRAM, and others.

High Speed Serial I/O InterfacesTwo FX-series chips are placed in positions 0 and 12 and can be stuffed with FX60’s or FX100’s. The rocketI/O’s from each chip are attached to the following high-speed serial interfaces:

2 SFP sockets (1 MGT each) 2 XFP sockets (1 MGT each) 4 separate TX/RX via SMA’s (4MGT’s) 2 Samtec connectors for board-to-board cabling (4 MGT’s each)

Easy Configuration Via SmartMedia/Compact FLASH/USBThe configuration bit files for the FPGA's are copied onto a 128-megabyte SmartMedia or Compact FLASH card (provided) and an on-board Cypress microprocessor controls the FPGA configuration process. FPGA configuration can also be controlled via the USB interface. Visibility into the configuration process is enhanced with an RS232 port. Sanity checks are performed automatically on the configuration bit files, streamlining the configuration process. FPGA configuration occurs at the fastest possible SelectMap frequency - 48MHz. Multiple LED's provide instant status and operational feedback.

As always, reference material such as DDR SDRAM controllers, flash controllers, and PowerPC code is included (in Verilog, VHDL, C) at no additional cost.

Easy Expansion via daughter cardsThe DN8000k10 is easily adaptable to all applications via daughter cards. FCI Meg-Array connectors are utilized in either 300-pin or 400-pin versions and FPGA signals are routed differentially to these connectors, but can be used single-ended. Clocks and fused power are provided on each connector. Clocks can be driven from a daughter card to the global clock networks of the DN8000k10. Signals are routed from the FPGA’s on a bank basis, and the daughtedaver card selects the I/O voltage of the connector by driving the VccI/O of the FPGA bank. The I/O voltage ranges are +1.5V to +3.3V.

Max(100% util)*

(1000's)

Practical(60% util)*(1000's)

Blocks(18kbits)

Total (kbits)

Total (kbytes)

LX100 -10,-11,-12 49,152 98,304 1,380 830 960 10 96 0 240 4,320 540LX160 -10,-11,-12 67,584 135,168 1,890 1,130 960 10 96 0 288 5,184 648LX200 -10,-11 89,088 178,176 2,490 1,490 960 10 96 0 336 6,048 756FX40 -10,-11,-12 18,432 36,864 520 310 448 10 32 2 144 2,592 324FX60 -10,-11,-12 25,280 50,560 710 430 576 10 128 2 232 4,176 522FX100 -10,-11,-12 42,176 84,352 1,180 710 768 10 160 2 376 6,768 846

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Slices or LE's

FF's

Po

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rPC

Blo

cks Memory

Vir

tex-

4

LX

FX

Gate Estimate

Max

I/O

's

FF

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I/O pad

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FPGA

DN8000K10 Virtex-4 Based ASIC Prototyping Engine

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DN8000K10 Virtex-4 Based ASIC Prototyping Engine

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Optional 19” Rackmount Chassis

The DN8000k10 comes standard mounted to a base plate. An optional 19”, 4U-high Rackmount chassis is available. The photos below show the DN8000k10 installed in this optional chassis. The top plate is not shown.

The chassis is shipped with a Zippy Technology Corporation power supply rated at 600 watts with an AC input voltage range of 100~240 VAC. The front panel has an LCD display with an ON/OFF switch for power, and momentary switches for HARD RESET and LOGIC RESET. On the front panel connectors support the following functions: MCU RS232 – FPGA configuration and control USB – Hosting and/or FPGA configuration User RS232 (2,3,4) – User RS232 ports (requires UART in FPGA) Compact FLASH – FPGA configuration

The back panel has the following connectors:

16 SMA’s – Directly connected to 4 Rocket I/O MGT’s 2 -- SFP Modules 2 -- XFP Modules

Bottom

Top

DN8000K10 Virtex-4 Based ASIC Prototyping Engine

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DN8000K10 Virtex-4 Based ASIC Prototyping Engine

4the DINI group

Block Diagram

SMARTMEDIAFPGA

CONFIGURATION(128 MB)

Reset

0 1 2 3

4 5 6 7

8 9 10 11

12 13 14 15

COMPACT FLASHFPGA

CONFIGURATION

9393

9393

9393

6262

6262

6262

6262

6262

6262

93

64

80

64

80

64

939393

9393

6262

9393

9393

6262

1

9393

6262

9393

1

1

1

1

1

11

= Single ended or when paired, differential = FX100

DN8000K10 Block Diagramv1.03

1

3

6

1

1

93 93 62 62

116 116

116 116

62 62 93 93

93 93 62 62 62 62 93 93

93 93 62 62 62 62 62 62

62 62

62 62

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

31 31

MBUS80-2

MBUS64-3

MBUS64-1

MBUS80-1

MBUS64-2

441

441

8

SMA

SMA

10Gb/s

10Gb/s

10Gb/s

10Gb/s

5Gb/s

5Gb/s

CY7C68013uP Configuration

controller

ConfigFPGALX80

(FF1148)

FPGA0

Virtex-4FX60/100(FF1152)

FPGA12

Virtex-4FX60/100(FF1152)

FPGA1

Virtex-4LX100/160/200

(FF1513)

FPGA2

Virtex-4LX100/160/200

(FF1513)

FPGA3

Virtex-4LX100/160/200

(FF1513)

FPGA5

Virtex-4LX100/160/200

(FF1513)

FPGA4

Virtex-4LX100/160/200

(FF1513)

FPGA6

Virtex-4LX100/160/200

(FF1513)

FPGA7

Virtex-4LX100/160/200

(FF1513)

FPGA9

Virtex-4LX100/160/200

(FF1513)

FPGA8

Virtex-4LX100/160/200

(FF1513)

FPGA10

Virtex-4LX100/160/200

(FF1513)

FPGA11

Virtex-4LX100/160/200

(FF1513)

FPGA13

Virtex-4LX100/160/200

(FF1513)

FPGA14

Virtex-4LX100/160/200

(FF1513)

FPGA15

Virtex-4LX100/160/200

(FF1513)

BootEPROM

M0 M1

JTAG

IdentifyTM orChipscope

(PC4)

RS232serialport

USB 2.0

48 MHz

SRAM128Kb x 8

Flash1 M x 8

MEG

Arra

y Ex

pans

ion

Con

nect

or (3

00-p

in)

MEG

Arra

y Ex

pans

ion

Con

nect

or (4

00-p

in)

MEG Array ExpansionConnector (300-pin)

MEG Array ExpansionConnector (300-pin)

DDR2 SODIMM

(4GB max)

DDR2 SODIMM

(4GB max)

DDR2 SODIMM

(4GB max)

DDR2 SODIMM

(4GB max)

MEG

Arra

y Ex

pans

ion

Con

nect

or (4

00-p

in)

MEG

Arra

y Ex

pans

ion

Con

nect

or (4

00-p

in)

MEG

Array ExpansionC

onnector (300-pin)M

EG Array Expansion

Connector (300-pin)

MEG

Arra

y Ex

pans

ion

Con

nect

or (4

00-p

in)

RS232

4 SerialPorts

(Tx/Rx)

64-bitbus switch

80-bitbus switch

64-bitbus switch

80-bitbus switch

64-bitbus switch

M2 M3

FX0_MGTCLK0

(Rx/Tx)

FX0_MGTCLK1

Daughter Card 0

25.5MHz

25MHz

ICS84321

SAMTEC

MGT's

Roc

ketI/

O

XFPSocket

XFPSocket

XFPSocket

XFPSocket

SFPSocket

SFPSocket

SFPSocket

SFPSocket

(Rx/Tx)

SAMTEC

ICS84321

PLL Config

PLL Config

FX1_MGTCLK0

FX1_MGTCLK1

Daughter Card 3

25.5MHz

25MHz

OSC

OSC

ICS84321

ICS84321FLASH, RLDRAM, SSRAM, Mictor compatible SODIMM's available

+1.5V to +3.3V I/O

+1.5V to +3.3V I/O

+1.5

V to

+3.

3V I/

O+1

.5V

to +

3.3V

I/O

+1.5

V to

+3.

3V I/

O+1

.5V

to +

3.3V

I/O

+1.5V to +3.3V I/O+1.5V to +3.3V I/O

+1.5

V to

+3.

3V I/

O

5Gb/s

5Gb/s

MGT's

RocketI/O

OSC

OSC

PLL ClockSynthesizers

Reference Clock

Ext. Clock(SMA's)

Config PROM

Control

Clock M

ux

Single Step Clocks

LCDControlPanel

GCLK0

GCLK2

GCLK1

Ext. Clock(SMA's)

Ext. Clock(SMA's)

ICS8442

ICS8442

ICS8442

ICS8442 14.318MHz

16.66MHz

25.00MHz