The Development of an ATCA-based Digitizer Board– for ILC Beam Instrumentation R&D –

30/4/2007 ATCA Workshop 1

Alexei SemenovManfred Wendt

Fermilab, AD-Instrumentation

The International Linear Collider

30/4/2007 ATCA Workshop 2

beam energy = 2 x 250 GeV

luminosity L = 2 x 1034

rep. frequency frep = 5 Hz

macro pulse length tpulse = 800 µs

# of bunches per pulse = 2820

bunch spacing Δtb = 369 ns

bunch charge = 3.2 nC

bunch length σz ≈ 300 µm

vert. emittance γ εy* = 0.04 mm mrad

RMS energy spread = 0.1 %

βx* (IP) = 21 mm

βy* (IP) = 0.4 mm

hor. beamsize (IP) σx = 500 nm

vert. beamsize (IP) σy = 5 nm

ILC Beam Parameters (nominal):

Standardization & High Availability

The International Linear Collider (ILC):• A multibillion dollar HEP project with ~ 80 km beam-lines.• Operates 24/7 over the year, expecting a better yield than HEP

accelerators of today (uptime ~ 60-70 %).• Should benefit from new technologies for front-end and data

acquisition hardware, beyond VME/VXI, CAMAC,…• Needs a very strict standardization for thousands of electronics

crates, to manage compatibility, maintenance, simplify the overall installations, and “solve the distribution problem”.

ILC R&D Proposal:• ATCA is chosen as baseline HA platform for ALL electronics

hardware (instrumentation, front-ends, data-acquisition, controls)!

• Initiate ATCA R&D activities in various ILC areas, includingbeam instrumentation.30/4/2007 ATCA Workshop 3

ILC Beam Instrumentation

• ~ 2000 Button/stripline BPM’s (10-30 / 0.5 µm resolution)• ~ 1800 Cavity BPM’s (warm, 0.1-0.5 µm resolution)• 620 Cavity BPM’s (cold, part of the cryostat, ~ 1 µm)• 21 LASER Wirescanners (0.5-5 µm resolution)• 20 Wirescanners (traditional)• 15 Deflecting Mode Cavities (bunch length)• ~ 1600 BLM’s• Many other beam monitors, including toroids, beam phase

monitors, wall current monitors, faraday cups, OTR & other screen monitors, sync light monitors, streak cameras, feedback systems,etc.

• Read-out, control and data acquisition electronics for all beam monitors

– ILC beam instrumentation requires ~ 16000 input channels,i.e. ~ 1000 ATCA 16-channel digitizer boards, located in ~ 250 crates.

30/4/2007 ATCA Workshop 4

Signal Processing

30/4/2007 ATCA Workshop 5

369 ns

~ 1 ms

1 2 3 4 5 6 …. ~ 3000bunch # 2 3 4 5 61

200 ms

~ 1 ps

• Broadband analog pickup signals– Pulse signals have 0.1-1 ns width.– Linearity, reproducibility, S/N, precision,

sensitivity (~ 0.0002 dB).– Minimum analog signal processing

• Digital signal processing issues:– Clean analog path to the ADC input – Low jitter clock signals (< 500 fs)– Undersampling, sufficient analog bandwidth– Trigger, synchronization, data management,

time stamping, etc.

ILC bunched beam ILC beam pickup pickup analog signals:•before signal processing

• after signal processing

NML Beamline Instrumentation

beam-line for advanced beam instrumentation, e.g. EOS, Laser-wire, OTRI, cavity BPM’s,…

RF-

gun

capture cavities1 & 2

3.9

Ghz

cav

doub

let

triplet quadsbeamtrans.

bunch compressor dipole

low energyinjector dumpILC Module 1

O OTSSO

BOCBYF

TB

T

O YO

O S O

T

PS O OC

S

P

T S YO

S

O

S

S O

T

doublet

S O BT O S OS

SO

T

high energy intensity dump

triplet

doublet

dog leg test beam-line (TBD)

BC

HOM couplers

T

Beam current / bunch charge (T:toroid)

Time-of-flight or beam phase monitor

Synchrotron light bunch length monitor

BPM (B:button, S:stripline, C:cavity, PS:perp. stripline)

Screen monitor (Y:YaG, O:OTR, C:CTR, S:slit, F:F-cup)

S

S S

doublet dipole

dipoledoublet

30/4/2007 ATCA Workshop 6

Basic Design Guidelines

• Primary application: button BPM signal processing

– ~ 1 GHz analog bandwidth– 500 MS/s sampling rate– Multichannel ADC/DAC board,

also for feedback applications– Analog inputs through zone 3

coaxial connectors– Clock and trigger-signal

distribution

30/4/2007 ATCA Workshop 7

analog section

16-ch digitizer

coax connection

Digitizer Board Block Diagram

30/4/2007 ATCA Workshop 8

10/1

00/1

,000

ET

HE

RN

ET

Base Interface10/100/1,000MB

Ethernet

Fabric InterfaceFull Mesh

Digital IO:Ext Clock,Ext Trigger,Ext Gates,Front-EndControl

16 Analog Inputs

&

16 Analog Outputs

Ext CLK

Int CLKClock Synthesizer

and Distribution

AD9510

FPGASTRATIX IIEP2S60F1020

Fabric & Base Ethernet Interface

NIOS II

DDR2 SDRAM

1GB

Hot Swap Power Controller,Low Noise, Slew Control

Spread Spectrum DCDC

Power48V DC200W

FLASH&

Config

EPC16

DDR2Controller

ATCABackplane

48V A48V B

ATCARear Transition

Board

10/1

00/1

,000

ET

HE

RN

ET

IPM

C

Intelligent Platform

Management Bus IPMB-AIPMB-B

4 +4 ChannelsADC&DAC

Module

4 +4 ChannelsADC&DAC

Module

4 +4 ChannelsADC&DAC

Module

4 +4 ChannelsADC&DAC

Module

1GSPS Serial LinkFull Mesh

4-Channel ADC/DAC Section

30/4/2007 ATCA Workshop 9

FPGASTRATIX IIEP2S60F1020

ADC&DAC Interface

Data Flow control

Signal Processing

Digital IO:Ext Clock,Ext Trigger,Ext Gates,Front-EndControl

Analog Inputs

ch1

ch2

ch3

ch4

Ext CLK

Int CLK

Clock Synthesizer and

Distribution AD9510

ADC ADS5463

12bit, 500MSPSPA

ADC ADS5463

12bit, 500MSPSPA

ADC ADS5463

12bit, 500MSPSPA

ADC ADS5463

12bit, 500MSPSPA

DAC AD9736

14bit, 1200MSPS

DAC AD9736

14bit, 1200MSPS

DAC AD9736

14bit, 1200MSPS

DAC AD9736

14bit, 1200MSPS

FLASH &ConfigEPC16

DDR2 SDRAM

32M

DD

R2

Con

trol

ler

ATCARear Transition

Board

Analog Outputs

ch1

ch2

ch3

ch4

DDR2 SDRAM

32M

DDR2 SDRAM

32M

DDR2 SDRAM

32M

1GSPS Serial links for module

communicationDD

R2

Con

trol

ler

LV

DS

LV

DS

ADC Chip

Texas Instruments ADS5463:• 12-bit resolution• 2 GHz analog bandwidth (- 3 dB)• 500 MS/s sampling rate• LVDS output• ~ 2.2 W power consumption

30/4/2007 ATCA Workshop 10

DAC Chip

Analog Devices AD9736:• 14-bit resolution• 1200 MS/s sampling rate• LVDS output• Build in self-test

for data transfer• 380 mW power consumption

30/4/2007 ATCA Workshop 11

Design Issue #1: Data Rate

• ADC FPGA: 500 MS/s• FPGA DAC: 1200 MS/s

(max)• FPGA DDR2RAM: 633 MS/s• Fabric Interface: 1000 MS/s• Base (Ethernet) Interface:

10/100/1000 MB

30/4/2007 ATCA Workshop 12

Timing Budget Analysis of 500MHz System

Clock

Data

2.0ns

Transmit Channel-to-Channel SkewClock Duty Cycle DistortionPLL Output JitterBoard (Layout) SkewSampling Window

Possible Solutions:• LVDS• Dynamic Phase

Alignment (DPA)• Dynamic Auto-

Calibration Circuit

Design Issue #2: Clock Jitter

ADC & DAC clock jitter:How to reach 100-500 fs RMS ?

30/4/2007 ATCA Workshop 13

Quantization Limit

Signal-to-Noise Ratio Due to Aperture Jitter Amplitude Error vs. Clock Jitter

Clock Signal Distribution

AD9510:• Additive output jitter 275 fs RMS• Input reference frequencies up to 250 MHz• 4 independent 1.2 GHz LVPECL clock

outputs• 4 independent 800 MHz LVDS clock outputs• Programmable divider for each output• Fine delay adjust for two LVDS outputs• Serial mode control port

30/4/2007 ATCA Workshop 14

PECL Clock Oscillator

65MHz Si530300fs

External Clock from Rear Transition Board

MUXICS853054

238 fs

Clock Selectfrom FPGA

PECL VCXOSi550350fs

PLL

Clo

ck D

istr

ibut

ion

AD

9510

27

5fs

LoopFilter

To DAC: Ch1Ch2Ch3Ch4

(PECL,1200MHz)

Osc. ClockEnable

Serial Mode Control

from FPGA

Clock A&

Clock B

from ATCA Backplane

To ADC: Ch1Ch2Ch3Ch4

(LVDS,500MHZ)

Backplane ClockEnable

Clock A&

Clock Bto ATCA BackPlane

Design Issue #3: Clean DC Power

How to reduce EMI from the ATCA - 48 VDC power converters?

30/4/2007 ATCA Workshop 15

~40 dB reduction~ 200µV !

Linear TechLinear TechLT1683LT1683

• Slew Rate Controlled MOSFET Switches

40 dBm vs 55 dBm

• Spread Spectrum Clock for DC-DC Converters

Board Layout (Design in Progress)

30/4/2007 ATCA Workshop 16

4 ADC/DAC Modules

Base & Fabric Interface

DC_DC Converters

Analog IOHARTING

COAX&

Digital IO

PreAmps &Drivers

Personal Remarks

• ATCA vs. other HA platforms (VXS, VITA46, etc.)• Commercial vs. home-brew digitizer board development• Commercial ATCA instrumentation boards???• No VME/VXI compatibility!• Good, but expensive mechanics. Very noisy fans!!!• Long delivery times for commercial ATCA hardware!• Unknown future of the ATCA standard?• Many disadvantages as instrumentation platform:

– HA use for RF and microwave signals is limited (in principle!).– No high-density coaxial connectors available, space limitations

in zone 3.– - 48 VDC requires many noisy DC-DC converters.

30/4/2007 ATCA Workshop 17

Backup Material

ATCA development equipment (Motorola ARSCH-084 kit & other stuff)• 1x AXP1405 Shelf, 14 slot 19”, 12U• 2x ATCA-F101 system controller & switch blade (hub)• 2x 123065 ATCA 717 processor blade,

Intel Pentium M, 1.8 GHz, 2 GB memory, 4x PMC slots• 1x MCPBL0040B01Q ATCA CPU blade,

Dual Xeon, 2 GHz, 1x AMC slot • 2x 120980 ACC/ATCA-715 CPU blade• 1x HDD-IDE-0040 HDD for CPU blade, 30 GB• 1x SA-BBS-MV-ATCA-F101 BBS SW & MV GCE 4.0 for ATCA-F101• 2x SA-BBS-MV-ATCA-717 BBS SW & MV GCE 4.0 for ATCA-717

30/4/2007 ATCA Workshop 18

ADC Schematics (1 Channel)

30/4/2007 ATCA Workshop 19

C20

10pF

In_ADC

R6 50

L2 10uH12

adc_pD11

AV_+5V

adc_AVdd_+3.3V

adc_pD[11:0]

adc_nD10adc_pD10

adc_pD9adc_nD9

adc_nD7adc_pD8adc_nD8

adc_clk_p

adc_nD6adc_pD7

adc_nD5adc_pD6

adc_pD4adc_nD4adc_pD5

adc_pD3adc_nD3

adc_pDrdy

adc_pD2adc_nD2

adc_nD0adc_pD1adc_nD1

adc_pD0

AV_+3.3V

adc_AVdd_+5V

adc_clk_n

3V3

adc_pOVRadc_nOVR

adc_nD[11:0]

adc_nDrdy

+Ain16

-Ain17

+5V

_AV

dd1

3

+5V

_AV

dd2

8

+5V

_AV

dd3

13

+5V

_AV

dd4

14

+5V

_AV

dd5

19

+5V

_AV

dd6

21

+5V

_AV

dd7

23

+5V

_AV

dd8

25

+5V

_AV

dd9

27

+5V

_AV

dd10

31

+3V

3_A

Vdd

135

+3V

3_A

Vdd

237

+3V

3_A

Vdd

339

+3V

3_D

Vdd

11

+3V

3_D

Vdd

251

+3V

3_D

Vdd

366

gnd1

2

gnd2

7

gnd3

9

gnd4

12

gnd5

15

gnd6

18

gnd7

20

gnd8

22

gnd9

24

gnd1

026

gnd1

128

gnd1

230

gnd1

332

gnd1

434

gnd1

536

gnd1

638

gnd1

740

gnd1

852

gnd1

965

+clk10

-clk11

+D0 54

+D1 56

+D258

+D360

+D462

+D5 64

+D6 68

+D7 70

+D8 72

+D9 74

+D10 76

+D11 78

-D0 53

-D1 55

-D2 57

-D3 59

-D4 61

-D5 63

-D667

-D769

-D871

-D973

-D10 75

-D11 77

+Drdy80

-Drdy 79

nc3

43

nc444 nc545 nc646 nc747 nc848 nc949 nc1050 nc1

4nc

25

+OVR 42

-OVR41

RSV129 RSV233

Vref6

In+

In-

PD

Vee(-2.5V)

Vcc(+2.5V)

CM1CM2

Out+

Out-

U1

THS4509

1

2 3

4

5 6 7 8

9

1011

12

13 14 15 16

C2

0u1

R7

50

+C14

100u0AV1_+5V

C13

0u1

+C18

100u0

C9

0u1

C17

0u1

C12

0u1

C8

0u1

C11

0u1

C15

0u1

R8 250

R3 50

R9

50

+C5

100u0

C6

0u1

adc_nD11

C7

0u1

R4

50

C4

0u1+

C1

100u0

R1 250

C21

0u1

C16

0u1

C10

0u1

L3 10uH12

R2 250

L1 10uH12

C19

0u1

R5 250

C3

0u1

DAC Schematics (1 Channel)

30/4/2007 ATCA Workshop 20

Title

Size Document Number Rev

Date: Sheet of

14bit 1200MSPS DAC1. 00

ATCA 12 bits 500MHz Digitizer

B

68 92Friday, March 09, 2007

dac_nD6dac_pD6dac_nD7dac_pD7dac_nD8

dac_IRQ

dac_pD8dac_nD9dac_pD9dac_nD10dac_pD10

AVcc_-5V

dac_nD11

AVcc_+5V

dac_pD11

dac_DV_3.3V

dac_DV_1.8V

dac_agnd

dac_reset

dac_dclkout_p

dac_DV_1.8V

dac_nD12

dac_dgnd

dac_DV_3.3V

dac_clkgnd

dac_dgnd

dac_pD12

dac_asgnddac_clkgnd dac_dgnd

dac_agnd

dac_CV_1.8V

nOut_DAC

dac_nD13

dac_CV_1.8V

dac_pD13

dac_clkgnd

dac_agnd

dac_SCLK

dac_DV_3.3V

dac_CS

dac_AV_3.3V

dac_agnd

dac_DV_1.8V

AV_+3.3V

dac_AV_3.3Vdac_CV_1.8V

dac_AV_3.3V

3V3

L386 100uH

C2987

1n

L38110uH1 2

+C3009

100u0

+C2995

100u0

dac_SDIO

In+

In-

PD

Vee(-2.5V)

Vcc(+2.5V)

CM1CM2

Out+

Out-

U234

THS4509

1

2 3

4

5 6 7 8

9

1011

12

13 14 15 16

C2993

0u1

C3004

0u1

R1041 350

C2996

0u1

C2999

0u1

R1036 350

C3007

0u1

R1037 100

C3012

0u1

R1039 100

C3011

0u1

C2998

0u1

C3008

0u1+

C3003

100u0

C2990

0u1

+

C2991

100u0dac_dclkout_n

C3002

0u1

C2992

0u1

+ C2989

100u0

2V5

L38210uH1 2

C2994

0u1

C3010

0u1

+C3000

100u0

R1040

29

L383 100uH

L384 100uH

R1042

50

C3013

0u1

C3006

0u1

C2988

0u1

C2997

0u1

U233

AD9736

CV

dd18

_4B

1

CV

dd18

_5B

2

CV

dd18

_6B

3

agnd

7B

4ag

nd8

B5

agnd

9B

6

Ioutb2B7

Iouta2 B8

agnd

10B

9ag

nd11

B10

agnd

12B

11

AV

dd33

_3B

12

AV

dd33

_4B

13

I120 B14

CV

dd18

_1A

1

CV

dd18

_2A

2

CV

dd18

_3A

3

agnd

1A

4ag

nd2

A5

agnd

3A

6

Ioutb1 A7

Iouta1A8

agnd

4A

9ag

nd5

A10

agnd

6A

11

AV

dd33

_1A

12

AV

dd33

_2A

13

nc1 A14

CV

dd18

_7C

1

CV

dd18

_8C

2

CV

dd18

_9C

3

agnd

13C

4ag

nd14

C5

agnd

15C

6

Ioutb3C7

Iouta3C8

agnd

16C

9ag

nd17

C10

agnd

18C

11

AV

dd33

_5C

12

AV

dd33

_6C

13

VrefC14C

Vdd

_gnd

1D

1

CV

dd18

_10

D2

CV

dd18

_11

D3

agnd

19D

4ag

nd20

D5

agnd

21D

6

Ioutb4 D7

Iouta4D8

agnd

22D

9ag

nd23

D10

agnd

24D

11

AV

dd33

_7D

12

AV

dd33

_8D

13

nc2D14

DAC_CLKnE1

CV

dd_g

nd2

E2

CV

dd_g

nd3

E3

CV

dd_g

nd4

E4

AS

gnd1

E11

AS

gnd2

E12

IRQE13

RESETE14

DAC_CLKpF1C

Vdd

_gnd

5F2

CV

dd_g

nd6

F3

CV

dd_g

nd7

F4

AS

gnd3

F11

AS

gnd4

F12

CSB/2xF13

SDIO/FIFOF14

CV

dd_g

nd8

G1

CV

dd_g

nd9

G2

CV

dd_g

nd10

G3

CV

dd_g

nd11

G4

AS

gnd5

G11

AS

gnd6

G12

SCLK/FSC0G13

SDO/FSC1G14

DV

dd18

_1H

1

DV

dd18

_2H

2

DV

dd18

_3H

3

DV

dd18

_4H

4

DV

dd18

_5H

11

DV

dd18

_6H

12

DV

dd18

_7H

13

DV

dd18

_8H

14

DV

dd18

_9J1

DV

dd18

_10

J2

DV

dd18

_11

J3

DV

dd18

_12

J4

DV

dd18

_13

J11

DV

dd18

_14

J12

DV

dd18

_15

J13

DV

dd18

_16

J14

DV

gnd1

K1

DV

gnd2

K2

DV

gnd3

K3

DV

gnd4

K4

DV

gnd5

K11

DV

gnd6

K12

DB13nK13

DB13pK14

MODEL1

DV

gnd7

L2

DV

gnd8

L3

DV

gnd9

L4

DV

gnd1

0L5

DV

gnd1

1L6

DV

dd33

_2L7

DV

dd33

_1L8

DV

gnd1

2L9

DV

gnd1

3L1

0

DV

gnd1

4L1

1

DV

gnd1

5L1

2

DB12nL13

DB12pL14

DB00pM1 DB00nM2

DV

gnd1

6M

3

DV

gnd1

7M

4

DV

gnd1

8M

5

DV

gnd1

9M

6

DV

dd33

_3M

7

DV

dd33

_4M

8

DV

gnd2

0M

9

DV

gnd2

1M

10

DV

gnd2

2M

11

DV

gnd2

3M

12

DB11nM13

DB11pM14

DB01nN1

DB02nN2

DB03nN3

DB04nN4

DB05nN5

DCLKout_nN6

DV

dd33

_5N

7

DV

dd33

_6N

8

DCLKin_nN9

DB06nN10

DB07nN11

DB08nN12

DB09nN13

DB10nN14

DB01pP1

DB02pP2

DB03pP3

DB04pP4

DB05pP5

DCLKout_pP6

DV

dd33

_7P

7

DV

dd33

_8P

8

DCLKin_pP9

DB06pP10

DB07pP11

DB08pP12

DB09pP13

DB10pP14

L385 100uHC3001

0u1

L387 100uH

R1038

28

C3005

0u1

dac_nD0

-2V5

dac_pD0dac_nD1

dac_pD[13:0]

dac_pD1dac_nD2

dac_clk_ndac_clk_p

AV_-5V

1V8

AV_+5V

dac_pD2dac_nD3dac_pD3dac_nD4dac_pD4 pOut_DAC

dac_SDO

dac_dclkin_p

dac_nD5

dac_dgnd

dac_dclkin_n

dac_nD[13:0]

dac_pD5

Clock Distribution Schematics

30/4/2007 ATCA Workshop 21

C19

0u1

C31

0u1

C29

0u1

C3

0u1

C32

0u1

C28

0u1

C7

0u1

C27

0u1

C33

0u1

C6

0u1

L2 100uH

C21 0u1

C17

0u1R6 5k

R750

R24

25

C22

0u1

R12 200

+clk_adc4

LVPECL

LVDS

Serial Control

PLL

Clock Distribution

U7

AD9510

Ref_p1

Ref_n2

gnd1

3

Vs1

4

Vcp

5

CP6

gnd2

7

gnd3

8

Vs2

9

Clk2-p 10Clk2_n11

gnd4

12

Vs3

13

Clk1_p14

Clk1_n15

Function16

Status17

SCLK18

SDIO19

SDO20

SCSn21

gnd5

22

Vs4

23

Out7_n24Out7_p 25

Vs5

26

gnd6

27

Out3_n28Out3_p29

Vs6

30

Vs7

31

gnd7

32

Vs8

33

Out2_n34Out2_p 35

Vs9

36

Vs1

037

Out6_n 38Out6_p39

Vs1

140

Vs1

241

Out5_n42Out5_p43

Vs1

344

Vs1

445

Out4_n46Out4_p47

Vs1

548

gnd8

49

gnd9

50

Vs1

651

Vs1

752

Out1_n 53Out1_p54

gnd1

055

Vs1

856

Out0_n57Out0_p 58

Vs1

959

Vs2

060

Rset 61

gnd1

162

CPRset63

Vs2

164

C23

0u1

R20

25

R19

25

R2 50

C24

0u1

R11 200

C13

0u1 R4 100

+C1

100u0

L3 100uH C11

0u1

C30

0u1

R29

1k

C12 0u1

R27

1k

R14 200

R164k12

R28

330

R25

1k

R18

25

C5

0u1

C26

0u1

C25

0u1

C4

0u1

R8 200

L1 100uH

R1 50

R32

330

R17

25

R15 200

R13 200

R21

25

R5 50

C16

0u1

R9 200

U6Si550

Vc1

OE2

GN

D3

CLKp 4

CLKn 5

Vdd

6

R30

330

C14

0u1

R10 200

C8

0u1

R351

R23

25

C18 0u1-BaseClock

+BaseClock

3V3

Base_Function

-clk_adc1

-clk_adc4

-clk_adc3

-clk_adc2Base_SCLK

Base_Sena

Base_SDO

base_Vs_3.3V

Base_VCXOena

base_Vs_3.3V

Base_SDIO

Base_PLLstatus

-clk_dac4+clk_dac4

-clk_dac2

-clk_dac1+clk_dac2

+clk_dac1

-clk_dac3+clk_dac3

+clk_adc1

base_Vs_3.3V

+clk_adc2

C9

0u1

C15 0u1

C2

0u1

+clk_adc3

C20

0u1

R22

25R26

330

+C10

100u0

R31

1k

Dynamic Phase Alignment

30/4/2007 ATCA Workshop 22

STRATIX II Built-in Dynamic Phase Alignment (DPA) Circuitry

…Using one of eight phase-shifted clocks generated by the fast PLL, the dynamic phase aligner samples the incoming data and aligns the data by choosing the clock phase that is closest to the center of the incoming data. This alignment is continuous and can compensate for dynamic changes in the real-time timing variations between the clock and data signals….

The DPA circuitry eliminates clock-to-channel skew by aligning a sampling clock with the incoming data

Stratix II Source-Synchronous Channels Support 1 GbpsEach channel has its own DPA circuit that provides independent

data alignmentThe DPA circuitry supports multiple SERDES factors including

the 3x to 10x modes

Notes:1.PLL = phase-locked loop 2.FIFO = first in, first out 3.SERDES = serializer/deserializer