Embed Size (px)
Citation preview
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 2 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
INTENTIONALLY BLANK
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 3 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
CONTENTS
1 INTRODUCTION AND SCOPE ............................................................................................................7 1.1 Introduction ........................................................................................................................................7 1.2 EC (EarthCARE) Background ...........................................................................................................7 1.3 Scope.................................................................................................................................................8
2 DOCUMENTS .......................................................................................................................................9
3 DEFINITIONS......................................................................................................................................10 3.1 Acronyms list ...................................................................................................................................10 3.2 Specific definitions ...........................................................................................................................10 3.3 Specification format .........................................................................................................................10 3.4 DATA numbering conventions.........................................................................................................11
4 INTERFACE CIRCUIT : DESIGN RULES ..........................................................................................12
5 OVERVIEW .........................................................................................................................................13 5.1 Electrical interfaces overview ..........................................................................................................13 5.2 Cross-strapping principle .................................................................................................................14 5.3 Signals identification ........................................................................................................................15 5.4 Cabling and wiring between CAS and IDE......................................................................................16
6 CAS POWER SUPPLY .......................................................................................................................17 6.1 Power supplies characteristics ........................................................................................................17 6.2 Power supplies lines distribution .....................................................................................................22 6.3 Transient profile ...............................................................................................................................22 6.4 Wiring and grounding.......................................................................................................................23
7 CLOCKS AND SYNCHRONISATION SIGNALS ................................................................................24 7.1 High Frequency Clocks : Master clock MCLK_IDE .........................................................................24 7.2 Synchronisation signal : IDE_SYNC_REF ......................................................................................25 7.3 CAS Pixel Clock : CAS_PIXCLK .....................................................................................................26 7.4 Synchronisation signal : CAS_VALID..............................................................................................26
8 CAS VIDEO SIGNAL : CAS_VID_OUT ..............................................................................................28 8.1 CAS video signal phasing characteristics........................................................................................28 8.2 CAS video signal electrical characteristics ......................................................................................29 8.3 AnaloG link ......................................................................................................................................31 8.4 IDE-CAS video lines overshielding..................................................................................................32 8.5 CAS-MCCD format features ............................................................................................................33
9 OPERATIONAL REQUIREMENTS.....................................................................................................37 9.1 IDE nominal / redundant selection...................................................................................................37 9.2 CAS POWER-on sequence............................................................................................................37 9.3 CAS POWER-OFF sequence..........................................................................................................38 9.4 Failure cases at IDE-CAS interfaces ...............................................................................................38
9.4.1 CAS voltages supplies.........................................................................................................38
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 4 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
9.4.2 Clock signals........................................................................................................................38 9.4.3 Video signals .......................................................................................................................38
TABLES
Table 5.3-1: CAS - IDE (CVE N/R) I/F : signals identification ........................................................................16 Table 6.1-1: CAS power supplies characteristics...........................................................................................17 Table 6.1-2: DM/CM voltage ripple on VBIAS to CAS, at IDE output ( expressed in mV p-p).......................20 Table 6.1-3: DM/CM voltage ripple on VDIG to CAS, at IDE output ( expressed in mV p-p).........................20 Table 6.1-4: DM/CM voltage ripple on VANA_P to CAS, at IDE output ( expressed in mV p-p) ...................21 Table 6.1-5: DM/CM voltage ripple on VANA_M to CAS, at IDE output ( expressed in mV p-p)...................21 Table 6.1-6: Stability level on power supply lines to CAS, at IDE level..........................................................22 Table 7.1-1: “MCLK_IDE” driver and receiver implementation at IDE and CAS level ...................................25 Table 7.2-1: “IDE_SYNC_REF” driver and receiver implementation at IDE and CAS level........................25 Table 7.3-1: "CAS_PIXCLK" driver and receiver implementation at IDE and CAS level ............................26 Table 7.4-1: “CAS_VALID” driver and receiver implementation at IDE and CAS level ...............................27 Table 8.1-1: CAS video signal timing characteristics .....................................................................................28 Table 8.2-1: CAS video signal level characteristics ........................................................................................31 Table 8.2-2: Driver and receiver implementation at IDE and CAS level (Video Signals)...............................31 Table 8.3-1: Analogue link characteristics.......................................................................................................32 Table 8.5-1: CAS video Background Image 1 (CBI_1) data organization at CAS output / IDE I/F - read-out
train n° 1 ..................................................................................................................................................34 Table 8.5-2: CAS video Echo Image 1 (CEI_1) data organization at CAS output / IDE I/F - read-out train n° 235 Table 8.5-3: CAS video Background Image 2 (CBI_2) data organization at CAS output / IDE I/F - read-out
train n° 3 ..................................................................................................................................................36 Table 9.1-1: IDE Electrical interfaces characteristics in OFF state .................................................................37
FIGURES Figure 1.2-1: EarthCARE Satellite Configuration ..............................................................................................7 Figure 5.1-1: CAS/IDE Interfaces, including redundancy scheme.................................................................14 Figure 5.2-1: Cross-strapping principle between CAS and IDE (CVE N/R)...................................................15 Figure 6.1-1: CAS equivalent interface line circuits (principle schematics TBD) ...........................................19 Figure 6.3-1: Transient profile on a CAS power line ......................................................................................23 Figure 8.1-1: CAS video signal timing characteristics ....................................................................................29 Figure 8.2-1: Vm, Vp and Vref definitions .......................................................................................................30 Figure 8.2-2: maximum range and saturation case (over illumination) ...........................................................30 Figure 8.3-1: Video link interface (schematic) .................................................................................................32 Figure 8.4-1: IDE-CAS video lines overshielding principle..............................................................................32 Figure 8.5-1: CAS acquisition sequence principle...........................................................................................33
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 5 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
INTENTIONALLY BLANK
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 6 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
SUMMARY
In the frame of ATLID FM Instrument, this specification defines the Electrical Interface requirements between IDE and CAS.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 7 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
1 INTRODUCTION AND SCOPE
1.1 Introduction
This document establishes the electrical interfaces, the performances and the management requirements between IDE (Instrument Detection Electronics) and CAS (Co-Alignment Sensor) units, whose Flight Models will be embarked for the ATLID Instrument on-board the EarthCARE Satellite.
Unless otherwise specified, each requirement applies to both IDE and CAS contractors, for both the unit itself (IDE, CAS) and for its Unit tester.
1.2 EC (EarthCARE) Background
Earth Explorer Core Missions are an element of the Earth Observation Envelope Programme. They are defined as major missions led by ESA to cover primary research objectives set out in the Living Planet Program (ESA, 1998). The Earth Clouds, Aerosols and Radiation Explorer Mission (EarthCARE) has been approved for implementation as the third Earth Explorer Core Mission.
EarthCARE is a cooperative mission between ESA and JAXA, where JAXA will provide a Cloud Profiling Radar. ESA is responsible for the entire system including the Spacecraft, three instruments, the Launcher and the Ground Segment.
The EarthCARE Mission will help in determining the Earth radiation budget by providing global observations of vertical cloud and aerosol profiles. The mission is centred on the synergetic use of the data provided by an instrument suite consisting of an ATmospheric LIDar (ATLID), a Cloud Profiling Radar (CPR), a Multi-Spectral Imager (MSI) and a Broad Band Radiometer (BBR).
Figure 1.2-1: EarthCARE Satellite Configuration
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 8 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
1.3 Scope
The document in hand comprises the contractually relevant requirements and constraints for the ATLID IDE-CAS Electrical Interfaces. This includes :
•the performance as well as design and interface requirements of the ATLID IDE-CAS hardware,
•the product assurance requirements,
•the testing and verification requirements.
IF-IDE-CAS-13 / R / / /
In all cases, excepted when a restriction is clearly mentioned, the requirements shall be considered as "End Of Life and In-Orbit" requirements. As a consequence, both IDE and CAS supplier shall define "On-Ground Beginning Of Life" success criteria compatible with the as mentioned EOL requirements.
IF-IDE-CAS-14 / A / / /
If any TBCs (To Be Confirmed) remain in the present document for some requirements and if considered as critical wrt equipments development, either IDE or CAS sub-contractor shall identify the latest date, the confirmation has to take place.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 9 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
2 DOCUMENTS
Refer to Documents listed in dedicated paragraph of units requirements specifications.
Note : The applicable General Design and Interface Requirements (GDIR) are located inside the units requirements specifications documents (chapter 9 for IDE requirement specification and chapter 14 for CAS requirement specification).
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 10 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
3 DEFINITIONS
3.1 Acronyms list
In addition to acronyms defined in reference documents [RD-201] and [RD-203], in both IDE and CAS requirement specifications, the following list of acronyms is used in the current specification :
ACDM : ATLID Control and Data Management Unit
BRC : Basic Repetitive Cycle
CAS : Co-Alignment Sensor
CCD : Charge Coupled Device
CDS : Correlated Double Sampling
CVE : Control and Video Electronics (redundant part of IDE)
EICD : Electrical Interface Control Document
EOL : End Of Life
GDIR : General Design and Interface Requirements
HF : High Frequency
IDE : Instrument Detection Electronics
LCLK : Low (rate) CLocK
LF : Low Frequency
LVDS : Low Voltage Data Signal
MCCD : Memory CCD (CAS-MCCD within CAS)
MCLK : Master CLocK
PRF : Pulse Repetition Frequency
p-t-p : peak to peak
ST : Short Term
TBC : To Be Confirmed
3.2 Specific definitions
Refer to IDE and CAS units specifications. In addition :
1. Tmc_IDE : It represents the Clock Period of the Master Clock dedicated to ATLID detection units (MCLK_IDE), which is at a frequency of 32 MHz.
2. LCLK or PRF : It represents the Frequency of the Low clock (LCLK) which is between 50 and 100 Hz. (Also called Pulse Repetition Frequency - PRF). Baseline frequency is 51 Hz (+ 10 %; - 0 %).
3. LCLK_P : It represents the Clock Period of the Low clock (LCLK).
3.3 Specification format
Requirements within this document are shown in an italic font. Each requirement is preceded by a summary line that contains the following fields, delimited by "/".
• Doors Requirement Number
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 11 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
• Intended Verification Method
• Created From
as shown here after :
IF-IDE-CAS-28 / T,A,I,R,S / / /
Requirement text
The Doors Requirement Number has the form IF-IDE-CAS-xxx, where xxx is a unique number assigned consecutively.
The Intended Verification Method codes are as follows :
• R - Review
• A - Analysis
• I - Inspection
• T - Test
The Created from information is used for upper link information (identify which customer requirements are derived from).
When a requirement has no straight upper link, Created from is filled with “created”.
The requirement text follows the summary line. If tables are considered as part of requirement they are referenced clearly in the text and inserted after and separated from the requirement and are managed as free text attached to the identifier requirement.
All document elements not presented in the format explained above are not requirements and shall not be verified or tracked.
3.4 DATA numbering conventions
Refer to GDIR in both IDE and CAS requirement specifications.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 12 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
4 INTERFACE CIRCUIT : DESIGN RULES
IF-IDE-CAS-36 / R / / /
The design of any signal interface shall ensure that the interface is not susceptible to noise specified and that the noise it generates is compatible with the emission requirements.
IF-IDE-CAS-37 / R / / /
Two wires interface shall be used : all electrical links between the instrument units shall be performed by either differential, or galvanic insulation ( relay, optocoupler,...) interfaces.
Use of a common return for several links is not allowed.
The reference point(s) for these lines will be defined in such a way to avoid interference loops. Moreover, a return line will not be connected to the mechanical ground at both ends but will be referenced to one point, generally at transmitter level.
IF-IDE-CAS-38 / R / / /
Signals outputs shall be referenced to box structure or ground plane :
- for single ended output, referencing to structure is via the secondary power / signal ground,
- for differential output, referencing to structure is via the driver output impedance.
IF-IDE-CAS-39 / R / / /
Analogue and digital circuits shall be designed to respond only to working frequency bandwidths. Filtering shall be used at the receiver inputs to reject both differential and common mode unwanted signals.
IF-IDE-CAS-40 / R / / /
Transmission bandwidths shall be limited to the minimum necessary bandwidth.
IF-IDE-CAS-41 / R / / /
Interface circuit not powered :
When not powered, the receiver shall withstand any transmitter characteristics without damages and stress.
When not powered, the transmitter shall withstand any receiver characteristics without damages and stress.
IF-IDE-CAS-42 / T,A / / /
The CAS shall withstand without damages and stress the following conditions :
• 1 or several interface signals from IDE are absent.
IF-IDE-CAS-43 / T,A / / /
The IDE shall withstand without damages and stress the following conditions :
1 or several interface signals from CAS are absent.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 13 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
5 OVERVIEW
5.1 Electrical interfaces overview
The electrical interfaces between IDE and CAS consist of :
From IDE to CAS :
•CAS power supply lines : the IDE provides the CAS with four voltage supply lines
•CAS Clock & synchros signals :
The IDE provides the CAS with :
MCLK_IDE :
This master clock acts as a unique high frequency source for both ATLID detection units electronics and synchronous link clock.
The period of this master clock is defined as Tmc_IDE.
It corresponds to the image of the Master Clock, generated initially by ACDM, received by IDE from ACDM (for IDE internal use), and routed directly to IDE/CAS interface.
IDE_Sync_Ref :
This synchronisation signal is used for detection accurate acquisitions for both ATLID detection units electronics.
It corresponds to the image of the synchronisation signal, generated initially by ACDM, received by IDE from ACDM (for IDE internal use), and routed directly to IDE/CAS interface.
Note:
Both above clock signals are transmitted with equivalent design (from ACDM output to IDE input and IDE/CAS I/F), in order to keep always the same synchronisation.
From CAS to IDE :
•CAS video interface signals :
The CAS provides the IDE with an analogue video interface (corresponding to CAS-MCCD) defined by three signals :
CAS Video out "CAS_VID_OUT" :
Video signal from the output (read-out register) of the CAS-MCCD. AC coupled, source terminated, known impedance shielded twisted pair cabling.
Signal level of 2 V (TBC) between the reset level and the video level being the full scale.
4.5 MHz bandwidth with 100 Hz low-frequency cut-off (TBC).
CAS Pixel Clock "CAS_PIXCLK" :
Clock synchronised to the video.
The rising edge of "CAS_PIXCLK" will indicate the start of the reference level of the video signal while the falling edge of "CAS_PIXCLK" indicated the start of the video level of the CAS-MCCD video signal.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 14 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
CAS Pixel Valid signal "CAS_VALID" :
When at a high level, it indicates that the analogue pixel signal has a video signal from the acquired pixel part of the sequence. These pixels are to be stored for further processing. All pixels are to be checked for over-range.
An overview of the CAS-IDE electrical interfaces is given in Figure 5.1-1.
CAS Video out / (x 1)
Master clock (MClk_IDE) / (x 1)
Synchro signal (IDE_Sync_Ref) / 1
Voltage supplies / (x 4)
CAS Video out / (x 1)
Master Clock (MClk_IDE) / (x 1)
Synchro signal (IDE_Sync_Ref) / 1
Voltage supplies / (x 4)
CAS I/F
Nominal
CAS I/F
Redundant
IDE
CVE Nominal
CVE Redundant
CAS Pixel Valid Signal / (x 1)
CAS Pixel Clock / (x 1)
CAS Pixel Valid Signal / (x 1)
CAS Pixel Clock / (x 1)
CAS Video out / (x 1)
Master clock (MClk_IDE) / (x 1)
Synchro signal (IDE_Sync_Ref) / 1
Voltage supplies / (x 4)
CAS Video out / (x 1)
Master Clock (MClk_IDE) / (x 1)
Synchro signal (IDE_Sync_Ref) / 1
Voltage supplies / (x 4)
CAS I/F
Nominal
CAS I/F
Redundant
IDE
CVE Nominal
CVE Redundant
CAS Pixel Valid Signal / (x 1)
CAS Pixel Clock / (x 1)
CAS Pixel Valid Signal / (x 1)
CAS Pixel Clock / (x 1)
Figure 5.1-1: CAS/IDE Interfaces, including redundancy scheme
5.2 Cross-strapping principle
The cross-strapping principle is defined such that CAS faces the two redunded part Control and Video Electronics (CVE) of the IDE. The CAS encompasses a full redundancy at interface level.
The architecture of the electrical interface and the partial cross-strapping principle are depicted in Figure 5.2-1.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 15 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
IDE CVE Redundant
CAS I/F N
CAS I/F R
IDE CVE Nominal
CAS interfaces are in redundancy CVE is fully redunded within IDE
To CAS
internal functions
IDE CVE Redundant
CAS I/F N
CAS I/F R
IDE CVE Nominal
CAS interfaces are in redundancy CVE is fully redunded within IDE
To CAS
internal functions
Figure 5.2-1: Cross-strapping principle between CAS and IDE (CVE N/R)
5.3 Signals identification
Table 5.3-1 depicts the signal identification as input for units EICD.
IF-IDE-CAS-61 / R / / /
CAS and IDE contractor shall apply the signal identifications as specified in Table 5.3-1.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 16 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Signal name Description From To
CAS_N_VANA_P IDE/CVE N CAS_IF_N CAS_R_VANA_P IDE/CVE R CAS_IF_R CAS_N_VANA_N IDE/CVE N CAS_IF_N CAS_R_VANA_N
Pre amplifier voltage supplies
IDE/CVE R CAS_IF_R CAS_N_VDIG IDE/CVE N CAS_IF_N CAS_R_VDIG
Digital voltage supplies IDE/CVE R CAS_IF_R
CAS_N_VBIAS IDE/CVE N CAS_IF_N CAS_R_VBIAS
CAS-MCCD bias supplies IDE/CVE R CAS_IF_R
MCLK_IDE_N IDE/CVE N CAS_IF_N MCLK_IDE_R
Master clock
IDE/CVE R CAS_IF_R IDE_SYNC_REF_N IDE/CVE N CAS_IF_N IDE_SYNC_REF_R
IDE Sync Ref signal
IDE/CVE R CAS_IF_R CAS_VID_OUT_N CAS_IF_N IDE/CVE N CAS_VID_OUT_R
CAS Video Signal
CAS_IF_R IDE/CVE R CAS_PIXCLK_N CAS_IF_N IDE/CVE N CAS_PIXCLK_R
CAS Pixel Clock
CAS_IF_R IDE/CVE R CAS_VALID_N CAS_IF_N IDE/CVE N CAS_VALID_R
CAS Pixel Valid Signal
CAS_IF_R IDE/CVE R
Table 5.3-1: CAS - IDE (CVE N/R) I/F : signals identification
5.4 Cabling and wiring between CAS and IDE
IF-IDE-CAS-65 / T,A,R / / /
The cabling between CAS and IDE is included in the CAS equipment perimeter.
It shall be defined, manufactured, tested and provided by CAS sub-contractor with each CAS model.
IF-IDE-CAS-66 / A,R / / /
The CAS/IDE harness organisation, cabling/wiring type and electrical characteristics, shall be proposed by CAS sub-contractor, approved by ATLID prime, then incorporated in the present specification when needed.
IF-IDE-CAS-67 / A,R / / /
All the requirements of the present specifcation shall therefore applied at IDE/CAS interface, this interface being considered at IDE output and CAS/IDE cabling being considered on CAS side.
IF-IDE-CAS-68 / A,R / / /
All the cabling/wiring requirements defined in GDIR chapter within both IDE/CAS equipment specifications shall apply without any restrictions to CAS/IDE harness.
IF-IDE-CAS-69 / T,A,R / / /
The overall length of the harness between CAS and IDE shall be specified without contingency through CAS/IDE harness IRD.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 17 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
6 CAS POWER SUPPLY
6.1 Power supplies characteristics
IF-IDE-CAS-72 / T,R / / /
The IDE shall provide the CAS with four voltage supplies as specified in Table 6.1-1.
Note :
All values are provided as first indicative. They shall be defined by CAS subcontractors with ATLID prime, and confirmed by IDE sub-contractor.
IF-IDE-CAS-73 / A,R / / /
The requirements as specified in Section 6 shall apply to both nominal and redundant power supply functions.
IF-IDE-CAS-74 / A,R / / /
In any case (in particular in case of failure within IDE), the IDE shall not create any overvoltage at CAS input, higher than the maximum absolute ratings, as specified in Table 6.1-1 (those values shall be considered as applicable in a permanent state).
IF-IDE-CAS-75 / T,R / / /
These absolute maximum ratings, applied at CAS input, shall not induce any loss of functional and/or performance characteristics of CAS functions.
IF-IDE-CAS-76 / T,A,R / / /
The CAS (except in failure) shall not create any maximum current at IDE output, higher than the maximum absolute values, as specified in Table 6.1-1 (those values shall be considered as applicable in a permanent state).
IF-IDE-CAS-77 / T,A,R / / /
Any permanent short-circuit configuration for any line (between lives and/or return) shall not affect functional and performances characteristics of the electronics supplied by all the other non-affected lines.
Mini voltage
(V)
Nom voltage
(V)
Maxi voltage
(V)
Mini current(mA)
Typ. current(mA)
Maxi current(mA)
Over current (CAS failure case
(mA)
CAS equivalentI/F circuit
Absolutemax. rating (failure case)(V)
VANA_P 16,2 17,05 17,9 33 42,5 70 87,5 Note 1 19
VANA_N - 16,2 - 17,05 - 17,9 2.5 8 15 18,75 Note 1 - 19
VBIAS 36.1 38,0 39.9 7 9 20 25 Note 1 46
VDIG 4,9 5,14 5,4 26 86 160 200 Note 1 6
Table 6.1-1: CAS power supplies characteristics
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 18 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Note 1 : The CAS equivalent interface power line circuits (to be demonstrated by CAS equipment and to be considered by IDE at interface) shall be equivalent to the circuits TBC (principle schematics in Figure 6.1-1).
They shall be provided by CAS subcontractor from CAS design definition.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 19 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Figure 6.1-1: CAS equivalent interface line circuits (principle schematics TBD)
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 20 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
IF-IDE-CAS-83 / T,A / / /
Noise performance :
Noise on power supply, measured at IDE output, shall not exceed frequency templates in Differential Mode (dm) and Common Mode (cm), given in :
•Table 6.1-2 for VBIAS,
•Table 6.1-3 for VDIG,
•Table 6.1-4 for VANA_P,
•Table 6.1-5 for VANA_M.
F (kHz) Vdm (mV p-p) Vcm (mV p-p)
0.01 50 50
10 50 50
90 50 50
90 15 15
500 15 15
3000 8 8
8000 8 8
50000 50 50
Table 6.1-2: DM/CM voltage ripple on VBIAS to CAS, at IDE output ( expressed in mV p-p)
F (kHz) Vdm (mV p-p) Vcm (mV p-p)
0.01 50 50
10 50 50
90 50 50
90 10 10
3000 10 10
7000 50 50
50000 50 50
Table 6.1-3: DM/CM voltage ripple on VDIG to CAS, at IDE output ( expressed in mV p-p)
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 21 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
F (kHz) Vdm (mV p-p) Vcm (mV p-p)
0.01 50 50
10 50 50
90 50 50
90 15 15
500 15 15
1000 10 10
20000 10 10
50000 50 50
Table 6.1-4: DM/CM voltage ripple on VANA_P to CAS, at IDE output ( expressed in mV p-p)
F (kHz) Vdm (mV p-p) Vcm (mV p-p)
0.01 50 50
10 50 50
90 50 50
90 15 15
500 15 15
1000 10 10
20000 10 10
50000 50 50
Table 6.1-5: DM/CM voltage ripple on VANA_M to CAS, at IDE output ( expressed in mV p-p)
IF-IDE-CAS-86 / T,A / / /
Stability performances :
The stability performances on each secondary voltage are specified in Table 6.1-6. The stability power supply, measured at IDE output, shall not overcome these values.
Values are given for Short Term (ST) stability, as defined in GDIR in both IDE and CAS requirement specifications.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 22 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Name Stability over ST (mV)
VANA_N ± 50
VANA_P ± 50
VBIAS ± 50
VDIG ± 50
Table 6.1-6: Stability level on power supply lines to CAS, at IDE level
6.2 Power supplies lines distribution
IF-IDE-CAS-90 / R / / /
Each CAS voltage supplies shall be generated from specific secondary windings at IDE level.
The CAS is fed by a dedicated converter set inside the IDE.
IF-IDE-CAS-91 / R / / /
All the lines shall be transmitted from IDE to CAS via twisted shielded pairs leads.
IF-IDE-CAS-92 / R / / /
All the line returns shall be galvanically isolated each other and from unit chassis, at IDE level.
IF-IDE-CAS-93 / R / / /
The CAS secondary voltages returns delivered by IDE shall be connected at a unique point within CAS.
This point corresponds to electrical “0 V” of the CAS.
Note on requirements IF-IDE-CAS-92 and IF-IDE-CAS-93 :
The baseline configuration of 0 V between the two units consists of the following : a unique connection to ground (e.g. connection to instrument mechanical ground point ) is made at CAS level.
The CAS voltages supplies return are isolated from IDE chassis.
Flexibility allowing evolution of this definition is specified at unit level, in each unit specification.
6.3 Transient profile
IF-IDE-CAS-96 / T,R / / /
Requirement for IDE :
When submitted to perturbation on the primary power bus as defined in GDIR in both IDE and CAS requirement specifications, the IDE shall not generate in differential and common mode, on each power line towards CAS a transient deeper than those specified in Figure 6.3-1.
Transients are defined for a voltage V which value is taken from the range Vmin to Vmax defined in Table 6.1-1.
IF-IDE-CAS-97 / T,R / / /
Requirement for CAS :
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 23 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
When CAS is submitted to transient of Figure 6.3-1 (with a ratio of 2 deeper than the lowest voltage with the same falling slope - 6 dB margin) on each power line independently or simultaneously, the CAS is required to fulfil all its functional and performance requirements, during and after such transients occurrence.
level (mV)
Time
Power line value( Vmin < V < V max )
V - 100 mV(TBC)
V - 400 mV(TBC)
2.5 mV/ 0.8 mV/
t0 T0 + 500 μs
(μs)
μsμs
level (mV)
Time
Power line value( Vmin < V < V max )
V - 100 mV(TBC)
V - 400 mV(TBC)
2.5 mV/ 0.8 mV/
t0 T0 + 500 μs
(μs)
μsμs
Figure 6.3-1: Transient profile on a CAS power line
6.4 Wiring and grounding
Wiring and grounding aspects of the CAS power supply lines shall comply to requirements of Section 5.4, and shall be reported in the present specifcation when defined and agreed.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 24 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
7 CLOCKS AND SYNCHRONISATION SIGNALS
IF-IDE-CAS-299 / T,R / / /
For all signals defined in this section, IDE and CAS shall fulfil the cross-strapping principle defined in Section 5.2.
Protection and Immunity shall comply with GDIR.
7.1 High Frequency Clocks : Master clock MCLK_IDE
IF-IDE-CAS-104 / T,R / / /
The IDE shall provide the CAS with one high frequency clock, considered as the master clock and called “MCLK_IDE”,
This unique master clock shall garantee that both units are running with a fully synchronized timing sequence based on a unique high frequency source, when the IDE is operated in detection sub-modes.
IF-IDE-CAS-105 / A,R / / /
Master clock features :
The “MCLK_IDE” signal characteristics shall be compliant with the following requirements :
The signal specific characteristics are the following :
Frequency : Nominal : 32 MHz
Range : 31 MHz - 33 MHz
Jitter : < 10 nsec
Duty Cycle : ratio 33 : 66 (see note)
Note :
The master clock duty cycle is defined as the ratio Thigh/Tlow, at half maximum (50 %) of the measured differential amplitude of the complementary LVDS signals.
IF-IDE-CAS-106 / T,R / / /
The functional requirements of the CAS shall be verified considering the hereabove specified Clock (with tolerances indicated on frequency value).
IF-IDE-CAS-107 / T,R / / /
The performance requirements of CAS shall be verified considering a Nominal Master Clock at the indicated frequency (without considering any tolerance).
IF-IDE-CAS-108 / T,R / / /
Synchronisation & timing requirements :
The jitter shall be less than 1 Tmc_IDE.
Jitter is defined by the absolute uncertainty (peak-to-peak error) of edges temporal position.
Note :
This requirement shall be met, taking into account all the environmental conditions as specified in both IDE and CAS equipment requirement specifications.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 25 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
IF-IDE-CAS-109 / T,R / / /
Electrical Requirements :
"MCLK_IDE” signal drivers and receivers implementation within IDE and CAS shall be as specified in Table 7.1-1.
INTERFACE Type
SIGNAL at IDE level at CAS level
MCLK_IDE DRIVER - IDE ( see unit spec & GDIR “LVDS”)
RECEIVER - CAS ( see unit spec & GDIR “LVDS”)
Table 7.1-1: “MCLK_IDE” driver and receiver implementation at IDE and CAS level
7.2 Synchronisation signal : IDE_SYNC_REF
IF-IDE-CAS-114 / R / / /
The IDE shall generate 1 synchronisation signal towards CAS called “IDE_SYNC_REF”, for detection accurate acquisition during atmospheric return signal .
IF-IDE-CAS-269 / T,R / / /
The sending of the IDE_SYNC_REF signal by IDE to CAS shall initialize the CAS data production.
IF-IDE-CAS-115 / T,R / / /
The circuit implemented in the IDE and in the CAS shall be compliant to electrical characteristics of Table 7.2-1.
IF-IDE-CAS-116 / T,R / / /
The inactive level of this signal shall be Logical 0.
IF-IDE-CAS-117 / T,R / / /
The active level of all these signals shall be :
T(active) duration (Ta) : 12 µsec < Ta < 18 µsec
IF-IDE-CAS-118 / T,R / / /
“IDE_SYNC_REF” shall be compliant with the following requirements :
Frequency : Nominal : 51 Hz
Range : (+ 10 %; - 0 %)
Jitter : < 10 ns
INTERFACE Type
SIGNAL at IDE level at CAS level
IDE_SYNC_REF DRIVER - IDE ( see unit spec & GDIR “LVDS”)
RECEIVER - CAS ( see unit spec & GDIR “LVDS”)
Table 7.2-1: “IDE_SYNC_REF” driver and receiver implementation at IDE and CAS level
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 26 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
7.3 CAS Pixel Clock : CAS_PIXCLK
IF-IDE-CAS-290 / R / / /
The CAS shall generate 1 clock signal towards IDE called “CAS_PIXCLK”, for IDE synchronisation purpose.
This Clock shall be synchronised to the video.
IF-IDE-CAS-291 / T,R / / /
The rising edge of "CAS_PIXCLK" will indicate the start of the reference level of the video signal while the falling edge of "CAS_PIXCLK" indicated the start of the video level of the CAS-MCCD video signal.
IF-IDE-CAS-292 / T,R / / /
The circuit implemented in the IDE and in the CAS shall be compliant to electrical characteristics of Table 7.3-1.
IF-IDE-CAS-295 / T,R / / /
The “CAS_PIXCLK” signal characteristics shall be compliant with the following requirements (TBC) :
The signal specific characteristics are the following :
Frequency : Nominal : 888.888 kHz
Range : TBC
Jitter : < TBC nsec
Duty Cycle : TBC
IF-IDE-CAS-296 / T,R / / /
Electrical Requirements :
"CAS_PIXCLK" signal drivers and receivers implementation within IDE and CAS shall be as specified in Table 7.3-1.
INTERFACE Type
SIGNAL at IDE level at CAS level
CAS_PIXCLK DRIVER - IDE ( see unit spec & GDIR “LVDS”)
RECEIVER - CAS ( see unit spec & GDIR “LVDS”)
Table 7.3-1: "CAS_PIXCLK" driver and receiver implementation at IDE and CAS level
7.4 Synchronisation signal : CAS_VALID
IF-IDE-CAS-303 / R / / /
The CAS shall generate 1 synchronisation signal towards IDE called “CAS_VALID”, for .
validation purpose.
When at a high level, it indicates that the analogue pixel signal has a video signal from the acquired pixel part of the sequence. These pixels are to be stored for further processing. All pixels are to be checked for over-range.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 27 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
IF-IDE-CAS-305 / T,R / / /
The circuit implemented in the IDE and in the CAS shall be compliant to electrical characteristics of Table 7.4-1.
IF-IDE-CAS-306 / T,R / / /
The inactive level of this signal shall be Logical 0.
IF-IDE-CAS-307 / T,R / / /
The active level of all these signals shall be :
T(active) duration (Ta) : TBD µsec < Ta < TBD µsec
IF-IDE-CAS-308 / T,R / / /
“CAS_VALID” shall be compliant with the following requirements :
Frequency : Nominal : TBD Hz
Range : TBD
Jitter : < TBD ns
INTERFACE Type
SIGNAL at IDE level at CAS level
CAS_VALID DRIVER - IDE ( see unit spec & GDIR “LVDS”)
RECEIVER - CAS ( see unit spec & GDIR “LVDS”)
Table 7.4-1: “CAS_VALID” driver and receiver implementation at IDE and CAS level
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 28 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
8 CAS VIDEO SIGNAL : CAS_VID_OUT
8.1 CAS video signal phasing characteristics
IF-IDE-CAS-124 / T,R / / /
The CAS video signal shall feature the phasing characteristics as specified in Table 8.1-1 and Figure 8.1-1.
Parameter Symbol Unit Value
Pixel Clock Period Tpixel Tmc 36
Reset pulse duration Treset Tmc =< 6
Useful reference level duration Zr Tmc 10
Useful video level duration Zu Tmc 10
Position of reference level Tzr Tmc Pixel Clock rising edge
Position of video level Tzu Tmc Pixel Clock falling edge
Table 8.1-1: CAS video signal timing characteristics
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 29 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
MCLK_IDE
Tpixel
t1 t1 +Tpixel
CAS Video out signal
CAS Pixel Clock
Available zone forreference level sampling
Available zone forvideo level sampling
Tzr
Tzu
Zr
Zu
Treset
(1 Tpixel = 36 Tmc_IDE)
CAS Pixel Valid signal
(high level = valid pixel)
MCLK_IDE
Tpixel
t1 t1 +Tpixel
CAS Video out signal
CAS Pixel Clock
Available zone forreference level sampling
Available zone forvideo level sampling
Tzr
Tzu
Zr
Zu
Treset
(1 Tpixel = 36 Tmc_IDE)
CAS Pixel Valid signal
(high level = valid pixel)
Figure 8.1-1: CAS video signal timing characteristics
8.2 CAS video signal electrical characteristics
IF-IDE-CAS-130 / T,R / / /
The CAS video signal shall feature the level characteristics as specified in Table 8.2-1 and defined in Figure 8.2-1 and in in Figure 8.2-2.
Notes :
• Radiometric performances are specified within video signal range as defined in units specification requirements.
IF-IDE-CAS-131 / T,R / / /
High corner frequency :
On CAS output, the video signal high corner frequency shall be at least 4.5 MHz.
IF-IDE-CAS-132 / T,R / / /
Low corner frequency :
On CAS output, the video signal low corner frequency shall be at most 3 Hz TBC.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 30 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
IF-IDE-CAS-133 / T,R / / /
Immunity to Common Mode perturbation :
IDE shall fulfil its performances when video I/F is submitted to a 2.5 V Common Mode voltage up to 4.5 MHz.
pixel period
Video signal
Vp
Vm
VrefOV (Video return line)
pixel period
Video signal
Vp
Vm
VrefOV (Video return line)
Figure 8.2-1: Vm, Vp and Vref definitions
OV
Vp sat
Vp max
Vref max
Vm min
Vm sat
Figure 8.2-2: maximum range and saturation case (over illumination)
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 31 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Value ( V ) Parameter Symbol Unit
min sat
Comments
Reset level Vref V 0 + 1
Video signal negative excursion Vm V - 1 0
Video signal positive excursion Vp V 0 + 1
RESET amplitude overshoot Vp - Vref V 0 + 1
Maximum values, specified through
video level ranges, to be considered for
performance requirement are specified in units specifications.
Table 8.2-1: CAS video signal level characteristics
IF-IDE-CAS-270 / T,R / / /
CAS Video Signal Electrical Requirements :
CAS video signal drivers and receivers implementation within IDE and CAS shall be as specified in Table 8.2-2.
INTERFACE Type
SIGNAL at IDE level at CAS level
Video
Signals
DRIVER - IDE ( see unit spec & GDIR “LVDS”)
RECEIVER - CAS ( see unit spec & GDIR “LVDS”)
Table 8.2-2: Driver and receiver implementation at IDE and CAS level (Video Signals)
8.3 AnaloG link
IF-IDE-CAS-141 / T,R / / /
Each video signal shall be transmitted through a Twisted shielded pair line 120 Ohms adapted at the source, as represented on Figure 8.3-1 ,and as specified in Table 8.3-1.
IF-IDE-CAS-142 / R / / /
The emitter shall be unipolar.
IF-IDE-CAS-143 / R / / /
The receiver shall be of differential type.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 32 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
R = 60 Ohms
R = 50 kOhms
CAS IDEShield
Twisted shielded pair
R = 60 Ohms
R = 60 Ohms
R = 50 kOhms
CAS IDEShield
Twisted shielded pair
R = 60 Ohms
Figure 8.3-1: Video link interface (schematic)
Value Parameter Symbol Unit
min typ max
Comments
Source impedance (on CAS side) Zs Ω 110 120 130
Input impedance load (on IDE side) Ze kΩ 40 50 60
Length L video link m 2 2.5 3
Table 8.3-1: Analogue link characteristics
8.4 IDE-CAS video lines overshielding
IF-IDE-CAS-279 / A,R / / /
An overshielding of the video lines between IDE and CAS shall be implemented.
This overshielding shall be based on a braided mesh solution, as presented in Figure 8.4-1, with components described in the following.
Figure 8.4-1: IDE-CAS video lines overshielding principle
Mesh curtain :
Reference: C.G.P : BLJ-R- X; Electrolytic copper; Silver plated 1,5 μm
This over shield is a single curtain made of silver plated copper braids meshing.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 33 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
The cables bundle is inserted into the mesh sleeve (no helix wrap around the bundle).
The optical coverage of this over shield is 96%. The mesh curtain diameter fits closely with the bundle diameter.
The mass of this braided over shield is 73 kg/km
EMC back shell :
Reference: POLAMCO : 100P 2315-15S-15-07 L50- CHP (P148663) (other supplier can be selected)
Machined aluminium alloy 6082-T6, electroless Nickel-plated to MIL-C-26074, class 4, grade B, 13μm thick.
Band it clamps :
Reference : 600-052, stainless steel 300 SST
The mesh curtain overlaps the back shell chimney. At both ends of the bundle, a Band It clamp squeezes and bonds the mesh on the back shell chimney over 360°.
8.5 CAS-MCCD format features
Refer to CAS-MCCD documentation identified in each equipment specification (IDE and CAS) for details on CAS-MCCD format features and topology.
The CAS acquisition sequence principle is provided in both equipments specifications, and recalled here-below in Figure 8.5-1.
28281 Tmc
Read-out
Steps 1 2 34 567 8 910 110
IDE
_syn
c_R
ef
B = background Integ. 18.5 km A = atm. Integ. 18.5 km
18 km -500 m
B MT
MT = Image Transfer to MT area
9648 Tmc
MT A MTF F BFRead-out
Read-out
1213 14 1516171819 20
F = Flushing period, to clean-up CCD
CAS Sequence
28281 Tmc
Read-out
Steps 1 2 34 567 8 910 110
IDE
_syn
c_R
ef
B = background Integ. 18.5 km A = atm. Integ. 18.5 km
18 km -500 m
B MT
MT = Image Transfer to MT area
9648 Tmc
MT A MTF F BFRead-out
Read-out
1213 14 1516171819 20
F = Flushing period, to clean-up CCD
CAS Sequence
Figure 8.5-1: CAS acquisition sequence principle
IF-IDE-CAS-153 / T,R / / /
From the CAS acquisition sequence identified above in Figure 8.5-1, the video data that are exchanged between the CAS and the IDE is described in the following Table 8.5-1, Table 8.5-2 and Table 8.5-3.
These 3 Tables identify for each three successive acquisition (CAS background image 1 and 2 and CAS echo image within), the video data organization, at CAS output level (IDE I/F), in their order of read-out, the first useful pixels corresponding to echo/background image signal, followed at last by the chain offset pixels, the CAS Pixel Valid signal status being added in regard of each pixel value.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 34 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Pixel number at CAS output Signification CAS Pixel
Valid signal Read-out train n°1
1 Not Used 0 2 Not Used 0 3 Not Used 0 4 Not Used 0 5 Not Used 0
… … … … … … … … … 209 Not Used 0 210 Not Used 0 211 Pixel n°1 CBI_1 1 212 Pixel n°2 CBI_1 1 … … … … … … … … … … … … 257 Pixel n°47 CBI_1 1 258 Pixel n°48 CBI_1 1 259 Not Used 0 260 Not Used 0 … … … … … … … … … 263 Not Used 0 264 Not Used 0 265 Offset CBI_1 n° 1 1 266 Offset CBI_1 n° 2 1 267 Offset CBI_1 n° 3 1 268 Offset CBI_1 n° 4 1
Table 8.5-1: CAS video Background Image 1 (CBI_1) data organization at CAS output / IDE I/F - read-out train n° 1
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 35 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Pixel number at CAS output Signification CAS Pixel
Valid signal Read-out train n° 2
1 Not Used 0 2 Not Used 0 3 Not Used 0 4 Not Used 0 5 Not Used 0
… … … … … … … … … 209 Not Used 0 210 Not Used 0 211 Pixel n°1 CEI_1 1 212 Pixel n°2 CEI_1 1 … … … … … … … … … … … … 257 Pixel n°47 CEI_1 1 258 Pixel n°48 CEI_1 1 259 Not Used 0 260 Not Used 0 … … … … … … … … … 263 Not Used 0 264 Not Used 0 265 Offset CEI_1 n° 1 1 266 Offset CEI_1 n° 2 1 267 Offset CEI_1 n° 3 1 268 Offset CEI_1 n° 4 1
Table 8.5-2: CAS video Echo Image 1 (CEI_1) data organization at CAS output / IDE I/F - read-out train n° 2
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 36 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Pixel number at CAS output Signification CAS Pixel
Valid signal Read-out train n° 3
1 Not Used 0 2 Not Used 0 3 Not Used 0 4 Not Used 0 5 Not Used 0
… … … … … … … … … 209 Not Used 0 210 Not Used 0 211 Pixel n°1 CBI_2 1 212 Pixel n°2 CBI_2 1 … … … … … … … … … … … … 257 Pixel n°47 CBI_2 1 258 Pixel n°48 CBI_2 1 259 Not Used 0 260 Not Used 0 … … … … … … … … … 263 Not Used 0 264 Not Used 0 265 Offset CBI_2 n° 1 1 266 Offset CBI_2 n° 2 1 267 Offset CBI_2 n° 3 1 268 Offset CBI_2 n° 4 1
Table 8.5-3: CAS video Background Image 2 (CBI_2) data organization at CAS output / IDE I/F - read-out train n° 3
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 37 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
9 OPERATIONAL REQUIREMENTS
9.1 IDE nominal / redundant selection
IF-IDE-CAS-162 / T,R / / /
The CAS shall automatically detect the selected IDE-CVE (N or R) through the presence of its voltage supplies and by active I/F for the clock/synchro signals.
No specific command at CAS level shall be necessary.
IF-IDE-CAS-163 / T,R / / /
The non active IDE (redundant unit in nominal case) shall present isolated interface between wires and w.r.t. both its internal electronics and unit ground connection point, in accordance with the specification of Table 9.1-1.
IF-IDE-CAS-164 / T,R / / /
The CAS video I/F shall withstand to drive without loss of any performance the non operating IDE-CVE (redundant unit in nominal case).
Isolation specification Signal
x : N or R Resistance (MOhm) Capacitance (nF)
MCLK_IDE_x LVDS high impedance state TBD
IDE_SYNC_REF_x refer to GDIR refer to GDIR
CAS_x_VANA_P : RTN line
CAS_x_VANA_N : RTN line
CAS_x_VDIG : RTN line
CAS_x_VBIAS : RTN line
CAS_VID_OUT_x : + and RTN lines
CAS_PIXCLK_x : + and RTN lines
CAS_VALID_x : + and RTN lines
> 10
< 50
Table 9.1-1: IDE Electrical interfaces characteristics in OFF state
9.2 CAS POWER-on sequence
IF-IDE-CAS-168 / T,R / / /
Requirement for CAS :
CAS shall meet its functionalities and performances, as soon as all CAS voltages supplies being switched ON, without any specific order between all Power lines from the IDE-CVE (N or R).
Requirement for IDE :
With the specified way of powering CAS (refer to IDE specification) , the IDE shall switch the four CAS voltages within a maximum duration of 100 ms.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 38 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
9.3 CAS POWER-OFF sequence
IF-IDE-CAS-170 / T,R / / /
Requirement for CAS :
The CAS shall meet its functionalities and performances after being switched OFF without any time phasing between all Power lines from IDE, and ON in accordance with IF-IDE-CAS-168.
9.4 Failure cases at IDE-CAS interfaces
9.4.1 CAS voltages supplies
IF-IDE-CAS-173 / T,R / / /
Protection against over voltage :
In case of failure, the IDE shall guarantee to provide the CAS with voltages supplies in the range as specified in Table 6.1-1.
IF-IDE-CAS-174 / T,A / / /
The CAS shall withstand without any damage or stress maximum voltages supplies as specified in Table 6.1-1.
IF-IDE-CAS-312 / T,A / / /
The CAS shall withstand on any power line, without any damage or stress, 0 V voltages supplies up to its nominal values, as specified in Table 6.1-1.
9.4.2 Clock signals
IF-IDE-CAS-176 / T,R / / /
Refer to Section 7.
9.4.3 Video signals
IF-IDE-CAS-178 / T,R / / /
The IDE shall be protected against a constant absolute voltage in the range to [ - 18 V ; + 18 V] applied to its video input voltage.
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 39 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
CHANGE LOG
Note: This log is autogenerated from Doors. Special symbols may not be rendered correctly and hence the main body of the document shall always take precedence for requirements. Thus it should only be used as a guide to the modifications in the document and not as a substitute. Modified Objects The following table shows the new and old values of each modified attribute. The codes used in the object type (OT) column are: Rq = Requirement, Inf = Information, Hd = Heading, TC = Table Cell, Ah = Applicability Matrix Heading, Ar = Applicability Matrix Requirement Identifier Attribute OT New Text Old Text IF-IDE-CAS-51 section 5.1
Object Text Inf CAS video interface signals :The CAS provides the IDE with an analogue video interface (corresponding to CAS-MCCD) defined by three signals :CAS Video out "CAS_VID_OUT" :Video signal from the output (read-out register) of the CAS-MCCD. AC coupled, source terminated, known impedance shielded twisted pair cabling.Signal level of 2 V (TBC) between the reset level and the video level being the full scale.4.5 MHz bandwidth with 100 Hz low-frequency cut-off (TBC).CAS Pixel Clock "CAS_PIXCLK" :Clock synchronised to the video.The rising edge of "CAS_PIXCLK" will indicate the start of the reference level of the video signal while the falling edge of "CAS_PIXCLK" indicated the start of the video level of the CAS-MCCD video signal.CAS Pixel Valid signal "CAS_VALID" :When at a high level, it indicates that the analogue pixel signal has a video signal from the acquired pixel part of the sequence. These pixels are to be stored for further processing. All pixels are to be checked for over-range.
CAS video interface signals :The CAS provides the IDE with an analogue video interface (corresponding to CAS-MCCD) defined by three signals :CAS Video out :Video signal from the output (read-out register) of the CAS-MCCD. AC coupled, source terminated, known impedance shielded twisted pair cabling.Signal level of 2 V (TBC) between the reset level and the video level being the full scale.4.5 MHz bandwidth with 100 Hz low-frequency cut-off (TBC).CAS Pixel Clock :Clock synchronised to the video to enable Correlated Double Sampling (CDS) of the analogue video signal. The rising edge will indicate the start of the reset period of the video signal while the falling edge indicated the start of the video level period of the video signal.CAS Pixel Valid signal :When at a high level, it indicates that the analogue pixel signal has a video signal from the acquired pixel part of the sequence. These pixels are to be stored for further processing. All pixels are to be checked for over-range.
IF-IDE-CAS-53 section 5.1
OLE Inf Figure/Table modified
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 40 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Identifier Attribute OT New Text Old Text IF-IDE-CAS-69 section 5.4
Object Text Rq The overall length of the harness between CAS and IDE shall be specified without contingency through CAS/IDE harness IRD.
The overall length of the harness between CAS and IDE shall be 3 m (+ 0 / - 1), value TBC.
IF-IDE-CAS-109 section 7.1
Object Text Rq Electrical Requirements :"MCLK_IDE” signal drivers and receivers implementation within IDE and CAS shall be as specified in Table IF-IDE-CAS-111.
Electrical Requirements :Drivers and receivers implementation within IDE and CAS shall be as specified in Table IF-IDE-CAS-111.
IF-IDE-CAS-111 section 7.1
Object Text Inf [wdTCaption: “MCLK_IDE” driver and receiver implementation at IDE and CAS level]
[wdTCaption: Driver and receiver implementation at IDE and CAS level (HF clock)]
IF-IDE-CAS-118 section 7.2
Object Text Rq “IDE_SYNC_REF” shall be compliant with the following requirements : Frequency : Nominal : 51 Hz Range : (+ 10 %; - 0 %) Jitter : < 10 ns
“IDE_SYNC_REF” shall be compliant with the following requirements : Frequency : Nominal : 51 Hz (+ 10 %; - 0 %) Range : 50 Hz - 100 Hz Jitter : < 10 ns
IF-IDE-CAS-120 section 7.2
OLE Inf Figure/Table modified
IF-IDE-CAS-121 section 7.2
Object Text Inf [wdTCaption: “IDE_SYNC_REF” driver and receiver implementation at IDE and CAS level]
[wdTCaption: Driver and receiver implementation at IDE and CAS level (for synchronization)]
IF-IDE-CAS-122 section 8
Object Heading
Hd CAS video signal : CAS_VID_OUT
Video signals
IF-IDE-CAS-123 section 8.1
Object Heading
Hd CAS video signal phasing characteristics
Video signals phasing characteristics
IF-IDE-CAS-124 section 8.1
Object Text Rq The CAS video signal shall feature the phasing characteristics as specified in Table IF-IDE-CAS-126 and Figure IF-IDE-CAS-128.
The video signals shall feature the phasing characteristics as specified in Table IF-IDE-CAS-126 and Figure IF-IDE-CAS-128.
IF-IDE-CAS-126 section 8.1
Object Text Inf [wdTCaption: CAS video signal timing characteristics]
[wdTCaption: Video signals timing characteristics]
IF-IDE-CAS-127 section 8.1
OLE Inf Figure/Table modified
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 41 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Identifier Attribute OT New Text Old Text IF-IDE-CAS-128 section 8.1
Object Text Inf [wdFCaption: CAS video signal timing characteristics]
[wdFCaption: Video signals timing characteristics]
IF-IDE-CAS-129 section 8.2
Object Heading
Hd CAS video signal electrical characteristics
Video signals electrical characteristics
IF-IDE-CAS-130 section 8.2
Object Text Rq The CAS video signal shall feature the level characteristics as specified in Table IF-IDE-CAS-139 and defined in Figure IF-IDE-CAS-135 and in in Figure IF-IDE-CAS-137.Notes : Radiometric performances are specified within video signal range as defined in units specification requirements.
The video signals shall feature the level characteristics as specified in Table IF-IDE-CAS-139 and defined in Figure IF-IDE-CAS-135 and in in Figure IF-IDE-CAS-137.Notes : Radiometric performances are specified within video signal range as defined in units specification requirements.
IF-IDE-CAS-131 section 8.2
Object Text Rq High corner frequency :On CAS output, the video signal high corner frequency shall be at least 4.5 MHz.
High corner frequency :On CAS output, the video signal high corner frequency shall be at least 1 MHz.
IF-IDE-CAS-133 section 8.2
Object Text Rq Immunity to Common Mode perturbation :IDE shall fulfil its performances when video I/F is submitted to a 2.5 V Common Mode voltage up to 4.5 MHz.
Immunity to Common Mode perturbation :IDE shall fulfil its performances when video I/F is submitted to a 2.5 V Common Mode voltage up to 1 MHz.
IF-IDE-CAS-139 section 8.2
Object Text Inf [wdTCaption: CAS video signal level characteristics]
[wdTCaption: Video signals level characteristics]
IF-IDE-CAS-151 section 8.5
OLE Inf Figure/Table modified
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 42 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Identifier Attribute OT New Text Old Text IF-IDE-CAS-153 section 8.5
Object Text Rq From the CAS acquisition sequence identified above in Figure IF-IDE-CAS-152, the video data that are exchanged between the CAS and the IDE is described in the following Table IF-IDE-CAS-155, Table IF-IDE-CAS-286 and Table IF-IDE-CAS-288.These 3 Tables identify for each three successive acquisition (CAS background image 1 and 2 and CAS echo image within), the video data organization, at CAS output level (IDE I/F), in their order of read-out, the first useful pixels corresponding to echo/background image signal, followed at last by the chain offset pixels, the CAS Pixel Valid signal status being added in regard of each pixel value.
From the CAS acquisition sequence identified above in Figure IF-IDE-CAS-152, the video data that are exchanged between the CAS and the IDE is described in the following Table IF-IDE-CAS-155 to Table IF-IDE-CAS-159.These 3 Tables identify for each acquisition (CAS background image 1 and 2 and CAS echo image within), the video data organization at CAS output level in their order of read-out, the first useful pixels corresponding to echo/background image signal, followed at last by the chain offset pixels.
IF-IDE-CAS-153 section 8.5
Intended Verification Method
Rq TR R
IF-IDE-CAS-154 section 8.5
OLE Inf Figure/Table modified
IF-IDE-CAS-155 section 8.5
Object Text Inf [wdTCaption : CAS video Background Image 1 (CBI_1) data organization at CAS output / IDE I/F - read-out train n° 1]
[wdTCaption : CAS video Background Image 1 (CBI_1) data organization]
IF-IDE-CAS-252 section 10.2
Object Text TC CAS sub-contractor :
IF-IDE-CAS-255 section 10.2
Object Text TC <Name>
IF-IDE-CAS-270 section 8.2
Object Text Rq CAS Video Signal Electrical Requirements :CAS video signal drivers and receivers implementation within IDE and CAS shall be as specified in Table IF-IDE-CAS-272.
Video Signals Electrical Requirements :Video signals drivers and receivers implementation within IDE and CAS shall be as specified in Table IF-IDE-CAS-272.
Inserted Objects Identifier Object Type Text
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 43 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Identifier Object Type Text IF-IDE-CAS-274 section 10.1
TBD 03
IF-IDE-CAS-275 section 10.1
TBD
IF-IDE-CAS-276 section 10.1
TBD
IF-IDE-CAS-277 section 10.1
TBD after CAS KO
IF-IDE-CAS-278 section 8.4
Heading IDE-CAS video lines overshielding
IF-IDE-CAS-279 section 8.4
Requirement An overshielding of the video lines between IDE and CAS shall be implemented.This overshielding shall be based on a braided mesh solution, as presented in Figure IF-IDE-CAS-281, with components described in the following.
IF-IDE-CAS-280 section 8.4
Information
IF-IDE-CAS-281 section 8.4
Information [wdFCaption : IDE-CAS video lines overshielding principle]
IF-IDE-CAS-282 section 8.4
Information Mesh curtain :Reference: C.G.P : BLJ-R- X; Electrolytic copper; Silver plated 1,5 µmThis over shield is a single curtain made of silver plated copper braids meshing.The cables bundle is inserted into the mesh sleeve (no helix wrap around the bundle).The optical coverage of this over shield is 96%. The mesh curtain diameter fits closely with the bundle diameter.The mass of this braided over shield is 73 kg/km
IF-IDE-CAS-283 section 8.4
Information EMC back shell :Reference: POLAMCO : 100P 2315-15S-15-07 L50- CHP (P148663) (other supplier can be selected)Machined aluminium alloy 6082-T6, electroless Nickel-plated to MIL-C-26074, class 4, grade B, 13µm thick.
IF-IDE-CAS-284 section 8.4
Information Band it clamps :Reference : 600-052, stainless steel 300 SSTThe mesh curtain overlaps the back shell chimney. At both ends of the bundle, a Band It clamp squeezes and bonds the mesh on the back shell chimney over 360°.
IF-IDE-CAS-285 section 8.5
Information
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 44 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Identifier Object Type Text IF-IDE-CAS-286 section 8.5
Information [wdTCaption : CAS video Echo Image 1 (CEI_1) data organization at CAS output / IDE I/F - read-out train n° 2]
IF-IDE-CAS-287 section 8.5
Information
IF-IDE-CAS-288 section 8.5
Information [wdTCaption : CAS video Background Image 2 (CBI_2) data organization at CAS output / IDE I/F - read-out train n° 3]
IF-IDE-CAS-289 section 7.3
Heading CAS Pixel Clock : CAS_PIXCLK
IF-IDE-CAS-290 section 7.3
Requirement The CAS shall generate 1 clock signal towards IDE called “CAS_PIXCLK”, for IDE synchronisation purpose.This Clock shall be synchronised to the video.
IF-IDE-CAS-291 section 7.3
Requirement The rising edge of "CAS_PIXCLK" will indicate the start of the reference level of the video signal while the falling edge of "CAS_PIXCLK" indicated the start of the video level of the CAS-MCCD video signal.
IF-IDE-CAS-292 section 7.3
Requirement The circuit implemented in the IDE and in the CAS shall be compliant to electrical characteristics of Table IF-IDE-CAS-298.
IF-IDE-CAS-295 section 7.3
Requirement The “CAS_PIXCLK” signal characteristics shall be compliant with the following requirements (TBC) :The signal specific characteristics are the following :Frequency : Nominal : 888.888 kHzRange : TBCJitter : < TBC nsecDuty Cycle : TBC
IF-IDE-CAS-296 section 7.3
Requirement Electrical Requirements :"CAS_PIXCLK" signal drivers and receivers implementation within IDE and CAS shall be as specified in Table IF-IDE-CAS-298.
IF-IDE-CAS-297 section 7.3
Information
IF-IDE-CAS-298 section 7.3
Information [wdTCaption: "CAS_PIXCLK" driver and receiver implementation at IDE and CAS level]
IF-IDE-CAS-299 section 7
Requirement For all signals defined in this section, IDE and CAS shall fulfil the cross-strapping principle defined in Section IF-IDE-CAS-55.Protection and Immunity shall comply with GDIR.
IF-IDE-CAS-302 section 7.4
Heading Synchronisation signal : CAS_VALID
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 45 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Identifier Object Type Text IF-IDE-CAS-303 section 7.4
Requirement The CAS shall generate 1 synchronisation signal towards IDE called “CAS_VALID”, for .validation purpose.When at a high level, it indicates that the analogue pixel signal has a video signal from the acquired pixel part of the sequence. These pixels are to be stored for further processing. All pixels are to be checked for over-range.
IF-IDE-CAS-305 section 7.4
Requirement The circuit implemented in the IDE and in the CAS shall be compliant to electrical characteristics of Table IF-IDE-CAS-310.
IF-IDE-CAS-306 section 7.4
Requirement The inactive level of this signal shall be Logical 0.
IF-IDE-CAS-307 section 7.4
Requirement The active level of all these signals shall be : T(active) duration (Ta) : TBD µsec < Ta < TBD µsec
IF-IDE-CAS-308 section 7.4
Requirement “CAS_VALID” shall be compliant with the following requirements : Frequency : Nominal : TBD Hz Range : TBD Jitter : < TBD ns
IF-IDE-CAS-309 section 7.4
Information
IF-IDE-CAS-310 section 7.4
Information [wdTCaption: “CAS_VALID” driver and receiver implementation at IDE and CAS level]
IF-IDE-CAS-312 section 9.4.1
Requirement The CAS shall withstand on any power line, without any damage or stress, 0 V voltages supplies up to its nominal values, as specified in Table IF-IDE-CAS-79.
Deleted Objects IF-IDE-CAS-112 section 7.1 : Requirement IF-IDE-CAS-119 section 7.2 : Requirement IF-IDE-CAS-156 section 8.4 : Information IF-IDE-CAS-157 section 8.4 : Information IF-IDE-CAS-158 section 8.4 : Information IF-IDE-CAS-159 section 8.4 : Information 65 differences found Total number of requirements = 75 Number of inserted requirements = 13 Number of changed requirements = 9 Number of unchanged requirements = 53 Number of deleted requirements = 2
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 46 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
Requirement/Section Cross Reference Page numbers are the pages where the sections start
IF-IDE-CAS-13 ... 1.3....................8 IF-IDE-CAS-14 ... 1.3....................8 IF-IDE-CAS-28 ... 3.3....................10 IF-IDE-CAS-36 ... 4.......................12 IF-IDE-CAS-37 ... 4.......................12 IF-IDE-CAS-38 ... 4.......................12 IF-IDE-CAS-39 ... 4.......................12 IF-IDE-CAS-40 ... 4.......................12 IF-IDE-CAS-41 ... 4.......................12 IF-IDE-CAS-42 ... 4.......................12 IF-IDE-CAS-43 ... 4.......................12 IF-IDE-CAS-61 ... 5.3....................15 IF-IDE-CAS-65 ... 5.4....................16 IF-IDE-CAS-66 ... 5.4....................16 IF-IDE-CAS-67 ... 5.4....................16 IF-IDE-CAS-68 ... 5.4....................16 IF-IDE-CAS-69 ... 5.4....................16 IF-IDE-CAS-72 ... 6.1....................17 IF-IDE-CAS-73 ... 6.1....................17 IF-IDE-CAS-74 ... 6.1....................17 IF-IDE-CAS-75 ... 6.1....................17 IF-IDE-CAS-76 ... 6.1....................17 IF-IDE-CAS-77 ... 6.1....................17 IF-IDE-CAS-83 ... 6.1....................17 IF-IDE-CAS-86 ... 6.1....................17 IF-IDE-CAS-90 ... 6.2....................22 IF-IDE-CAS-91 ... 6.2....................22 IF-IDE-CAS-92 ... 6.2....................22 IF-IDE-CAS-93 ... 6.2....................22 IF-IDE-CAS-96 ... 6.3....................22 IF-IDE-CAS-97 ... 6.3....................22 IF-IDE-CAS-104 . 7.1....................24 IF-IDE-CAS-105 . 7.1....................24 IF-IDE-CAS-106 . 7.1....................24 IF-IDE-CAS-107 . 7.1....................24 IF-IDE-CAS-108 . 7.1....................24 IF-IDE-CAS-109 . 7.1....................24 IF-IDE-CAS-114 . 7.2....................25 IF-IDE-CAS-115 . 7.2....................25 IF-IDE-CAS-116 . 7.2....................25 IF-IDE-CAS-117 . 7.2....................25 IF-IDE-CAS-118 . 7.2....................25 IF-IDE-CAS-124 . 8.1....................28 IF-IDE-CAS-130 . 8.2....................29 IF-IDE-CAS-131 . 8.2....................29 IF-IDE-CAS-132 . 8.2....................29 IF-IDE-CAS-133 . 8.2....................29 IF-IDE-CAS-141 . 8.3....................31 IF-IDE-CAS-142 . 8.3....................31 IF-IDE-CAS-143 . 8.3....................31 IF-IDE-CAS-153 . 8.5....................33 IF-IDE-CAS-162 . 9.1....................37 IF-IDE-CAS-163 . 9.1....................37 IF-IDE-CAS-164 . 9.1....................37
IF-IDE-CAS-168..9.2 ................... 37 IF-IDE-CAS-170..9.3 ................... 38 IF-IDE-CAS-173..9.4.1 ................ 38 IF-IDE-CAS-174..9.4.1 ................ 38 IF-IDE-CAS-176..9.4.2 ................ 38 IF-IDE-CAS-178..9.4.3 ................ 38 IF-IDE-CAS-269..7.2 ................... 25 IF-IDE-CAS-270..8.2 ................... 29 IF-IDE-CAS-279..8.4 ................... 32 IF-IDE-CAS-290..7.3 ................... 26 IF-IDE-CAS-291..7.3 ................... 26 IF-IDE-CAS-292..7.3 ................... 26 IF-IDE-CAS-295..7.3 ................... 26 IF-IDE-CAS-296..7.3 ................... 26 IF-IDE-CAS-299..7 ...................... 24 IF-IDE-CAS-303..7.4 ................... 26 IF-IDE-CAS-305..7.4 ................... 26 IF-IDE-CAS-306..7.4 ................... 26 IF-IDE-CAS-307..7.4 ................... 26 IF-IDE-CAS-308..7.4 ................... 26 IF-IDE-CAS-312..9.4.1 ................ 38
Ref.: EC.RS.ASF.ATL.00051 Issue: 03 Rev: 00
Date: 23/11/2011 Page 47 of 47
The copyright in this document is the property of EADS ASTRIUM SAS and the contents may not be reproduced or revealed to third parties without prior permission of that company in writing. © EADS Astrium
DOCUMENT CHANGE DETAILS
ISSUE CHANGE AUTHORITY CLASS RELEVANT INFORMATION/INSTRUCTIONS 01 for CAS ITT 02 for IDE KO 03 after CAS KO
DISTRIBUTION LIST
INTERNAL EXTERNAL ASD : C. DELETTREZ U. SLANSKY L. LE HORS R. MUNZENMAYER Y. LEVILLAIN J. PILLER L. MAZURAY J-C. NONNET ESA : F. OLIVIER A. HELIERE D. PIBRAC N. NELMS P. THORAL Y. TOULEMONT CRISA : C. CARRETERO Configuration Management
