1

Abstract—A new family of switching amplifiers, each memberhaving some of the features of both class E and inverse F, isintroduced. These class E/F amplifiers have class-E featuressuch as incorporation of the transistor parasitic capacitanceinto the circuit, exact truly-switching time-domain solutions,and allowance for Zero Voltage Switching (ZVS) operation.Additionally, some number of harmonics may be tuned in thefashion of inverse class F in order to achieve more desirablevoltage and current waveforms for improved performance.Operational waveforms for several implementations arepresented, and efficiency estimates compared to class-E.

Index terms—Class E, Class F, Class E/F, ZVS, switchingpower amplifier, power efficiency.

I. INTRODUCTION

For power amplifier and power inverter applications,harmonic-tuned switching amplifiers such as class E [1, 2]and class F [3] offer high efficiencies at high powerdensities. By operating the active device as a switch ratherthan a controlled current source, the voltage and currentwaveforms can in principle be made to have no overlap,reducing the theoretically achievable device dissipation tozero. At the same time, unlike high-efficiency class-Coperation, the output power of switching modes iscomparable to or greater than that of class A or class B forthe same device peak voltage and current. For applicationswherein AM/AM and AM/PM nonlinearities can betolerated [4], or compensated for [5], such amplifiers canbe used to improve power efficiency and reduce heat sinkrequirements. High-speed power control circuits, such asdc-dc converters, similarly benefit from improvements in rfpower amplifier efficiency [6].

Unfortunately, only two types of amplifier tuningsappropriate for high-frequency operation, class E andclass F, have been explored. Class-E amplifiers have foundmost application as a higher-performance alternative toclass-D amplifiers, due to their compensation for transistoroutput capacitance and elimination of turn-on switchinglosses. Additionally, the class-E design may beimplemented with a relatively simple circuit. Thesebenefits have allowed class-E designs to push far beyondthe frequencies achievable by class-D designs, with recentresults reporting 55% at 1.8GHz using CMOS devices [7]and 74% at 800 MHz using GaAs HBT devices [8].

Class F and its recently popularized dual, inverse class F(class F-1) [9, 10, 11], have been developed primarily as ameans of increasing saturated performance of class-AB andclass-B designs. As a result, the operating frequenciesattainable have usually been somewhat higher [e.g. 5, 12]than those for class E circuits, but the performancelimitations due to the tuning requirements [13, 14] and thelack of a simple circuit implementation [e.g. 15] suitablefor nearly ideal switching conditions make this design apoor alternative at frequencies where a lumped-elementclass E can be implemented.

Nevertheless, there is reason to believe the waveformsachievable in principle by class F and/or F-1 should allowperformance benefits over class-E. Although Raab hasrecently shown that the efficiency of properly-tuned class Eand class F are identical if the efficiency is limitedprimarily by the harmonic content of the drain waveforms[16], the optimal performances when the transistor isswitching nearly ideally and the efficiency is limitedprimarily by the device’s on-resistance would seem to favorclass F and F-1 with their reduced peak voltages and, in thecase of class F-1, RMS current. Additionally, the class-Eapproach has limited tolerance for large transistor outputcapacitance [17], providing an identifiable limit to thisclass’s high frequency performance.

This paper presents a new family of harmonic tunings withthe promise to achieve the performance benefits of class Fby reducing the peak voltage and RMS current of class Edesigns. Additionally, this tuning method allows increasedtolerance to large transistor output capacitance, improvingthe high-frequency performance and extending thefrequency range of this new tuning beyond that of class E.This new E/F family of tunings unifies class E and class F-1

into a single framework, and demonstrates varying degreesof trade-off between the simplicity of class E and the highperformance of class F-1. All members of the E/F familyhave exact time-domain solutions, can be made to achieveclass-E switching conditions, and have circuitimplementations wherein the output capacitance of theswitch is explicitly accounted for.

This technique has been used to implement severalamplifiers at HF and microwave frequencies. The E/F2,odd

tuning has been used in the construction of a compact,high-efficiency power amplifier producing in excess of

Scott Kee, Ichiro Aoki, Member, IEEE, Ali Hajimiri, Member, IEEE, and David Rutledge, Fellow, IEEE

The Class E/F Family ofZVS Switching Amplifiers

2

1kW at 7MHz [18]. Using a similar design modified toachieve the E/Fodd tuning in the 7MHz and 10MHz bands,achieves over 200W of output power in each of these bandswith drain efficiencies higher than 90% [19]. Anotherfully-integrated CMOS amplifier uses the E/F3 mode toproduce 2.2W of output power at 2.4GHz [20]. This resultuses the distributed active transformer on-chip matchingand power combining structure [21, 22], which is notcompatible with either the class-E or class-F tunings. Inthis case, the E/F technique enables the use of a saturatedamplifier mode in the DAT power combining structure.

II. CLASS E AND CLASS F

This section reviews both class-E and class-F operatingmodes, comparing their relative advantages anddisadvantages. Finally, a “wish list” is presented ofproperties desirable in any hypothetical new tuning.

A. Class E

The class-E tuning approach, depicted in Fig. 1, has beendeveloped [1, 2, 23] mainly as a time-domain technique,with the active device treated as a nearly ideal switch.Specifically, the switch is assumed to be effectively open-circuit during the “off” duration and a perfect short-circuitduring the “on” duration, and that the time required toswitch between states is effectively zero. These conditionswill be denoted as strong switching.

f0

CS

XL

RL

L1

C1

I1

IDC

IX

Fig. 1. Class-E amplifier topology.

Under strong switching, a common problem is efficiencydegradation due to discharge of the switching device’soutput capacitance. If the voltage across the switch prior toa transition from the “off” state to the “on” state isnonzero, the energy stored in this capacitance is dissipatedby a discharge current through the switch. Since thisoccurs once per cycle, this loss increases linearly with theoperating frequency and can be considerable even atrelatively low frequencies. As a result, much effort hasbeen devoted to finding means of eliminating this lossmechanism [e.g. 2, 6, 24]. The class-E approach is onesuch method, wherein the switch voltage is driven to zeroprior to turn-on by an appropriately tuned resonant circuit.This technique is known as zero voltage switching (ZVS).

Using the circuit of Fig. 1, the switch is made to conductwith 50% duty cycle at frequency f0, and its parasiticoutput capacitance is absorbed into the switch parallel

capacitance CS. The resonator consisting of L1 and C1 isused to block the harmonic frequencies and dc, forcing thecurrent I1 to be a sinusoid with frequency f0. The choke isassumed to be ideal, so that it can only conduct the dccurrent IDC. The current into the switch/capacitorcombination IX must then be a dc offset sinusoid.

This current will be commutated between the capacitor andthe switch, depending on the switch’s state. When theswitch is closed, the voltage is forced to zero, fixing thecapacitor’s charge, thus forcing the current through theswitch. When the switch is open the capacitor mustconduct the current. By appropriately adjusting theamplitude and phase of the sinusoidal component of thecurrent, a solution is found wherein the capacitor charge iszero just prior to switch turn-on. This leaves an additionaldegree of freedom which is typically used to also set thecapacitor current at zero just before turn-on. This resultsin a switching waveform with zero voltage (no capacitorcharge) and zero voltage slope (no capacitor current) atturn-on, conditions now known as the class-E switchingconditions. The resulting switch voltage and currentwaveforms are depicted in Fig. 2.

Fig. 2. Class-E amplifier dc normalized waveforms.

B. Class F and Class F-1

The class-F approach has been developed [3, 13] in thefrequency domain as a means of increasing the efficiencyof class A/B and class B amplifiers. Rather than using thestrong-switching assumption, it is assumed that theamplifier has reached only a limited degree of compressionso that a relatively small number of harmonics have beengenerated at the drain. Although the transistor is acting asa switch for some parts of the cycle, it is spendingconsiderable time transitioning between switching states,where this time is limited by the harmonic composition ofthe drain waveforms. The class-F approach seeks todetermine how best to utilize these few harmonics toimprove efficiency.

A class-F amplifier implementation is depicted in Fig. 3.Starting with a standard class-B amplifier wherein aparallel resonant filter is used to force the load voltage tobe sinusoidal, additional resonators are added in serieswith the load/resonator combination in order toopen-circuit the transistor drain at the low order odd

3

harmonics to be tuned. By doing this, the compressedvoltage waveform will begin to increasingly resemble asquare wave as the generated odd harmonics will tend toflatten the top and bottom of the waveform simultaneously,as can be seen in Fig. 4. This flattening decreases thevoltage across the transistor during the times for whichthere is current through it, increasing the efficiency. Themore harmonics open-circuited, the greater the flatteningand the higher the resulting efficiency will be. Thewaveform will ultimately become the same as the class-Dsquare-wave when all harmonics have been tuned.

Fig. 3. Example class-F amplifier topology.

The efficiency increase beyond the class-B theoretical limitof 78% is substantial for the low order harmonics butdiminishes rapidly with increasing harmonic number. Forinstance, if the harmonics appear in a manner so as tomake the voltage waveform maximally flat at the voltageminimum point [13], the resulting maximum efficienciesfor tuning up to the 3rd 5th and 7th harmonics will be 88%92% and 94% respectively. In the limiting case, whereinthe number of tuned harmonics approaches infinity, thevoltage waveform is a square wave and the efficiency limitis 100%, as in the class-E case. These maxima are set bythe tuning strategy and will be further degraded by suchfactors as the transistor on-resistance, switching speed,passive losses, etc.

Fig. 4. Class-F maximally-flat dc normalized waveforms forvarious numbers of harmonics tuned and class-B drive conditions.

Class F-1 is the dual tuning of class F. Where class Fshort-circuits even harmonics and open-circuits oddharmonics, class F-1 open-circuits the tuned evenharmonics and short-circuits the tuned odd harmonics.This has the effect of interchanging the voltage and currentwaveforms, so that as the number of tuned harmonicsincreases, the voltage waveform increasingly resembles a

half-sinusoid and the current waveform increasinglyresembles a square wave. Several recent studies suggestthat class F-1 compares favorably to class F [10, 11],although the efficiency limits imposed by the waveformsare the same [16]. Example waveforms for a class F-1

amplifier are shown in Fig. 5.

Fig. 5. Class F-1 maximally-flat dc normalized waveforms fortuning up to the 3rd harmonic. Dotted line waveforms representthe limiting case wherein the number of harmonics tuned isinfinite.

C. Comparison and Motivation for E/F

Comparing class E to the two class F tunings, severaladvantages and disadvantages are apparent. The class-Ecase has the advantage of being capable of strong-switching operation even with a very simple circuit,whereas class F allows this only as a limiting case using acircuit with great complexity. From Fig. 4 it is easily seenthat even with tuning up to the 9th harmonic, the voltageand current waveform exhibit significant overlap.Whereas the class-E amplifier is limited only by theintrinsic switching speed of the active device, class-Famplifier tunings may find their switching speeddominated by the limited number of harmonics which havebeen utilized in the waveforms.

Additionally, class E has the advantage of incorporatingthe output capacitance of the transistor into the circuittopology. A simple class-F implementation as shown inFig. 3 will not work in the presence of large outputcapacitance, since the harmonics which were intended tobe open-circuited at the transistor will instead becapacitive. Although a tuning network can beimplemented to resonate with the output capacitance inorder to produce open-circuits at each required frequency,this technique adds significant design complexity andtuning difficulty. The class-E tuning not only allows thecapacitance to be absorbed into the basic network, but alsoallows for ZVS operation, eliminating discharge lossesfrom this capacitor. The tuning of class-E circuits is alsovery simple, requiring only one parameter to be adjusted toachieve high efficiency ZVS operation.

Class-F and Class F-1 also have advantages. First, theypresent more desirable waveforms in the limiting, strong-

4

switching case. As will be explained in the followingsection, it is desirable to have waveforms with low peakvoltage and RMS current. Examining the waveforms ofFig. 2, Fig. 4, and Fig. 5, it is clear that class-F amplifierscan perform better in these respects.

Additionally, the allowable output capacitance in theclass-E case is limited. The switch parallel capacitance CS,which must be at least as large as the transistor outputcapacitance, is determined by the output power, dc voltage,and operating frequency. This restriction on the size of thetransistor may limit the performance of class-E amplifiers[17]. Class-F tunings, however, can in principle utilize atransistor with any output capacitance provided that it isproperly resonated out at the appropriate frequencies.Although this approach might be used to resonate part ofthe output capacitance of a class-E tuned transistor at eachharmonic, the resulting circuit complexity would be at leastthat of class F. Since class-F tunings present betterwaveforms, it would seem to be a poor approach. It wouldbe better, if possible, to find a tuning strategy that increasesthe capacitance tolerance without adding such complexity.

These issues motivate the search for more desirablestrong-switching amplifier tunings which would, ideally,have some of the best features of both the class-E andclass-F tunings. If such a harmonic tuning strategy is to befound, it would ideally have the following features:

� Incorporation of the transistor output capacitanceinto the tuned circuit, where this capacitance maybe as large as possible.

� Zero voltage switching (ZVS) to eliminatedischarge loss from this capacitor.

� Simple circuit implementation.� Use of harmonic tuning to achieve improved

waveforms for improved performance.

III. WAVEFORM EVALUATION

The final point on the above “wish list” needs furtherclarification. To compare “performance” of tunings, it isnecessary to have a figure of merit for harmonic tunings.Accordingly, this section introduces methods ofapproximating strong-switching amplifier performancefrom properties of the switching waveforms. First,however, it is necessary to visit some properties ofswitching amplifiers, to understand what a “tuning” is andhow one changes under scaling of voltage and impedance.Additionally, a simple active device model will benecessary.

In the most general sense, a switching amplifier consists ofa periodically driven switch connected to a passive loadnetwork, which is assumed to be linear and time-invariant(LTI). This one-port load network includes any matchingnetwork, dc feed, and the load to be driven. The switchpresents a time-varying conductance, alternating between

very high conductance (i.e. switch “on”) and very lowconductance (i.e. switch “off”). This has the effect offorcing the voltage to nearly zero for the “on” duration ofthe cycle and the current to be nearly zero for the “off”duration, but leaves the waveforms otherwiseunconstrained.

The voltage waveform during the “off” portion of the cycleand the current waveform during the “on” portion aredetermined by the load network. Since this load network islinear and time-invariant (LTI), its properties may bespecified by its input impedance as a function of frequency.If the waveforms are periodic, this impedance is relevantonly for the fundamental and harmonic frequencies.Therefore, the network properties determining theswitching amplifier waveforms are completely specified bythe impedance presented to the switch at the integermultiples of the fundamental frequency.

Fig. 6. General harmonic tuned switching amplifier circuitincluding switch output capacitance.

A generalized network suitable for implementation of mostswitching amplifiers is shown in Fig. 6. This topologyrepresents the case where the switch is presented acapacitance, consisting partially of its own outputcapacitance, and a number of harmonic filters. Eachharmonic filter presents a desired impedance at theharmonic it tunes, while leaving other harmonicsunaffected. Thus the circuit describes all switchingamplifiers for which the impedance presented to the switchis capacitive at all harmonics except for a finite number oftuned harmonics.

A. Scaling Properties

It is possible to analytically determine the switchingwaveforms of any circuit of the type shown in Fig. 6 [27].Supposing the waveforms for one such circuit are known, itis useful to know how these waveforms change undersimple scaling conditions. Then, if waveforms can befound for one case, scaled solutions may be easilydetermined.

5

The first scaling technique needed for the results of thispaper is bias scaling. Consider an amplifier whosesolution is known for a given load network and dc biasvoltage VDD. Suppose it is desired to find the waveformsthis amplifier under a bias of DDV⋅α . Since the circuit is

linear, albeit time varying due to the changing conductanceof the switch, the scaled solution is simply the originalvoltage and current waveforms each scaled by a factor of α.For instance, if the original current and voltage waveformsare Iold(t) and Vold(t) respectively, the scaled current andvoltage waveforms Inew(t) and Vnew(t) are:

)()( tVtV oldnew ⋅= α (1)

)()( tItI oldnew ⋅= α (2)

The second scaling technique is impedance scaling.Consider an amplifier whose solution is known for a givenload network and dc bias voltage. Suppose it is desired toknow the waveforms for an amplifier operating at the samebias voltage, but with a load network presentingimpedances Znew(k) at each harmonic number k, equal to

)(kZold⋅α for some real number α, where Zold(k) is the

impedance presented by the original network. It is easilyverified that the following scaled current and voltage,Inew(t) and Vnew(t) respectively, provide the correctwaveforms provided that Iold(t) and Vold(t) were waveformsof the original amplifier:

)()( tVtV oldnew = (3)

( ) )(1)( tItI oldnew ⋅= α (4)

By utilizing these two scaling techniques, the initialsolution may be transformed to have any desiredindependent scaling of the voltage and current waveforms.Since the waveforms of such a group of transformedamplifiers are identical in shape, and since the topology ofthe circuits utilized by the amplifiers may be identical, theamplifiers within the group are considered to be utilizingthe same tuning strategy or class of operation. Thus whencomparing methods for harmonic tuning, it is implicit thatthe comparison is between the best amplifiers from eachtuning group.

B. Simple FET Switch Model

A simple model for the non-ideality of the switch is alsorequired. Unlike in amplifiers operating in classes A, B,C, or F, strong-switching amplifiers do not have anyfundamental requirement for overlap between the voltageand current waveforms. Therefore, if the switch wereideal, the efficiency of every possible tuning would be100%, rendering efficiency comparisons between tuningspointless. Switch non-ideality, however, degradesperformance to below this theoretical maximum in amanner which is dependent on the properties of theharmonic-tuning.

Fig. 7. Simple FET switch model.

Although bipolar switches have been popular and aresuitable for many switching applications, the most capablehigh frequency switching devices are field effect transistors(FETs). A simple model suitable for FET switchingdevices is shown in Fig. 7. This model includes anon-resistance, a linear output capacitance, and a simplenetwork for input power approximation. Although notexplicitly shown, it should be understood that the inputpower is a function of the desired frequency of operation.Up to the breakdown voltage Vbk of the switch, the off-stateconductance of the switch is assumed to be zero. While thismodel should not be expected to predict performance withgreat accuracy, it is useful for comparisons betweencompeting tuning strategies as it captures the first ordernon-ideal effects of FET switches.

Another important factor is the scalability of FET switches.By varying the effective gate width, the device properties inany given technology may be modified to suit thedesigner’s needs. As the device size is increased, the on-resistance decreases, the output capacitance increases, andthe input power required to drive the transistor intoswitching mode increases. In FETs, these parameters varylinearly or inversely with the device size. For instance, ifthe on-resistance, output capacitance, and input power for

a given device are onR , outC , and inP respectively, then

the parameters for a device scaled by a factor of λ are:

( ) onon RR ⋅= λ1 (5)

outout CC ⋅= λ (6)

inin PP ⋅= λ (7)

Reduction in on-resistance is beneficial to the performance,but increase of output capacitance and input power areundesirable. Therefore, it should be expected that there isan optimal FET device size for a given technology andtuning strategy. Accordingly, comparisons betweendifferent tunings should assume the best combination ofwaveform scaling factors and device size.

C. Assumptions and Limitations

Certain assumptions and design limitations help simplifythe analysis. First, the effect of the non-idealities on theshape of the switching waveforms will be assumed to besmall, so that the conduction loss, Pcond, may be calculated

6

using the RMS value, IRMS, of the switch current waveformfor the case of an ideal switch:

onRMScond RIP 2≈ (8)

Using this and assuming that ZVS switching conditionsare met so that no discharge loss occurs, the drainefficiency η can be calculated to be:

DCDC

onRMS

DC

condDC

DC

out

IV

RI

P

PP

P

P 2

1 −≈−

=≡η (9)

where Pout is the output power, VDC is the dc drain voltage,and IDC is the dc drain current. Using this drain efficiencyapproximation, the power added efficiency (PAE) is:

−

−≈

−≡

DCDC

onRMS

out

in

DC

inout

IV

RI

P

P

P

PPPAE

2

11 (10)

The chief design limitations assumed are that the peakvoltage must not exceed the breakdown voltage for thedevice technology, and that the switch output capacitanceshould not exceed the switch parallel capacitance CS.These two limitations enforce a maximum dc bias anddevice size, each dependant on the properties of the tuningstrategy.

D. Waveform Figures of Merit

Using the results of the previous sections, it is now possibleto estimate switching amplifier performance from the basicwaveforms of a tuning strategy. This section developsefficiency estimates under several design constraints.

1) Maximum Drain Efficiency, Fixed Device Size

Occasionally, the device size may be limited by economicor technological limitations to well below the theoreticalperformance-optimal size given the properties of thetechnology. This may occur at relatively low frequencieswhere the performance optimum would require anextremely large device size or for relatively newtechnologies where large devices are not available or areprohibitively expensive. Accordingly, it is desirable topredict the maximum performance of a tuning strategy fora given output power Pout, given that the device size issmall and fixed. It will be assumed that the device size issmall enough that the output capacitance will be smallerthan CS.

The terms of (9) may be rearranged to produce:

( )DCDCpk

on

DC

pk

DC

RMS IVV

R

V

V

I

I

−≈

2

22

1η (11)

The final term in this expression is the dc power

consumed, which is equal to ηoutP . Using this, (11) is

simplified to:

out

pk

on

DC

pk

DC

RMS PV

R

V

V

I

I

+≈ 2

22

2

1

2

1η (12)

This may be expanded into a Taylor series:

K−−−≈ 21 KKη (13)

where:

out

pk

on

DC

pk

DC

RMS PV

R

V

V

I

IK

≡

2

22

(14)

It is easily verified that the first term of K, the ratiobetween the RMS and dc switch currents, is constant underboth bias and impedance scaling, and is thus solelydetermined by the tuning strategy. Similarly, if Vpk is thepeak voltage across the switch, the second term is also afunction only of the tuning strategy. The final term issimply the output power, a design constraint. This leavesonly the third term. Since the efficiency (13) increaseswith increasing peak voltage, the maximum efficiency isachieved by setting this voltage as high as possible,resulting in a corresponding decrease in RMS current forthe same output power. Since the peak voltage limitationis a dependent solely on the transistor, the optimized thirdterm is a function only of the transistor technology. Thisoptimum occurs when the peak voltage is equal to thedevice breakdown Vbk:

out

bk

on

DC

pk

DC

RMS PV

R

V

V

I

IK

≡

2

22

(15)

For purposes of comparisons between tunings, up to thefirst order terms of (13) may be used under the assumptionthat the efficiency close to unity. Since the higher orderterms have negative coefficients, comparisons utilizing thissimplification will underestimate the true difference in theefficiency performance of the tunings being compared:

outbk

on

DC

pk

DC

RMS PV

R

V

V

I

I⋅

−≈

2

22

1η (16)

This expression indicates that a desirable tuning strategywould have a low RMS to dc current ratio and a low peakto dc voltage ratio. Similarly, a desirable FET devicewould have low on-resistance relative to the square of itsbreakdown voltage.

E. Maximum Drain Efficiency, Optimal Device Size

Another important case is the maximum drain efficiencyfor a given transistor technology where the optimal devicesize may be freely choosen. This might occur in caseswhere the cost of incremental device area is small, and thedevice gain is large, allowing the drive power to beneglected. Using a similar technique as before, (9) isrearranged as:

7

( )( )

−≈

out

Souton

DCS

DCDC

DC

RMS

C

CCR

VC

IV

I

I02

0

2

1 ωω

η (17)

As before, the purpose is to separate the effects ofwaveform and the transistor technology. The first term hasbeen encountered already and is a function only of thetuning strategy. The second term, is also found to beinvariant under both scaling techniques1, depending onlyon the tuning. The third term is a function only of thetransistor technology, being invariant under changes intransistor size. The next term indicates the lineardegradation in optimal performance over frequency.

This leaves the final term, representing the proportion ofthe switch parallel capacitance CS made up by the switch’sown output capacitance Cout. Since the transistor size isdetermined by the designer, this term represents a degreeof freedom to be optimized, with the constraint that Cout

cannot be greater than CS. Clearly the best choice is tochoose Cout as large as possible, thus the optimal devicesize has the transistor output capacitance making up theentirety of CS:

( )( )020

2

1 ωω

η outonDCS

DCDC

DC

RMS CRVC

IV

I

I

−≈ (18)

To illuminate the meaning of the somewhat mysterioussecond term, consider that VDCIDC is approximately theoutput power and that 1/(ω0CS) is the switch parallelcapacitor’s impedance magnitude at the fundamentalfrequency, ZC:

( )( )02

2

/1 ωη outon

CDC

out

DC

RMS CRZV

P

I

I

−≈ (19)

( )SC CZ 01 ω≡ (20)

Shown this way, the term can be viewed as a ratio betweenthe output power and the reactive power in the capacitanceCS. The term measures the tuning’s ability to utilize alarge output capacitance (therefore a high reactive power)without necessitating a very large output power. A smallervalue for this term allows a larger device size for any givenoutput power, reducing the on-resistance and theconduction loss.

From (19) it may be concluded that it is desirable to havetunings with low RMS to dc ratio in the currentwaveforms, and which tolerates a large switch parallelcapacitance relative to the output power for a given dcvoltage. Similarly, a good transistor technology should

1 Careful inspection also reveals this term to be invariant under changes in theoperating frequency as well, since the tuning strategy is defined in terms ofthe impedances presented at the harmonics, and thus ω0CS is constant for thesame tuning at different frequencies.

have a small RonCout product relative to the switchingperiod

F. Maximum PAE, Optimal Device Size

The final case to be considered is the maximum PAE for agiven transistor technology where the designer is free tochoose the optimal sized device. This is similar to theprevious case, except that the gain is low enough to be aconsideration.

There are actually two possible cases in this scenario.First, since the drain loss is inversely proportional to thetransistor size whereas the required input power isproportional to this size, there will be an optimum PAEpoint with minimum total loss. An amplifier operating atthis minimum may be said to be gain-limited, since anincrease in transistor size is inadvisable due to theresulting decrease in gain. This minimum may not beachievable, however, since it is possible that the outputcapacitance of a device with gain-limited size might exceedthe tuning’s switch parallel capacitance CS. Under thiscapacitance-limited condition, the best size will be thelargest possible given the capacitance constraint, i.e.wherein Cout = CS.

First the gain-limited case will be examined. Starting from(10), the transistor scaling rules of (5) – (7) are introduced:

⋅−

⋅−≈

λλ 1

112

DCDC

onRMS

out

in

IV

RI

P

PPAE (21)

Optimizing over λ for maximum PAE results in:

22

1

−≈

outDCDC

inonRMS

PIV

PRIPAE (22)

Using the approximation that the output power isapproximately the dc power, this becomes:

2

2 /1

−≈

onpk

in

DC

pk

DC

RMS

RV

P

V

V

I

IPAE (23)

The first two terms of this expression have beenencountered previously and are functions only of the tuningstrategy. The third term contains a degree of freedom, i.e.the peak voltage of the waveform. As before, the bestperformance is achieved by choosing this value as high aspossible, with the limiting case being the breakdownvoltage of the technology. Setting Vpk = Vbk renders thethird term a function only of the transistor technology,invariant under scaling of the transistor size:

2

2 /1

−≈

onbk

in

DC

pk

DC

RMS

RV

P

V

V

I

IPAE (24)

8

If the loss is small, this may be approximated as:

⋅−≈

onbk

in

DC

pk

DC

RMS

RV

P

V

V

I

IPAE

/21

2 (25)

From this result, it is clear that tunings with low RMS todc ratios on the current waveform and low peak to dc ratioson the voltage waveform are desirable.

The capacitance-limited case is very similar to the case ofmaximum drain efficiency explored in the previous section.In particular, the transistor size will be the same, so thatthe drain efficiencies are identical. Thus, to calculate thePAE, it is only necessary to calculate the input power inthe case wherein Cout = CS and Vpk = Vbk. First noticingthat the ratio of Cout to Pin is constant over changes in thetransistor size, the input power may be expressed as:

inout

Sin

out

outin P

C

CP

C

CP == (26)

Inserting this into the PAE expression, results in:

η⋅

−=

outout

Sin

CP

CPPAE 1 (27)

Rearranging, keeping in mind that Vpk = Vbk, yields:

ηω

⋅

−=

0

22

2

1/1

DC

pk

out

CDC

bkout

in

V

V

P

ZV

VC

PPAE (28)

Combining this with (19) yields:

( )( )[ ]02

0

2

2

1

11

ω

ω

outonCI

C

V

bkout

in

CRFF

F

F

VC

PPAE

−⋅

−=

(29)

where the waveform factors have been represented as:

DCpkV VVF /≡ (30)

DCRMSI IIF /≡ (31)

CDC

outC

ZV

PF

/2≡ (32)

Of note also is the amplifier gain G in this case:

=

2

20

V

C

in

pkout

F

F

P

VCG

ω(33)

Although it may first appear that gain is increasing withfrequency, it should be remembered that inP is itself a

function of frequency. If a simple resistor/capacitor modelof the input is used, this dependence is inverse with thesquare of the frequency. Thus the gain of the optimally

sized amplifier will reduce only inversely proportional tothe frequency since the optimal device size in this case isreducing as frequency is increased.

Reviewing the results of (29), the following conclusions arereached. As before, tunings with low RMS to dc ratio onthe current waveform result in higher capacitance-limiteddrain efficiency. A low peak to dc ratio on the voltagewaveform improves the gain. Having a large tolerance tooutput capacitance (i.e. low FC) allows for higher drainefficiency, but at the cost of reduced gain due to theassociated increase in transistor size.

IV. CLASS E/F AMPLIFIERS

With comparison methods in hand to decide betweencandidate tunings, the discussion turns toward findingthese candidates. Until now, only two strong-switchingharmonic tuning strategies suitable for use with largeoutput capacitance have been introduced, class E and the“even harmonic resonant” class-E variant [26]. It wouldnot be unreasonable to suspect that other tunings havingsuperior characteristics may exist. From the standpoint ofthe FI and FV waveform conditions, the class-F waveformsare much better than class E, but have the drawbacks ofbeing unrealizable in the case of strong switching. Anobvious first line of inquiry might attempt to achieve thebenefits of class F (or inverse F) tuning by constructing ahybrid tuning taking on characteristics of both E and F.The new class E/F amplifier family, as its name suggests,is a method of achieving a hybrid tuning between class Eand class F-1, class F-1 being a natural choice than for aZVS amplifier hybrid since the ideal waveforms of thisclass are ZVS unlike class F which presents voltagewaveform discontinuities at the switching events in theideal (all harmonics tuned) case.

Although one might suggest many different ideas forcomposing such a hybrid, the method proposed here is afrequency domain hybrid, choosing at each overtone totune either according to the class F-1 or class E method. Inother words, some selection of even harmonics may beopen-circuited, some selection of odd harmonics may beshort-circuited, and the remaining harmonics are presentedwith a fixed capacitance. As in the class-E case, thefundamental frequency load resistance RL and inductivereactance XL are adjusted in order to achieve ZVSswitching conditions. This leaves one degree of freedomthat might be used to set the slope of the voltage during theswitch turn-on to zero, allowing for class-E switchingconditions2. If the number of class F-1 tuned harmonics isfinite, the amplifier is be realizable using the circuit in Fig.6, although this is not necessarily the most desirableimplementation.

2 Class E/F tunings are not limited to class-E switching conditions, andperformance advantages may be found using a tuning with non-zero voltageslope at turn-on due to reduced peak voltage and larger capacitance tolerance.

9

This technique may be used to produce many differentamplifier tunings according to which overtones have beentuned as class F-1, and so a naming scheme is required todifferentiate between them. The names used herein are ofthe form Class E/Fn1,n2,n3,…, where the numerical subscriptsindicate the numbers of the class F-1 tuned harmonics.Table 1 shows the impedance specifications of severalrepresentative E/F amplifiers.

f0 2f0 3f0 4f0 5f0

E RL

XLCS CS CS CS CS

E/F3 RL

XLCS CS short CS CS

E/F2,3 RL

XLCS open short CS CS

E/F2,4 RL

XLCS open CS open CS

E/F3,4 RL

XLCS CS short open CS

F-1RL open short open short

Table 1. Sample class-E/F harmonic tuning specifications infrequency domain.

A. Waveforms and Tuning Requirements

Recently, a general analytic method for determining boththe exact waveforms and the fundamental frequency tuningof RL and XL to achieve ZVS conditions for any circuit ofthe form shown in Fig. 6 has been developed [27].Although the details of this technique are beyond the scopeof this paper, the results summarized in the followingsection may be found using this method.

Some sample E/F waveforms are depicted in Fig. 8. Thewaveforms contain features both of class-E and class-F-1

amplifiers. Like class E, the voltage waveform switches atzero voltage and zero voltage slope, while the currentwaveform has a discontinuity at the switch turn-off, as isrequired in a ZVS amplifier [28]. The waveforms forsmall numbers of harmonics tuned tend to resemble classE, and as the number of tuned harmonics is increased, theresemblance to class F-1 increases. Low order harmonicshave the most effect, and even harmonics tend to primarilyaffect the current waveform, whereas odd harmonics tendto have the most effect on the voltage waveform.

(a) (b)

(c) (d)

(e) (f)

Fig. 8. Class-E/F amplifier waveforms: (a) Class E/F2,(b) Class E/F3, (c) Class E/F2,3, (d) Class E/F2,4, (e) Class E/F2,3,4,(f) Class E/F3,5. Waveforms are normalized to dc voltage andcurrent. The time is normalized to the switching period.

As can be seen from the sample waveforms, the voltagepeak relative to the dc voltage is generally lower than inclass E, and the current waveform tends to resemble asquare wave, lowering the RMS to dc ratio. These effectsare quantified in Table 2, wherein the waveform figures ofmerit for various E/F tunings are shown.

FV FI FC

E 3.56 1.54 3.14E/F2 3.67 1.48 1.13E/F3 3.14 1.52 3.14E/F2,3 3.13 1.47 2.31E/F2,4 3.43 1.46 0.97

E/F2,3,4 3.08 1.45 1.18E/F3,5 3.20 1.51 3.14

E/F2,3,4,5 3.20 1.45 2.11F-1 3.14 1.41 N/A

Table 2. Waveform properties for sample class E/F amplifiers.Smaller numbers indicate better performance.

For the tunings selected, only one of the amplifiers listedperforms worse in any category than class E. Generallyspeaking, tuning the second harmonic tends to increase thepeak voltage, reduce the RMS current, and greatly increasethe tolerance to output capacitance. Tuning the thirdharmonic tends to reduce the peak voltage, has little effecton the RMS current, and has a varying effect on thecapacitance tolerance. Tuning the fourth harmonic has

10

varying effectiveness depending on which other harmonicshave been tuned. The fifth harmonic, interestingly, usuallyhas detrimental effects on the performance, e.g. E/F2,3,4

shows better performance than E/F2,3,4,5 under mostmeasures. This would indicate that, contrary to the case ofclass F and class F-1 amplifiers, tuning of additionalharmonics using the E/F method does not necessarily resultin better performance.

22IV FF

see (16)IV FF2

see (25)CI FF 2

see (29)CV FF 2

see (29)

E 30.03 10.96 7.44 4.03E/F2 29.57 10.87 2.49 11.9E/F3 22.76 9.54 7.24 3.14

E/F2,3 21.25 9.22 5.02 4.24E/F2,4 25.10 10.02 2.07 12.2E/F2,3,4 20.08 8.96 2.50 8.00E/F3,5 22.39 9.67 7.18 3.26

E/F2,3,4,5 21.68 9.31 4.47 4.85F-1 19.74 8.88 N/A N/A

Table 3. Loss factors for selected E/F tunings. The first threecolumns represent a factor in the drain loss for three differentcases and the fourth column represents a factor in the drive lossof a capacitance-limited amplifier.

Efficiency and gain factors derived previously for variousE/F tunings are shown in Table 3. The first column showsthe waveform factor for the size-limited drain efficiency(16). As can be seen, several E/F tunings such as E/F2,3,4

reduce the drain loss to around 67% that of class E. Thisimprovement puts several class-E/F tunings into the sameperformance range as ideal class F-1 and would serve toreduce the heat-sinking requirements by one third. Thesecond column shows the waveform factor for thegain-limited PAE as in eq. (25), and tells a similar story,although the improvements are more modest.

The application where E/F promises to have the mostusefulness is the capacitance-limited drain efficiency caseas shown of the third column. As can be seen, the E/Famplifiers can show extremely good performance underthese conditions, in some cases reducing the expected drainloss to less than 30% that of class-E. This is accomplishedby increasing the transistor size, as class E/F tunings oftenshow greatly increased tolerance to output capacitance, asindicated by their very low values of FC. This additionalefficiency comes at the price of gain, as shown in thefourth column, but in many cases the intrinsic device gainat the frequency of interest is high but large outputcapacitance limits the device size in class E amplifiers.Even if the designer does not wish to make full use of theavailable gain/efficiency trade-off, he is free to choose anytransistor size having an output capacitance smaller thanthe capacitance CS with the remainder being made up bydiscrete capacitors.

V. PUSH/PULL CLASS E/F AND E/FODD AMPLIFIERS

One problem which arises in the implementation ofclass E/F amplifiers is the difficulty of tuning the relativelylarge numbers of harmonics in a way that is bothreasonably simple and low-loss. Since each additionalresonance added to the circuit introduces loss, it isdesirable to reduce the stored energy in the resonators, i.e.make their loaded Qs low. Unfortunately, this causes theeffect of the tuning circuit to be broad in the frequencydomain and to spill over into adjacent harmonics as well,usually with adverse effects. For instance, if a series LCresonator is used in a class E/F3 tuning to tune a shortcircuit at the 3rd harmonic, this resonator will present acapacitance at the second harmonic, reducing itsimpedance. This causes the waveforms to degrade withregard to all three waveform figures of merit, particularlywith regard to FC. The designer is thus forced to eitherutilize a very high loaded Q resonant circuit ─ increasingthe loss of this component ─ or to introduce additionalresonances into the circuit ─ again increasing the loss.

There is, however, a more elegant way to separate theeffects of the even and odd harmonic frequencies. Byutilizing a symmetric push/pull switching amplifier circuit,the differing symmetries of the even and odd harmonics inthe switching waveforms may be beneficially employed.

Consider, for instance the circuit depicted in Fig. 9. Thecircuit employs two switches, each with 50% duty cycle butoperated such that when one switch is conducting the otheris open. Due to the symmetry of the circuit, the waveformsof each switch are identical except for a time delaydifference of a half cycle between them. Connectedbetween the switches is a differential T-section loadcomposed of a differential impedance ZD connectedbetween the two drains, and a common-mode conductanceYC connected between the center of the differentialimpedance and ground.

(b)

(a)

(c)

Fig. 9. Push/pull amplifier with a T network load: (a) circuittopology, (b) tuning effect at odd harmonics, (c) tuning effect ateven harmonics.

11

The effective impedance seen from each drain at eachharmonic may be calculated. Due to the time-delaysymmetry of the waveforms, the odd harmonic voltagecomponents of each switch must be equal in amplitude butopposite in phase. Consequently, a virtual ground developsat the line of symmetry at the center of the differentialimpedance, shorting across conductance YC so each switchsees an impedance of 2DZ . At the even harmonics,

however, the harmonic voltage components are equal inamplitude and phase. Thus, the line of symmetry becomesa virtual open-circuit so the switches must share theconductance YC, each seeing an impedance of

CD YZ /22 + .

Using this principle, an E/F3 amplifier might beconstructed by placing the third harmonic short circuit as adifferential load, shorting the third harmonic using alow-Q resonator without adversely affecting theimpedances of any even harmonics. Similar strategies maybe used to selectively tune the impedances of evenharmonics.

While this technique is itself useful for the efficientconstruction of the E/F amplifiers discussed in the previoussection, it also opens up the very interesting possibility ofshort circuiting all odd harmonics by placing a differentialshort circuit between the two switches. To avoid alsoshort-circuiting the fundamental, a bandstop filter such asa parallel LC tank may be used to provide a differentialshort-circuit at all frequencies other than the fundamental.This technique would have the promise to yield anE/F3,5,7,9,etc. tuning, denoted hereafter as E/Fodd.

Fig. 10. E/Fodd circuit implementation using a push/pullamplifier and a bandstop filter.

This technique might conceivably be improved by furthertuning several even harmonics, generating an E/Fx,odd

amplifier where x is a set of tuned even harmonics. Amethod by which a number of even harmonics may beopen-circuited is shown in Fig. 11, wherein the E/Fodd

circuit of Fig. 10 has been augmented with additionalresonators in parallel with each switch. Each resonatormay be treated analytically as a bandpass filter in serieswith a capacitance –CS. The filter connects this negativecapacitance in parallel with the switch parallel capacitanceat those even harmonics to be tuned, canceling thiscapacitance at these frequencies.

Fig. 11. E/Fx,odd conceptual circuit implementation. Additionalresonant circuits in parallel with each switch resonate with theswitch capacitance at selected even harmonics.

Unlike the class E/F amplifiers with finite numbers ofharmonics tuned, the waveforms of E/Fx,odd amplifiers arederived with relative ease. In the E/Fx,odd amplifierdepicted in Fig. 11, the bandstop filter located between thetwo switches forces the voltage differential, 12 VV − to be a

sinusoid with a frequency equal to the fundamentalfrequency f0. Letting the amplitude and phase of thesinusoid be denoted VD and φ respectively:

)sin(12 φθ +⋅=− DVvv (34)

Since one of the switches is always on and therefore haseffectively zero voltage across it, the differential voltagemay be used to calculate the voltages V1 and V2. Assumingthe leftmost switch is closed for πθ <<0 :

<<+⋅−<<

=πθπφθ

πθ2)sin(

001

DVv (35)

<<<<+⋅

=πθπ

πθφθ20

0)sin(2

DVv (36)

Assuming a ZVS tuning is to be found, these voltagewaveforms must be continuous at the switching turn-onevents. As can be seen, the only non-trivial solution is forφ to be zero, indicating that the properly-tuned voltagewaveform is half-sinusoidal. As each switch is connectedto the dc supply through an inductor, the dc value of eachswitch voltage waveform must equal the dc supply voltageVDC. Since the peak to average ratio of a half-sinusoid is π,the voltages are:

<<⋅−<<

=πθπθπ

πθ2)sin(

001

DCVv (37)

<<<<⋅

=πθπ

πθθπ20

0)sin(2

DCVv (38)

Now that the voltages across the capacitances CS1 and CS2,each with capacitance CS, are known, their currents ICS1

and ICS2 may be calculated3:

3 Although the case presented here assumes a linear capacitance, the case of anonlinear capacitance is also readily solved [18].

12

<<−<<

=πθπθπω

πθ2)cos(

00

01

DCSCS VC

i (39)

<<<<

=πθπ

πθθπω20

0)cos(02

DCSCS

VCi (40)

The frequency dependence may be removed by expressingthe currents in terms of the capacitances’ fundamentalfrequency impedance ZC:

( )

<<⋅−<<

=πθπθπ

πθ2)cos(

001

CDCCS ZV

i (41)

( )

<<<<⋅

=πθπ

πθθπ20

0)cos(2

CDCCS

ZVi (42)

The even-harmonic resonator currents IT1 and IT2 may becalculated using the known resonator impedance. TheFourier decomposition of the switch voltage waveformsare:

{ }

−−−⋅= ∑

∈ K,6,4,221 )cos(

1

2)sin(

21

kDC k

kVv θθπ

(43)

{ }

−−+⋅= ∑

∈ K,6,4,222 )cos(

1

2)sin(

21

kDC k

kVv θθπ

(44)

The admittance YT(k) of the tuning network at the kth

harmonic is:

CT ZjkkY −=)( (45)

Using equations (39), (40), and (41), the resonator currentsIT1 and IT2 may be calculated. Denoting the set of tunedeven harmonic numbers as T:

∑∈

−⋅−==

TkC

DCTT k

k

k

Z

Vii )sin(

1

2221 θ (46)

Since, at all times, at least one switch is non-conductingand the chokes only conduct dc current IDC, all currentsexcept for the conducting switch are known. Therefore,current through the conducting switch may be determinedby Kirchhoff’s current law (KCL):

<<

<<

−+−

= ∑∈

πθπ

πθθθπ

20

0)sin(1

4)cos(2

21 TkC

DC

C

DCDC

Sk

k

k

Z

V

Z

VI

i (47)

<<

−++

<<= ∑

∈

πθπθθππθ2)sin(

1

4)cos(2

00

22

TkC

DC

C

DCDC

S kk

k

Z

V

Z

VIi (48)

With the switching waveforms in hand, the remaining taskis to determine the fundamental-frequency load impedance.The load current iLOAD is readily calculated using KCL:

<<−

⋅−+

<<−

⋅++−=

∑

∑

∈

∈

πθπθθπ

πθθθπ

2)sin(1

2)cos(

0)sin(1

2)cos(

2

2

TkC

DC

C

DCDC

TkC

DC

C

DCDC

LOAD

k

k

Z

V

Z

VI

k

k

Z

V

Z

VI

i (49)

With the load current and load voltage known, theirfundamental frequency Fourier components VLOAD andILOAD may be found:

DCLOAD VjV πωω == )( 0 (50)

( ) DCTkC

DC

C

DCLOAD Ij

k

k

Z

V

Z

VI

πππωω 4

1

8)(

22

2

0 +−

−== ∑∈

(51)

Computing the fundamental frequency differential loadconductance as the ratio of this voltage and current yields:

( )

−⋅−

⋅−

= ∑

∈TkCDC

DCLOAD

k

k

Zj

V

IY

22

2

221

811

14

ππ(52)

From this expression, it is apparent that the required loadfor ZVS operation is a resistance in parallel with anappropriately sized inductive susceptence, the size of whichis determined by the harmonics tuned and the switchparallel capacitance.

This load conductance formula suggests a degree offreedom in the tuning. Since the conductance has nodependence on the capacitor CS and the susceptance is afunction only of this capacitance (and the tuning), theamplifier will operate in ZVS mode without retuning forany value of the load conductance and without the voltageson the switch or on the load changing. The currentwaveforms, however, do change. Expressing (47) in termsof the load resistance and the dc voltage yields:

<<

<<

−−−= ∑

∈πθπ

πθθθππ

20

0)sin(1

4)cos(

2 2

2

1 TkC

DC

L

DC

Sk

k

k

Z

V

R

Vi (53)

This expression indicates that amplitude of the squarewave component is a function only of the resistance,increasing as the resistance is decreased. The “ripple”component, consisting of the resonator and capacitorcurrents, is independent of the load resistance, and iscompletely determined by the capacitance CS and theharmonics tuned. This effect is depicted in Fig. 12,showing class E/Fodd amplifier waveforms with varyingload resistance.

13

Fig. 12. E/Fodd waveforms for various values of load resistanceRL keeping switch parallel capacitance CS constant.

This load invariance may be a useful in many applications,but even for systems utilizing a fixed load this propertymay be applied. By keeping the load resistance constantand varying CS an E/Fx,odd tuning for a given output powerand dc voltage may be found for any value of thecapacitance CS provided that the susceptance of thefundamental frequency differential load is appropriatelytuned. The current waveform again changes according to(53), in this case varying the amplitude of the ripplecomponent as the value of the switch parallel capacitanceis adjusted. If the capacitance is zero, the current is asquare wave4 and increasing capacitance results in higherpeak and RMS currents. This effect is shown in Fig. 13.

Fig. 13. E/Fodd normalized switching waveforms for variousvalues of switch parallel capacitance.

There are several conclusions to be drawn from this. First,it is clear that the RMS current increases as thecapacitance is increased. Since, unlike class E whereinchoosing too small of a value for CS results in negativeswitch voltages – especially undesirable in FET deviceswith parasitic drain-bulk diodes – the E/Fx,odd circuitwaveforms improve as the capacitance is decreased. Thusunlike the class-E case wherein discrete capacitance isoften added parallel to the switch, it would be foolish to doso in the E/Fx,odd case.

This is not to say that the capacitance will necessarily besmall. Although the current waveforms improve withdecreased capacitance, the on-resistance improves withtransistor size. The tunings for different output

4 The zero-capacitance case is actually the well-known current mode class-Dinverter [6]. In a sense, E/Fodd is an output capacitance correction techniquefor current-mode class-D circuits.

capacitances have different values of FI and FC, and thusdifferent performances. It is therefore necessary to indicatethe size of capacitance being used in the amplifier whenspecifying the waveforms. Herein the waveforms will bespecified by their FC figure of merit relative to that ofclass E. For instance, a “2E” tuning would have an FC halfthat of class E. Physically, this corresponds to tolerancefor twice the capacitance of a class E amplifier operating atthe same output power from the same dc voltage.

(a) (b)

(c) (d)

(e) (f)

Fig. 14. Class-E/Fodd amplifier voltage (black) and current(grey) waveforms: (a) class E/Fodd “E” size device, (b) classE/Fodd “2E” size device, (c) class E/F2,odd “E” size device, (d)class E/F2,odd “2E” size device, (e) class E/F4,odd “E” size device,(f) class E/F2,4,odd “2E” size device. Waveforms are normalized todc voltage and current.

Waveforms for selected E/Fx,odd amplifiers are shown inFig. 14. For each of these tunings, the voltage waveform isa half-sinusoid. The current waveforms depend on theeven harmonics tuned and the switch parallel capacitance.Using the basic E/Fodd tuning results in a nearly trapezoidalcurrent waveform, and open-circuiting additional evenharmonics has the effect of causing the current waveformto more closely approximate a square wave, even for verylarge values of the output capacitance. In this way, theeven harmonic tuning is helpful for allowing even largertransistor sizes while keeping reasonable RMS currents.

14

FV FI FC

E 3.56 1.54 3.14E/Fodd (E) 3.14 1.50 3.14

E/Fodd (2E) 3.14 1.73 1.57E/F2,odd (E) 3.14 1.44 3.14E/F2,odd (2E) 3.14 1.51 1.57E/F2,4,odd (E) 3.14 1.43 3.14

E/F2,4,odd (2E) 3.14 1.47 1.57E/F2,4,odd (3E) 3.14 1.54 1.05E/F2,4,6 (2E) 3.14 1.45 1.57E/F2,4,6 (3E) 3.14 1.50 1.05E/F2,4,6 (4E) 3.14 1.57 0.79

F-1 3.14 1.41 N/A

Table 4. Waveform figures of merit for various E/Fx,odd tunings.

Waveform figures of merit for selected E/Fx,odd amplifiersare presented in Table 4. The voltage waveform is in allcases equal to that of class F-1, and the RMS currents inmany cases are nearly ideal. As in the case of thesingle-ended E/F amplifiers, the biggest improvement is inthe capacitance tolerance factor FC which may bedrastically reduced in many cases.

22IV FF IV FF2

CI FF 2 2VC FF

E 30.03 10.96 7.44 0.248E/Fodd (E/2) 20.36 9.02 12.96 0.637E/Fodd (E) 22.21 9.42 7.07 0.318

E/Fodd (2E) 29.61 10.88 4.71 0.159E/F2,odd (E) 20.43 9.04 6.50 0.318E/F2,odd (2E) 22.50 9.48 3.58 0.159E/F2,4,odd (E) 20.14 8.98 6.41 0.318

E/F2,4,odd (2E) 21.36 9.24 3.40 0.159E/F2,4,odd (3E) 23.38 9.67 2.48 0.106E/F2,4,6 (2E) 20.89 9.14 3.32 0.159E/F2,4,6 (3E) 22.33 9.45 2.37 0.106E/F2,4,6 (4E) 24.34 9.87 1.94 0.080

F-1 19.74 8.88 N/A N/A

Table 5. Efficiency and gain factors for various E/Fx,odd tunings.

Efficiency and gain factors for various E/Fx,odd tunings arepresented in Table 5. These tunings may excel in eachperformance category. Where transistor size is limited bycost, the low FV and FI values for small capacitance tuningsallow E/Fodd to approach the performance of class F-1

utilizing a circuit with only one resonator. In thegain-limited case, the lower peak voltage and the reducedRMS current will similarly improve performance. Thecapacitance limited case, however, is again the mostpromising area for performance enhancement, with drainloss less than 30% of class E in some cases.

VI. CONCLUSION

A new family of ZVS harmonic-tuned switching amplifiershas been introduced, each member of which may be

constructed using a straightforward circuit incorporatingthe transistor output capacitance as a circuit element.These E/F tunings allow strong-switching operation as inclass E, but show a greater tolerance for transistor outputcapacitance and present waveforms approaching the moredesirable class-F-1. The family exhibits a tradeoff betweencircuit complexity and performance. In addition to single-ended approaches similar to class-E, push/pull E/Fx,odd

approaches taking advantage of circuit symmetries promiseto greatly improve performance of class-E style amplifierswith little added circuit complexity.

ACKNOWLEDGMENT

The authors would like to thank the Jet PropulsionLaboratory, the Lee Center for Advanced Networking, theNational Science Foundation, the Army Research Office,and Xerox Corporation for their support. We would alsolike to thank K. Potter and J. Davis for their invaluableadvice and assistance as well as B. Kim, M. Morgan, H.Hashemi, H. Wu and D. Ham for the helpful discussions.

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15

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