The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 1

The Belle SVD TriggerTom Ziegler

on behalf of the Belle SVD group

Vertex 2002

Kailua-Kona, Hawaii, 4-8th nov 2002

The SVD 2.0 Update The Front-End Readout

Electronics Level 0 & 1 Trigger Level 1.5 Trigger Summary

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 2

The Belle detector

SVD 1.4

SVD 2.0

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 3

Update SVD 1.4 => SVD 2.0

Increase radiation hardness of the front-end readout chip:

0.8m => 0.35m CMOS process

Stable > 10 MRad!

Better polar angle coverage:

23°-139° => 17°-150°

Closer to beam pipe (3->2.1cm)

increasing peak luminosity:

8.256 1033 cm-2 s-1 (28-oct-2002)

Include trigger capability in front-end chip

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 4

The Readout Electronics

RepeaterSystem

FADC

PCI and DAQ

TriggerL0&L1

TriggerL1.5

DSSD

Hybrid,VA1TA

4 layers (6, 12, 18, 18) 54 ladders, 108 halfladders

(108*512)*2 = 110.592 channels

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 5

Each chip reads out 128 DSSD channels.Trigger capability is included in the ASIC.

FE readout chips: VA1TA, IDE AS

Front-end Electronics

slowShaper

S/H

Mu

ltiple

xer

PA

Hold Analog out

128x

fastShaper

Threshold

Discr.

128x

Trigger out1x !

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 6

The Readout Electronics

RepeaterSystem

FADC

PCI and DAQ

TriggerL0&L1

TriggerL1.5

DSSD

Hybrid,VA1TA

4 layers (6, 12, 18, 18) 54 ladders, 108 half ladders

(108*512)*2 = 110.592 channels

TA signal,granularity of 128 strips

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 7

ToF trigger

CDC trigger

SVD TA

CDC

SVD-CDCmatching

Global L1

Global L0

Level 0 and Level 1 Trigger

We take advantage of the trigger capabilities of the front-end readout electronics (VA1TA).

Resolution not very good, but very fast decision possible( <600ns for L0 / <2.5s for L1).

Other SubS.

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 8

The Readout Electronics

RepeaterSystem

FADC

PCI and DAQ

TriggerL0&L1

TriggerL1.5

DSSD

Hybrid,VA1TA

4 layers (6, 12, 18, 18) 54 ladders, 108 half ladders

(108*512)*2 = 110.592 channels

VA analog signals,full granularity

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 9

The Level 1.5 r-z-Trigger

After 25 s all information are available from the FADC-system and can be used for a trigger 1.5 decision with a very good tracking resolution!

Mainly reject beam gasevents that do not comefrom the primary vertex.

Generate MC eventsand record ‘trigger terms’for each of 18 wedges.

3.2cm

wed

ge

IP

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 10

The Trigger Logic

Resolution which probably will be used:Layer 1/4: merge 32 strips to 16 segments on each waferLayer 2/3: merge 16 strips to 32 segments on each wafer

We see all the gapsbetween wafers.

Single track efficiency < 80%!=> 4/4 too simplisticGoal: at least 90%

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 11

Improve efficiency

Consider 3/4 terms (one layer missing)

=> 98% efficient, but not very goodrejection of background events!

Try 3/4 terms and demand 1. layer=> Overall efficiency 95% in good region(but more than 20,000 trigger terms).

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 12

Some statistical tricks

Some of the logic terms are contained in others, e.g.:20 22 20 2020 21 20 2020 22 19 2020 22 20 18

Reduce number of terms by 25%.

Number of hits in each trigger term in simulation, e.g.:

15 17 15 15 1634x15 16 15 15 1034x15 17 14 15 341x15 17 15 13 11x

Skip all trigger terms with few hits!=> skip terms without losing much efficiency

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 13

4/4 terms 79.8% 21449 terms3/4 terms 98.0% 23867 terms3/4 terms (with inner layer) 95.3% 23867 termsstrip terms contained in others 95.3% 13474 termsstrip terms with #hits <50 95.3% 10105 termsstrip terms with #hits <100 95.1% 8272 termsstrip terms with #hits <500 93.1% 5452 termsstrip terms with #hits <750 90.5% 2497 terms

Implementation of trigger logicin Xilinx FPGAs on a 9U VME board.

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0 500 1000 1500 2000 2500

cut on number of hits

%

single track efficiency

number of trigger terms

Implementation of Trigger Logic

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 14

Further improvement

FADCDOCK

TDM

T1.5data

Level 1.5 trigger decision

CDC

ToF

Up to 128 bits

Up to 64 bits

T1.5BB

1 bit for each of

the 18 sectors

Start of data transfer

TTM

SEQ

GDL

monitoring

monitoring

FECdatadata

Introduce Trigger 1.5 Buffer Board

Merging of SVDwith CDC and ToFinformation!

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 15

The Trigger System

The different trigger levels will be:

L0 0.6 s SVD, ToF, CDC < 10kHz

L1 2.5 s SVD, CDC, ECL < 1kHz

L1.5 25 s SVD, (ToF, CDC)

DAQ read-out

The SVD will play a central role in the Belle trigger system!

The Belle SVD Trigger Tom Ziegler Vertex 2002 Kailua-Kona, Hawaii, 4-8th nov 2002 16

Summary

Upgrade to SVD 2.0 allows substantial improvements in the trigger capabilities for the Belle detector!

The implementation of the system with Xilinx FPGAs and overall setup is very flexible and there is still room for improvement to deal with the increasing luminosities of the KEKB accelerator.

The system will be tested the next months in an overall system integration test with the rest of the SVD readout system and is ready for installation in the next shutdown.