The 1553 Advanced Communication Engine (1553-ACE)

Steven N. Friedman ILC Data Device Corporation

P D C )

ABSTRACT

The next generation 1553 Terminals will address the concerns of reducing the size, power, cost, and adding features required to off-load the system designer. The 1553-ACE series programmable terminal is the smallest fully integrated MIL- STD-1 553AiB Notice 2, STANAG 3838 and MIL-STD-1760A dual redundant Remote Terminal (RT), Bus Controller (BC), and Bus Monitor (MT). The BUS-61580 ACE Terminal was designed to support a dual redundant RT/BC/MT protocol, including special transceivers housed in a ceramic package less than two square inches. This paper will discuss the various features incorporated, especially the programmable options which make this series terminal so flexible.

The ACE series has an advanced set of registers, Internal 4K words of shared RAM, dual encoderldecoders and the three- state buffers for address and data 1iO’s in one monolithic. It has selective IiO features, such as buffered DMA, or a shared RAM interface, with or without zero wait states to support a variety of microprocessors. Additional programmable features incorporated are RT circular data stacks programmed by individual subaddress, internal RAM command illegalization, plus advanced BCiMT options for bus snooping or for selective monitoring.

This paper will highlight the electrical, mechanical, and special competitive features of the 1553 ACE-series. The military screening and mechanical specifications and other product options are covered.

INTRODUCTION

The terminal designer of today has many MIL-STD- 1553 components to select from, but none that offers low risk, power,

Bawd o n a pre\entation at NAECON ‘92. oxx5 X9X53Y3 ’ 1993 l t E E

cost and reduces the terminal size, to under two square inches with transceivers, as the 1553-ACE (BUS-61580) series. The cornerstone element of this new series of terminal is a custom monolithic HCMOS digital protocol chip known as J ’ . This monolithic along with a variety of monolithic transceivers supports various applications such as MIL-STD- 1760A, and multi-protocol RTIBCIMT for MIL-STD-1 553A/B, Notice 2, STANAG 3838 and others. The 1553-ACE products are being offered in 70-pin 1.9 x 1 .0 inch plug-in, flat pkg, and J-lead ceramic packages. Since this is a multi-chip module (MCM), DDC plans to offer these as co-fired ceramic packages by the end of the year, in order to reduce the package height by the elimination of the separate internal substrate. In addition, with respect to DDC’s previous generation of AIM-HY and AIM- HY’er products, the ACE series provides complete software compatibility plus a great many enhancements. Please reference Fig. I , BUS-61580 Block Diagram.

The 1553 ACE-series includes 4K X 16 words of RAM within the J’ for additional reliability and subsystem support. The internal buffered 4K of RAM may be expanded to up to 64K words of external RAM. There will be 78-pin product available with the additional RAM within the package. This shared RAM besides supporting the subsystem with data transfers also provides programmable illegalization of Mode Commandslword count, TlR bit, Subaddress, Broadcastiown address for a combined possibility of 4096 combinations. Thus, saving the systems designer the need for any additional external components for implementing illegalization.

A choice of RT only (BUS-65 170) or RTiBCiMT (BUS- 61 580) configurations are available in the same 70-pin package and have the same footprint of signals. This supports future system expansion or upgrade when the additional BCiMT features become necessary. The 1553-ACE series software would be the only update necessary, since the existing PC board layout would be alright for either terminal.

4H IEEE AES System3 Muguzine, Junuary 1993

The ACE series advanced features make a real difference, especially since they are easily implemented through registers provided. The RT mode of operation supports 1553AiBi McAIR; optional broadcast separation for 1553B Notice 2 compliance, choice of single message, double buffering, or circular buffer (128 to 8192 words) on a subaddress basis, programmable illegalization, and programmable Busy, on a subaddress basis. Message time tagging, additional interrupts, and two special test mode registers are just a few more programmable features.

to 5 12 message frames, programmable intermessage gaps and frame times, automatic retries, frame auto-repeat, and programmable RT Status Word masking on a message basis. The 16-bit Time Tag Word will reflect the current contents of the internal Time Tag Register. This readiwritable register, which operates in all three modes, has programmable resolution from 2 to 64 microsecondsiLSB. In addition, the Time Tag register may be clocked from an external source.

The MT architecture will support three different monitor modes: 1) A word monitor; 2) A selective message monitor, with selection based on terminal address, TIR bit, subaddress; 3) A combined RT/Selective monitor mode. The combined RT/ Selective Monitor maintains three stack areas in the ACE-series address space: an RT Command stack, a Monitor Command

In the BC mode of operation, the ACE series supports up

stack, and a Monitor Data stack. Pointers for each stack are in fixed locations such that the subsystem can keep track of bus activity easily.

The BUS-65 170i61580 have been provided with an on-line self test and a off-line self test. The on-line test allows the terminal to wrap around all messages in the BC and RT mode, for real time word validity checking. The off-line supports testing in the BC mode, for complete exercise of the parallel and serial data paths, encoderidecoder, and a major portion of the BC protocol and memory management logic. The results of these tests are reported to the message's Block Status Word and also through an interrupt if enabled.

host processor interfacing. It offers a choice of 16-bit buffered and transparent modes, 8-bit buffered, 8-bit or 16-bit zero wait state, and 16-bit direct memory access (DMA). Other options include standard 16 MHz or factory 12 MHz clock input and an optional single-ended decoder inputs to support MIL-STD- 1773 fiber optic applications.

The ultimate flexibility of the ACE-series is its support of

DISCUSSION

The J' monolithic was developed with a great deal of flexibility for interfacing to a host processor and optional memory. Please refer to Fig. 2, 16-Bit Buffered Mode. This

IEEE AES Sy.strms Muguzine. Junuaiy 199.3 49

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Notes. I . CPU address latch signal provided byproc-

essors with multiplexed addressldata buses. 2 . I fPOLSEL = “1” RDIWR is high to read.

Low to write. If P r o S E L X “0” RDIWR is low to read. High to write.

3 , Zero-Wait should be strapped to Logic “ I ” for nm-zero wait. Interface and to logic

4 . CPU acknowledge processor input only for “0” for zero wait interface.

non-zero wait type of interface.

Fig. 2. 16-Bit Buffered Mode

figure shows the 16 control signals for supporting the processor/ memory interface. The designed interface options reduce the glue logic needed to support 8, 16, and 32-bit processor buses. In addition, features are included that support interfacing processors that do not have a “wait state” type handshake acknowledgement. The ACE-series will provide a reliable

interface to an external dual port RAM or shared RAM. This type of interface minimizes the portion of the available processor bandwidth required to access the 1553 RAM.

The 16-bit buffered mode (Figure 2) is the most common configuration used. The internal address and data buffers provide the isolation required for most processor’s address and

IEEE AES Sjstems Magazine, January 1993 50

data buses and the corresponding internal memory buses. Future MCM versions of the ACE-series products will offer larger amounts of internal RAM for supporting special applications. In order to support the Intel i960 series and Motorola 680x0 series microprocessors, Figure 2 shows a POLARITY-SEL input control signal. This POLARITY-SEL controls the logic sense of the RD/WR* control input so that its low for Motorola and high for the Intel processor.

The processor interface also has provisions for supporting ZERO-WAIT* state processors such as the Analog Devices’s ADSP2101 DSP chip. By strapping the ZERO-WAIT:‘: input to a logic “ 1 ,” will assert its READYD” output only after it has latched WRITE data internally or has presented READ data on D15-DO. If the ZERO-WAIT* is strapped to logic “0,” the interface will support the systems that do not have acknowledge type handshakes. In this type of configuration, the processor can clear its strobe output before the access to the ACE-series internal RAM or register has been completed.

The 16-bit buffered mode can be operated in a transparent mode should there be host supported RAM external from the terminal. This would be configured with up to 64K words of RAM and external buffers for the address and data lines required to isolate the processors. The ACE-series controls the RAM memory contention via the READYD”. I t is also possible to use dual port RAM, rather then conventional static RAM for applications requiring faster access times. In this mode the only concern would be the simultaneous access to the same memory address. This occurrence is rare, but if and when it does occur, the delay is limited to approximately 250 ns.

There will be some applications that require larger system RAM and therefore a Direct Memory Access (DMA) mode will be necessary. The ACE-series can be set-up so that the processor controls the address and data bus arbitration, by controlling the data grant (DTGRT”) return to the J’ while monitoring the data request (DTREQ*) and data acknowledge (DTACK”) signals. The host processor can support RAM above 64K words, with page registers for the upper address bits (above A15) when J’ accesses the RAM (during the time that DTACK* is asserted low).

There are many systems that arc still planning to use %bit processors such as the Intel 8051 series, to keep cost and complexity to a minimum. The ACE-series supports an %bit buffered mode because of embedded 8-bit registers in the J’ . The 8-bit I10 just like the 16-bit I10 can support ZERO-WAIT” state microcontrollers like the Intel 805 1 . that do not have an acknowledge handshake input. The programmable inputs POLARITY-SEL and TRIGGER-SEL support the different byte ordering conventions and “AO” logic sense utilized by different 8-bit processor families.

CONCLUSION

The next generation monolithics have been developed to support MIL-STD-1553AIB Notice 2, STANAG 3838 and MIL-STD- 1760A dual redundant Remote Terminal (RT), Bus Controller (BC), and Bus Monitor (MT). The ACE-series terminals concept evolved from an earlier LSI implementation know as the AIM-HY’er series. The new BUS-65170/61580 terminals, offers reduced power dissipation, while operating with + 5 VDC only, thanks to a new monolithic transceiver design. The new transceiver and J’ digital protocol monolithic have transformed the ACE-series into a co-fired MCM ceramic 70-pin package. At under 2 sq.in’s, the ACE-series terminal is the smallest and lowest cost fully integrated terminal available today.

The ACE-series terminal can support MIL-STD- 1750A computers, or standard microprocessors such as the 8080,8086, 68000 series, and the Intel i960,286,386,486 processors as well as microcontrollers such as the 805 1. It also has the flexibility to interface with external dual port RAM or shared system RAM with a minimum of glue logic. It is an achievement which offers the terminal designer software flexibility and low risk never before possible. It supports earlier designs with the AIM-HY’er series or can be expanded with the enhanced features by the additional register controls.

The BUS-65 17016 1580 terminals are produced in a certified MIL-STD- 1772 facility and therefore meets the requirements of MIL-H-38534 of MIL-STD-883. The terminals will operate over the full military temperature range of - 55 to + 12.5 C.

Steven N. Friedman, Data Bus Product Manager, joined DDC in 1979. He holds a BS in Electrical Engineering from N Y Institute of Technology and a MS in Management Engineering from Long Island University, C. W. Post College. In addition to overseeing DDC’s MIL-STD- 1553 products, Mr. Friedman has assumed applications responsibilities for DDC’s line of Solid-state Power Controllers (SSPCs).

IEEE AES Systems Magazine, Junuur) 1993