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Acknowledgement…..
This presentation has been summarized from
various books, papers, websites and
presentations on VLSI Design and its various
topics all over the world. I couldn’t itemwise
mention from where these large pull of hints and
work come. However, I’d like to thank all
professors and scientists who created such a
good work on this emerging field. Without those
efforts in this very emerging technology, these
notes and slides can’t be finished.
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Test Principal for Digital Circuits is
Universal…….
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Verification
• On Design
(functionality,
estimated speed)
• Pre-silicon
• One time
• By simulation,
emulation, formal
methods
• A Design Bug
• Makes all Fabricated
IC useless
• Less prone to occur
Detection/Testing
• On Device
(manufactured
hardware)
• Post-Silicon
• On all ICs, i.e. every
time IC is fabricated
• By Test Generation
and Test Application
• A fabrication defect
• May cause all ICs or
Some of the ICs
useless.
• More prone to occur
because of small
geometry
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What is Ideal Test?
• Ideal tests detect all defects produced in the manufacturing process.
• Ideal tests pass all functionally good devices.
• Very large numbers and varieties of possible defects need to be tested.
• Difficult to generate tests for some real defects.
• Defect-oriented testing is an open problem.
• Is it practical?
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Testing Philosophy
• Students-chips
• Course syllabus – specifications
• No one has infinite time
• Test paper – fault model
• If Failed,
• repeat the course - respin
• Interaction in class: verification
• Asking teachers the details in advance – DFT
• If too hard question paper: a student of pass category fails –student’s image at risk (manufacturer’s risk) – yield loss
• If too easy question paper: a student of fail category passes – teacher’s image at risk (consumer’s risk) – defect level or reject rate
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Test Plan
• Design House: Design is complete and checked
(verified)
• Fab vendor: How will you test it?
• Design house: I have checked it and …
• Fab vendor: OK. But, how would you test it?
• Design house: Why is that important?
• Complete the story…..
• None of the fab will manufacture your design if
you can not satisfy them with proper test plan.
• That is one reason for design-for testability,
test generation, Built-In-Self-Test etc.
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Test Development Vs
Manufacturing Test
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Cost Components of Testing
• Test Development Cost • Software process of test
• Test generation and fault simulation
• Test programming and debugging
• Test Application Cost • ATE Cost
• Test Center Operation Cost
• Depends on Test Time per IC
• DFT • Chip Area Overhead and Yield Reduction
• Performance Overhead
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What do we mean by
Effective Testing…..
• It means… now onwards all over efforts should be
for more and more effective testing….
It means……
• More fault coverage
• Less test cost
• Less test application time
• Less test power
• More yield
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Functional vs Structural testing
• For your hardware projects, the steps you follow
are:
• Specification
• Design
• Simulate (Verification – Functional Testing)
• Fabricate
• Testing (Structural Testing)
• Observation of each component and wire working fine
individually!, assumed that if it individual components
are fine and connections are right, the PCB will produce
intended functions correctly)
• Easy and Fast compared to structural
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Structural Testing
• Hardware components
• Defects in Hardware
• Its effect on output
• Complete list of all possible defects in given
circuits……
• The test which can prove the presence or absence
of the defect from given list
• Test set that can prove the presence or absence of
all possible defects from given list
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Functional Test
• Black Box Approach
Functional ATPG – generate complete set of tests for circuit input-output combinations
◦ 129 inputs, 65 outputs:
◦ 2129 = 680,564,733,841,876,926,926,749,214,863,536,422,912 patterns
◦ Using 1 GHz ATE, would take
2.15 x 1022 years
Structural Test
• White Box Approach Structural test:
◦ No redundant adder hardware, 64 bit slices
◦ Each with 27 faults (using fault equivalence)
◦ At most 64 x 27 = 1728 faults (tests)
◦ Takes 0.000001728 s on 1 GHz ATE
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Defects, Errors, Faults
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Defects, Errors, Faults…..
• Defects: A defect in an electrical system is the unintended difference between the implemented hardware and its intended design
• Process Defects:
• missing contact window, parasitic transistors, etc.
• Material Defect:
• bulk defects, material impurities etc
• Age Defects:
• Dielectric Breakdown, electromigration etc.
• Package Defects:
• contact degradation, seal leak etc.
• Errors
• A wrong output signal produced by a defective system is called an error.
• An error is an effect whose cause is some defect.
• Faults
• A representation of a defect at the abstracted level is called a fault.
• The fault is imperfection in function while the defect is imperfection in hardware.
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Defects modeled as Faults
• Failure mode is used in reference to the manifestation of a "defect" at the electrical level.
• Failure modes are modeled as faults at logic or behavioral level of abstraction.
• At the logic level, failure mode can be interpreted in different ways.
Physical defect
Physical model
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Why Models?
Models
• are easier to work with
• are portable
• can be used for simulation so avoid h/w
requirement at early stage
• Nearly all engineering systems are studied
using models
• are used to bridge the gap between
physical reality and mathematical
abstraction
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Structural Fault Model
• Considering at gate level schematic….
• Let’s start with listing all possible faults
to be considered
• For gate level schematic, fault may be
in:
• components (i.e. gate)
• nets (i.e. connections)
• Let’s assume components are fault free
(not a good assumption?? but for a moment….let’s
assume, we will justify the assumption later on….. )
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• So the nets are only culprits…..
• The nets may be open or shorted with some other net
• Let’s focus on nets shorted with some other one else
and
• neglect net open for a while.
• Nets may be shorted with Vdd line, ground line or some
other active net.
• If net connected with some other net
• bridge fault
• Net connected to power line
• stuck-at-1 fault,
• Net connected to ground line
• stuck-at-0 line
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• We will consider bridge fault later on……..
• FOCUS ON STUCK-AT FAULTS ONLY
• For a given fault model with k different types of
faults that can occur at each of n different
potential fault sites,
• So for n nets, there are 3n-1 possible faulty
conditions to be considered separately for
stuck-at fault model.
• Prepare the list for
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Single Stuck at Fault (SSF)
• Let’s consider, there is only one stuck at fault at a time,
• Ignore multiple suck-at faults
• Considering only single stuck-at a time…..2n possible
faults
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Stuck-at Faults,
So classic, so legacy…
• Eldred (1959) – First use of structural testing for the Honeywell Datamatic 1000 computer
• Galey, Norby, Roth (1961) – First publication of stuck-at-0 and stuck-at-1 faults
• Seshu & Freeman (1962) – Use of stuck-faults for parallel fault simulation
• Poage (1963) – Theoretical analysis of stuck-at faults
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Stuck-at Faults:
Classical Faults
• Why stuck-at faults are considered as classical
faults?
• They are found capable to detect other type of faults
also.
• Relates to yield modeling
• Simple to use
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Stuck-At Faults
• Single Stuck-at fault
• Only one line is faulty at a time
• The faulty line is permanently stuck at either zero or
one
• Stuck at zero (s-a-0)
• Stuck-at-one (s-a-1)
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Example of single stuck-at fault
• Taking an example of an
AND gate as shown below:
Inputs
AB
True
Response Faulty Response
A/0 B/0 Z/0 A/1 B/1 Z/1
00 0 0 0 0 0 0 1
01 0 0 0 0 1 0 1
10 0 0 0 0 0 1 1
11 1 0 0 0 1 1 1
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Detectable Faults
• For any fault/faults to be detectable, the output must
have the different value compared to the error free
output. For digital function, if error free output is 1, the
erroneous output should be 0 and vice versa.
• Zf(t) /= Z(t) Zf(t) XOR Z(t) = 1
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Single Stuck At Fault
• Find the test vector for given fault,
1100 0T(1F)
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One more…
S-a-1
S-a-0
S-a-1
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Redundant/Undetectable Fault
• For which Zf(t) = Z(t)
• As redundant fault do not change the functionality
of circuit, should it be ignored?.....
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Try this for a s-a-1….
• Undetectable fault a s-a-1
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For b s-a-0 ??
• b s-a-0 is detected by t=1101
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Multiple faults
{ a s-a-1, b s-a-0}….
• In presence of a s-a-1 undetectable fault, b
is no longer detected by t=1101 but it is
detected by t=0X0X
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c s-a-1 is undetectable Z= AB, Zf=AB
a s-a-0 is detectable by 110
Fault {c s-a-1, a s-a-0} is undetectable.
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Effect of Undetectable Fault
• If f is detectable fault and g is an undetectable
fault, then f may become undetectable in presence
of g. Such a fault f is called a second generation
redundant fault.
• Two undetectable single faults f and g may become
detectable if simultaneously present.
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Why single stuck-at fault?
• If we consider multiple stuck at faults, we will have to consider total 3n-1 possible fault. Even for moderate n, the number of faults rises to a large amount.
• Considering single-stuck at fault, this number reduces to 2n.
• Further the single stuck-at fault gives a quite good fault coverage nearly 99%.
• Frequent testing strategy But frequent testing is not enough in following condition.
1. Some physical faults manifest as multiple faults in high density chips
2. Prior to first testing in newly manufactured chip, multiple faults can exist
3. If testing experiment does not detect every fault, the circuit will contain undetectable fault every time.
In most cases, a multiple fault can be detected by the tests designed for the individual single faults that can compose the multiple one.
So single fault assumption is mostly adopted.
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Fault Equivalence
(by structural approach) • Two faults of a Boolean circuit are called
equivalent iff they transform the circuit such
that the two faulty circuits have identical output
functions. Equivalent faults are also called
indistinguishable and have exactly the same set
of tests.
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Fault Equivalence
at Fan-out Branches
• The stuck-at fault on stem is equivalent to multiple stuck-at fault on all branches. Prove this.
• A
• X s-a-0, the test set is a1, x0, y1
• Y s-a-0, the test set is a1, x1, y0
• A s-a-0, the test set is a1, x0, y0
• X, Y, A s-a-0 are not equivalent but A s-a-0 is equivalent to multiple fault {x s-a-0, y s-a-0}
X
Y
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Fault Equivalence
(by functional approach)
• What is the relation between F1, F2, F3
and F4?
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Fault Collapsing
• The input to output pass? or output to input pass?
• s-a-0 at d to keep or s-a-0 at e to keep or s-a-1 at g to keep? Why?
• Input to output pass. Because the Boolean gate has always single output and collapsing is not possible for fanout. So no one has to choose one i/p from multiple i/p. The selection of i/p can affect the overall no. of fault reduction.
• Collapse Ratio = # of faults in collapsed fault set/ # all faults
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Example of Fault Collapsing
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Fault Dominance
• If all test of some fault f2 detects another
fault f1, then f1 is said to dominate f2. f1
is removed from fault list.
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Let’s Develop our own EDA tool for fault
equivalence…….
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• Express circuit at gate level as a program
consisting of interconnected logic operations
• External representation in the form of
netlist…ISCAS format, uv fomat, EDIF format…
• Execute the program on netlist to determine the
circuit output for varying input.
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Steps to develop EDA tool….
• Let’s summarize how we will do it……
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Some other fault
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Transistor (Switch) Faults
• MOS transistor is considered an ideal switch
and two types of faults are modeled:
• Stuck-open -- a single transistor is permanently
stuck in the open state.
• Stuck-short -- a single transistor is permanently
shorted irrespective of its gate voltage.
• Detection of a stuck-open fault requires two
vectors.
• Detection of a stuck-short fault requires the
measurement of quiescent current (IDDQ).
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Stuck-Open Fault
Two-vector s-op test can be constructed by ordering two s-at tests
A
B
VDD
C
pMOS
FETs
nMOS
FETs
Stuck-
open
1
0
0
0
0 1(Z)
Good circuit states
Faulty circuit states
Vector 1: test for A s-a-0
(Initialization vector)
Vector 2 (test for A s-a-1)
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Modelling of Open Faults
• Stuck open fault of a pMOS can be modelled as a s-a-1
fault at the corresponding input signal
• Stuck open fault of a nMOS can be modelled as a s-a-o
fault at the corresponding input signal
• One more reason why stuck-at are called classical
faults!!!
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Stuck-Short Example
A
B
VDD
C
pMOS
FETs
nMOS
FETs
Stuck-
short 1
0
0 (X)
Good circuit state
Faulty circuit state
Test vector for A s-a-0
IDDQ path in
faulty circuit
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Bridge Fault
• After single stuck-at faults, bridge faults are the most important class of faults.
• Most commonly occurring type of fault.
• Simplified model assumes 0 resistance (short) between two lines (dotted line in the figure)
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Wired AND –Wired OR
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Wired AND/OR
• Depends on types of Gates driving the shorted lines and
inputs to the Gates
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Not known to fault models…
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Dominant Bridging Faults
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Dominant bridging Faults cont…
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• Wired-AND
• y=0 --> x is s-a-0
• Test for bridge fault: • Set y to 0 and test for x s-a-0 –or-
• Set x to 0 and test for y s-a-0
• Wired-OR
• y=1 --> x is s-a-1
• Test for bridge fault: • Set y to 1 and test for x s-a-1 –or-
• Set x to 1 and test for y s-a-1
• Dominant driver
• x always outdrives y
• y always outdrives x
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Bridge Fault cont….
• Need to consider drive strengths of bridged nodes to determine voltage level.
• Gates driven by the bridged nodes may interpret the voltage level differently, depending on their logic threshold voltages.
• The faulty logic value depends on:
• The relative strength of pull-up and pull-down network
• The number of transistors that are activated in conflicting network
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Bridge Fault cont….
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Feedback Bridge Faults
• In a feedback bridge fault, there exists at least one path between the two bridged nodes.
• The back line b is the line closest to the PI’s.
• The front line f is the line closest to the PO’s.
• AND:
• set b=0 and test for f s-a-0 (no logical feedback)
• set f=0 and test for b s-a-0, but not through f (i.e., f is not sensitive to b).
• OR: ???
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IDDQ Testing
• It relies on measuring the supply current (Idd)
in the quiescent state (when the circuit is not
switching and inputs are held at static values).
The current consumed in the state is
commonly called Iddq for Idd (quiescent) and
hence the name.
• IDDQ testing refers to the integrated circuit
(IC) testing method based upon measurement
of steady state power-supply current.
• Iddq stands for quiescent Idd, or quiescent
power-supply current.
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IDDQ Testing cont….
• In case of a defect such as gate-oxide short or short
between two metal lines, a conduction path from power-
supply (Vdd) to ground (Gnd) is formed and
subsequently the circuit dissipates significantly high
current.
• This faulty current is a few orders of magnitude higher
than the fault-free leakage current.
• Iddq testing provides physical defect oriented testing
• SoCs contain huge number of transistors
• Summation of leakage current of all transistors becomes
too large to distinguish between faulty and fault-free
chips
• Most of the SoCs contain multiple power supplies
• Iddq testing is done on one power supply at a time
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IDDQ Testing…..cont….
• Measure IDDQ current through Vss bus
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IDDT testing
• When a CMOS circuit switches state, a momentary
path is established between the supply lines and
results in dynamic current IDDT
• IDDT exhibits spikes every time circuit switches. The
magnitude and frequency components of the
waveform depends upon switching activity.
• By observing the magnitude and frequency
spectrum of IDDT, addition diagnostic information
about possible defects unmatched with IDDQ and
other methods can be found.
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THANKS!
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