Test and Design for Testability of Analog and Mixed-Signal Circuits … · 2018. 11. 18. · Boundary-Scan Architecture • IEEE-P 1149.2 - Extended Digital Serial Subset • IEEE-P1149.3

José Machado da Silva Test and DfT of Analog and Mixed-Signal Circuits 1

Test and Design for Testability of Analog and Mixed-Signal Circuits

ACEOLE - PH-ESE Electronics Seminars 4-5 February 2010

José Machado da Silva

U.Porto – Faculdade de Engenharia

INESC Porto


Summary

• Basic concepts on testing and design for testability

• Defect, fault modeling and test metrics

• Design for testability and built-in self-test

– structural and functional test

• Standard test infrastructures

• Digital signal processing based testing


Standard test infrastructures



IEEE 1149.1 (JTAG) I/O Scan Cell


Standard test infrastructuresChip-to-Chip Testing with Scan



IEEE 1149.1 TAP Controller

• Uses a state machine whose flow diagram is controlled by the TMS pin (next slide)– Generates shift, load and mode control signals required for

the scan chain operations

• Includes both a data and instruction register• Data register shifts test data into and out of the scan path

• Instruction registers allows incorporation of more powerful operations which allows flexibility for future scan architectures

• Can be used to initiate BIST operations



Other Scan Architectures

• IEEE-1149. I - Standard Test Access Port and Boundary-Scan Architecture

• IEEE-P 1149.2 - Extended Digital Serial Subset

• IEEE-P1149.3 – Standard for a System Test Bus (abandoned)

• IEEE-1149.4 - Mixed Signal Test Bus

• IEEE-I 149.5 -Standard Module Test and Maintenance (MTM) Bus Protocol - “System Level”protocol for control of multiple-board testing


Standard test infrastructuresIEEE Standard 1149.6: Boundary-Scan Testing of

Advanced Digital Networks

• AC coupling is becoming more common in high-speed devices

• Eliminates problems like DC offsets

• Increase testability of interconnects between high-speed differential AC-coupled devices

• 2 modes of operation: edge detection mode for AC-coupled transmission lines and level detection mode for DC-coupled lines


Standard test infrastructures• Delayed and filtered self-referenced waveform

reconstruction of both DC and AC-coupled waveforms by a test receiver


Standard test infrastructuresP1149.7 Proposal Standard

• Adds a new protocol layer on top of 1149.1

• Preserves existing software and hardware

• 2 pin interface in addition to 4-5 pin interface

• Supports multiple TAPs on one chip

• Multiple higher performance transfer protocols

• Provides more advanced system-level control

• Intended for small systems with limited I/O but large SOC chips with many TAPs per chip


Standard test infrastructuresIEEE 1149.1 Test Bus

MiscellaneousRegisters

Instruction Register

BypassRegister

TAP

MUX

BS Test Bus Circuitry

APPLICATION LOGIC

TDI

TMS

TCK

TDO

OPTIONAL

BIST registersScan registers

Sin

Sout

I/O Pad Boundary-scan cell Boundary-scan path

[IEEE1149.1]

© IEEE 1990

Bonding wire



1

0

Shift DR

Capture DR

Select DR

Exit-1 DR

Pause DR

Exit-2 DR

Update DR

Test LogicReset

Run Test /Idle

Shift IR

Capture IR

Select IR

Exit-1 IR

Pause IR

Exit-2 IR

Update IR

1

1

1

1

1

1

1

0

0

0

0

0

0

0

1 1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1149.1 TAP Controller State Diagram BS infrastructur e


Standard test infrastructuresThe IEEE 1149.4 standard for mixed signal test

Core

TBIC

SH

SL

VH

SB1 SB2

-+ c

c

cc

TDO

TDI AB1AB2

VL

TBIC

ATAP

SG

VG

CoreR

AT1

AT2

TDI

TDO

TMSTCK

ABM

AT 2

AT 1

ATAP

VTH

http://grouper.ieee.org/groups/1149/4/



BST infrastructure (except the BST register)

TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

• Defines an extension to 1149.1, to which it adds:

– An analogue test port (ATAP )with two pins (AT1, AT2)

– An internal analogue test bus(AB1, AB2)

– A test bus interface circuit (TBIC)

– The analogue boundary modules (ABM )

Architecture of an IEEE 1149.1/4 compliant device



AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp S1

S3

S2

S4 S9 S10

S8 S7 S5 S6


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

TBIC: The switching structure



AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Main testing conditions

TBIC: Switching structure patterns



AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Switching assignments for defined instructions (TBI C)


TBIC: Control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

Serial input

mux

C/S

L

Parallel input

Parallel output

Serial output

Parallel input

Serial input

Serial output

Parallel input

Parallel input

Parallel input

S1 S2 S10

Control logic

Parallel output

Mode

Inputs available to the user VTH VTH

AT1 AT2 Switching structure comparators

Switching structure

Parallel output

Parallel output

Parallel output


Standard test infrastructuresThe analogue boundary modules (ABM)

• The ABMs in the analogue pins extend the test functions made available by the DBMs

• All test operations combine digital (via TAP) and analogue test “vectors” (via ATAP)

• Each ABM comprises a switching structure and a control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO



SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD

Internal analog block


TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

ABMs: Switching structure


ABMs: Switching structure patterns (1)

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD


Main testing conditions for analogue

measurements


ABMs: Switching structure patterns (2)

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD


Normal mission mode; pin connected

to core only.


ABMs: Switching pattern requirements

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD




TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

Serial input

mux

C/S

L

Parallel input

Parallel output

Serial output

Parallel input

Serial input

Serial output

Parallel input

Parallel input

Parallel input

SD SH SB2

Control logic

Parallel output

Mode

Inputs available to the user

VTH

Pin

Switching structure comparator

Switching structure

Parallel output

Parallel output

Parallel output

ABMs: Controlstructure


Standard test infrastructuresThe 1149.4 register structure is entirely digital and identical to the corresponding1149.1 structure

User registers

Identification register

Reg. BP

Decoder

Instruction reg.

Data mux

Data / instruction mux

TAP contr.

TDI

/TRST TMS TCK

TDO

BST register

TBIC cells

ABM cells

DBM (BST cells in 1149.1)


The PROBE instruction

• The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE:– The selected data register is the BS register

– One or both of the ATAP pins connect to the corresponding AB1/AB2 internal test bus lines

– Analog pins connect to the core and to AB1/AB2 as defined by the ABM 4-bit control word

– Each DBM operates in transparent mode



SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Observability of analog(input / output) pins

• The signal present at any analog (input / output) pin may be observed at AT2, with (or without) the core connected to the pin


ABM

DBM

AT1 AT2

TDI

TMS

TCK

TDO

ABM

DBM

TBIC

(AB1, AB2)



SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Controllability of analog(input / output) pins

• The signal present at any analog (input / output) pin may be driven from AT1, regardless of the signal present at the analog input


ABM

DBM

AT1 AT2

TDI

TMS

TCK

TDO

ABM

DBM

TBIC

(AB1, AB2)


SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6



TBIC

ABM

DBM

(AB1, AB2)

AT1 AT2

TDI

TMS

TCK

TDO

IT

VVT

ZD = VT / IT if:

• ZV >> ZS6 + ZSB2

• ZV + ZS6 + ZSB2 >> ZD

ZD

Impedance measurement between pin and ground



SH SL SG

SB1 SB2 Analog output

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2

Analog input

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2 Analog output

AB2

AB1 VH VL VG VTH

SD


SH SL SG

SB1 SB2

Analog input

AB2

AB1 VH VL VG VTH

SD


VVVVHHHH

VVVVLLLL

????

Interconnect testing with 1149.4



• CMOS or other types of switches– Signal crosstalk

– Capacitive loading

– Increased noise and distortion

• In most cases the designer will need to use T-switch configurations to minimize these problems– Standard does not specify the switch types

– Problems are not insurmountable, they require careful consideration of imperfections introduced.



SB1 SB2

SD CORE

IC

TBICAT1

Stimulusgenerator

SB1 SB2

SDCORE

IC

Observer/Test instrument

AT 2

Control Observation

TBIC



• Test of Simple Interconnects

SD

VH

CORESD

CORE

IC 1 IC 2

AB1AB2 TBIC TBIC

SH

SL

VL

VH

VL

SH

SL

AT1AT2

-+ c

c

cc

TDI

Thresholdvoltage

TDO



Discrete Component Testing (Two-line method)

Parker, McDermid, Oresjo“Structure and Metrology for an Analog Testability Bus”, ITC 93

V1- V2I

R =

SB1 SB2

SD

SB1 SB2

CORESD

CORE

R

IC 1 IC 2

AB1AB2

I V1

TBIC TBIC

VH

VL

SH

SL

AT1

AT2

V2

V1 V2



Discrete Component Testing (Single line method)

Lu, Mao, Dandapani, Gulati“Structure and Metrology for a Single-wire Analog Testability Bus”, ITC 94

SB1 SB2

SD

SB1 SB2

SD R

IC 1 IC 2

AB

IV11V12

SH

VL

VH

SL

R

IC 1 IC 2

AB

IV21

SB2

SD

SB2SB1

SH

SLSB1

SD

VH

VL

V22

2V12-V11-2V22+V21I

R =


Standard test infrastructures• The power supply based method

R

IC 1 IC 2

AT

V2

VL

VDDIDDT=IDD0+∆I

S L SL

S HSDSD

SB2

SD R

IC 1 IC 2

AT

V1

VDDIDDT=IDD0+∆I

SL

S H S H

SD

SB2

V1-V2∆I

R =J. Machado da Silva, J. S. Matos“Implementation of Mixed Current/VoltageTesting Using the IEEEP1149.4 Infrastructure”, ITC 97

José Machado da Silva Test and DfT of Analog and Mixed-Signal Circuits


+

-

R1 R2

CS

vS

iDD

VDDA

D

CB

C1

C2

V

O

IC 2

TBIC

1

IC 1

1

AB2

TBIC

Core

AT1

AT2

AB

SB+

-

R1 R2v

VDD

C1

C2

A

C

CS

Stimulusgenerator


Observation of V OUT and i DD


Standard test infrastructuresPerformance degradation

0 50 100 150 200 250 300 350 400-0.15

-0.1

-0.05

0

0.05

0.1

0.15

input without ABMs with ABMsS1=1.6 kΩ

@923 Hz

+

-


DSP based test

Data acquisition and generation board

IEEE 1149.1/4 bus

IP

TAP ADC

DSP

MemCPU

MATLAB

Data Acquisition Toolbox

Data Acquisition Engine

Hardware Driver Adaptor

Data Acquisition Board

CUT

Test Buses

Software Engine

Hardware Engine

M-File Functions

PC based mixed-signal tester

A 1149.1/4 Toolbox for the Generation of Mixed-Signal Test ProgramsWithin a MATLAB Environment,Gabriel Pinho, José Machado da Silva, and José S. MatosProceedings of DCIS Conference, 2003


DSP based testMATLAB 1149.4 test generation toolbox Functions dedicated to the generation of TAP state

machine control signals;

Functions to load and store data in instruction and boundary-scan registers;

Digital test functions (BYPASS, EXTEST, SAMPLE/PRELOAD and INTEST IEEE 1149.1 instructions) and commands;

Analogue test functions (PROBE instruction) and commands;


DSP based test

Estimation of gain, offset error and the amplitude of a set of harmonics of an ADC;

Find the transfer function polynomial that best fits a set of points (x, y), obtained from the ADC test operation (harmonics can be found after a matricial transformation);

The SCANSTA400 chip drives the test stimulus into the ADC input (through the AT1-A01 path), being serial output data is captured with the data acquisition board;

Test stimulusTest of an ADC


Test method• apply the proper k DC levels

(x coordinates) and obtain M samples for each one

• obtain the respective average values (y coordinates)

• find the best fitting polynomial(vector P=[p0, p1, …, pk-1]

T)• find hi coefficients

(vector H=[h0, h1, …, hk-1]T)

• calculate ADC parameters(Vos, G, and Hn)

DSP based test

∑−

===

1

0

)(k

i

ii xpxpy

∑−

==

1

0

cosk

ii tihy ω

on-chip

x

yADC transferfunction

off-chip

P

H

"Computing ADC’s Harmonic Content from a Reduced Number of Values",

IEEE IMtc Conference, Vail, Colorado, Maio, 2003.


DSP based testtransfer_function_ADC routine

% Create digital I/O (DIO) and analogue output (AO) objects, add lines and channels to the device objects, and configure properties values.…% not relevant code omitted

change_state('TEST_LOGIC_RESET','SHIFT_IR');

load_IR(EXTEST);

change_state('EXIT1_IR','SHIFT_DR');

% ABMs configuration

write_BS([ 10000000000000000000 001000000000000000 0000000000]);

change_state('EXIT1_DR','SHIFT_IR');

load_IR(PROBE);

change_state('EXIT1_IR','UPDATE_IR');

% Generate data to be queued

num_samples=1000;

DC_level=1;

noise=(rand(1,num_samples)-0.5)*0.5;

ADCinput_signal=DC_level+noise;

% Begin ADC algorithm

for i=1:num_samples

% 1st sample is queued

putdata(ao,ADCinput_signal(i));

start(ao) % Generate data

putvalue(dio.Line(6),0); % Start conversion

putvalue(dio.Line(6),1);

stop(ao);

% Read the 16-bit ADC serial output

for j=1:16


output_signal(i,j)=getvalue(dio.Line(8));


end

end

% Calculate the average input and output voltage (x and y coordinates)

… % not relevant omitted code

change_state('UPDATE_IR','TEST_LOGIC_RESET');

… % not relevant omitted code


DSP based testAn ADC Test Wrapper

• Reduce test data transfers to reduce test time

• Use in-circuit data processing to reduce data transfers

• Reduce area by re-using reconfigurable logic

• Use standard test bus to maintain test hierarchy and

uniformity

– Mandatory instructions plus MYRunBIST and CLAMP are

implemented

A Wrapper for Testing Analogue to Digital Converter Cores in SoCsJ. A. Braga, J. Machado da Silva, J. C. Alves, and J. S. Matos9th IEEE European Test Symposium 25th, May, 2004


DSP based test

TAP

WSI WSO

AT1,2, clock

WIP

1149.1/4

ADC

D0

Md

/OE /SC

Ref± /Oflw D7

/CS /EC

Ain

WBC

WBC

WBC

ABM

TBIC

AT1

AT2 ABM

Test controller Pre-processing

Signature

WBY

WIR

MUX

clock

Scan chain

Control signals

Analog test bus

F

• IEEE 1149.1/4 test access port

• IEEE 1149.4 analogue test bus

to transport the test stimulus

• IEEE 1149.4 like ABM in the

analogue inputs

• wrapper boundary cells (WBC)

in digital I/O

• three line parallel test bus

• pre-processing logic to

compress data samples and to

compute test signatures

• test signature register


DSP based test

Select-DR-Scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

Select-IR-Scan

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

Run-Test/Idle

Convert

ADCAcc

Add-sign

Inc-sample

Mov-sign

New-Sign

Test-LogicReset

1

1

11

1

1

1

1

1

11

1

1

1

1

1

1

0

0

0

0

00

00

00

0

0

0

0

0

0

/TMS & /EC

0

/TMS &sample<1024

/TMS &sign<5

1

1

1

1

1

Test Flag, Test signature

10

Test controller state machine


DSP based test

FSM_TAP.V

FSM_POS_PROCESS.V

REGISTERS.V

ACCUMULATOR.V

TCK

TMS

TRST

Shift_IR, Update_IR, Clock_IR, reset

Shift_DR, Update_DR, Clock_DR3

select ( IR )

enable

test_flag

SC_in

address[ 2 : 0 ]

operation[ 2 : 0 ]

Clear

8

data[ 7: 0 ]

Reg_Sum [ 11 : 0 ]

CLK_SystCLK_Syst

12

Reset

3

EOC_AD

Data_out_AD[ 7: 0 ]SC_AD

8

cycle

CTRL_SW_ANLG

16

TDI

TDO

Tester interface Select

ADC_CLK


DSP based test

Output_MUX.V

register [ 1: 0 ]

2

2

3 3

1

Clock_DR, Shift_DR, Update_DR

resetClock_IR, Shift_IR, Update_IR

tdo1

tdo2

tdo3

tdo4

M1 M2

DD2D1

tdi1

tdi2

tdi3

tdi4

Reg_Sum [ 11: 0 ]

Address [ 2 : 0 ]

test_flag

enable

DATA_OUT[ 7: 0 ]

EOC_in DATA_IN [ 7 : 0 ]

8 8

12

3

SC_outCTRL_SW_ANLG

16

MUX_Register_Select.V

BOUNDARY_SCAN_CHAIN.V

INSTRUCTION.V

BYPASS.V

SIGNATURE.V

Registers

TDO

TDI

SC_in


DSP based test

FLAG.V

Signature register

TDO_signature

teste_flag

12

12

12

12

12

4

Reset, Clock_DR, Shift_DR, Update_DR

TDI select [ 2: 0 ]

Reg_Sum [ 11 : 0 ]

ta_sig [11:0]

tb_sig [11:0]

tc_sig [11:0]

td_sig [11:0]

te_sig [11:0]

tdo1

tdo2

tdo3

tdo4

3

12

ta.V

tb.V

tc.V

td.V

te.V


DSP based testApplication specific test processor

Managing overall SoCs test operations:

Generate test stimuli

Capture test responses

Test control and scheduling

Perform some preliminary data processing

Control the interface with the external tester


DSP based test

AT1,2

ADC

D0

Md

/OE /SC

Ref± /Ow D7/CS

/EC

AinABM

TBIC

1

2

Test stimulus

Dynamiccontrolsignals

STA400

TDI

TDO

Σ∆Σ∆Σ∆Σ∆modulator

TAP

Analogmissioninput

Testprocessor

1149.1controller

Staticcontrolsignals

AT

EIn

terf

ace

Tes

tsi

gnat

ures

D0 – D7

Analogtestbus

Digital wrapper cells


DSP based test

Coreunder test

Correlation

Correlation

X=A.sin(ωωωωt)

Xc=A.cos(nωωωωt)

RYXs(0)

RYXc(0)

Xs=A.sin(nωωωωt)

|H|=Y/X=2

A2RYXs(0)2 + RYXc(0)2

H = arctg (RYXs(0)/ RYXs(0) ) Gain and phase measured at the fundamental frequency, n=1


DSP based test Implement a cross-correlation based test method

• Gain, phase and harmonic distortion can be obtained.

Test Procedure:

1. Set the test infrastructure to configure the test mode

2. Apply the required test stimulus (50 Hz sine wave with 4Vpp)

3. Wait for the ADC initialization and CUT transient response to settle-down

4. Capture ADC response (16384 samples @ 25.6 kHz)

5. Perform the correlations between the captured response with in-phase and quadrature versions of the stimulus


DSP based testThe instruction set:

• Conventional instructions• Arithmetic/logical instructions, data transfer instructions

• Specific test control Instructions SRTEST – Starts the test procedure.

STIMULUS – Applies a digital stimuli vector to STIMULI BLOCK.

SVSTIMUL – Captures the successive test responses and accumulates it.

SVACC – Stores in memory the final result of the accumulation.

STATE – Changes the TAP controller state machine to aspecified state.

NSHF – Program the BS registers.


DSP based test7 general purpose

registers

2 counter registers

8-bit data bus

16-bit address bus

Memory organized in 3 segments

Code segment

Stimuli data segment

Test response segment

DDS andΣ∆

modulator

An Infrastructure and Application Specific Processo r for testingAn Infrastructure and Application Specific Processo r for testing Analogue and MixedAnalogue and Mixed --Signal Signal SoCsSoCsFrancisco Duarte, José Machado da Silva, José C. Alves and José S. MatosProceedings of the DCIS 2004 Conference,Bordeaux


DSP based testDigital wrapper cells


DSP based testNHARMONICS .EQU 5 ;no. of harmonics to determineSETDDS ;DDS as stimuli generator

; Set test infrastructure MOVC CNT1,11STATE 447MOVC CNT1,39NSHF $FFFFFMOVC CNT1,5STATE $7MOVC CNT1,48NSHF $400101MOVC CNT1,2STATE $3MOVC CNT2,NHARMONICS

;start test executionSTIMULUS ;schedules TSctrl block for

operationTEST_CS5330A ;schedules CUTctrl block for

operationL: XCORR RAD ;performs cross-correlation operation

XCORR LAD ;performs cross-correlation operation

STIMULUSDJNZ CNT2,L ;go to next harmonicMOVC CNT1, 6STATE $3F ; Resets test infrastructure EOTESTHLT

.END


DSP based test

-60h4

-70h5

-55h3

-52h2

Amplitude (dB)Hn/H1

Stimulus Spectrum at the ADC input

Harmonics amplitudes

• These values reflect both the distortion introduced by the ADC, as well as the residual one from the stimulus

• This might lead to the necessity of inserting a buffer to adapt the FPGA output to the load being driven


DSP based testApplication specific test processor

Provides on-chip stimuli generation, test control and scheduling, the control of a compliant IEEE 1149.1/4 test infrastructure, and data processing

These facilities allow reducing The number of signals to be sourced by the tester,

Extension of data to be transferred between the tester and the CUT,

Test time by performing on-chip preprocessing operations

Can be implemented by reusing reconfigurable logic Each test processor can be adapted for the specific test

requirements of each SoC

No significant silicon area overhead is introduced


DSP based test

THD = ΣΣΣΣ |Hn|2

|H1|2n=2N Calculated using the gains measured

for each one of the harmonics, inresponse to a single stimulus

SNR= SINAD–2 - THD2

1

= PΣ∆ - Pfund

Pfund

= V2

Σ∆ - V2fund

V2fund

= 1 - |H|2fund

|H|2fund

SINAD = Pnoise + Pharmonic distortion

Pfund


DSP based test

Inter-face PC

Interface RAM

Test controller

Amplitude calculatio

n Division

Accumulator

Subtra-cter

Resultsregister

Control

Dados

Data

ControlControl

Data

Control

Control

Dados

Control

Dados

Control

Constant (power Σ∆)

Data

Control

Control

Constant(1024)

16 bits

41 bits : 3 x 16 bits

39 bits

Dedicated logic to test a Σ∆Σ∆Σ∆Σ∆ modulator

"Functional In-Circuit Characterisation of Σ∆ Modulators", Jorge Duarte, J. Machado da Silva, J. Silva MatosMeasurement, Elsevier, Special Issue on ADC Modelling and Testing, Vol. 32/4, November, 2002.


DSP based testGain Phase


DSP based test

THD accuracy SINAD accuracy


DSP based testTest by cross-correlating i DD and v OUT

• Observing both iDD and vOUT provides a higher test efficiency

• Cross-correlation enables high fault coverage rates at lower quantisation and sampling resolutions

CorrelatorCUT

Testsignature

“Mixed Current/Voltage Observation Towards Effective Testing of Analog and Mixed-Signal Circuits”,J. Machado da Silva, J. Silva Matos, Ian Bell, G. TaylorJournal of Electronic Testing - TA, Vol. 9, 1996.

( ) ( )( ) ( ) ( )( )( ) ( ) ( ) ( )ττττ

ττ

DDOUTDDOUTDDOUTDDOUT

DDDDgOUTOUTgDDfOUTf

iviviviv

tititvtvT

iv

∂ℜ∂+ℜ∂+∂ℜ+ℜ

∫ =+∂++∂+=ℜ 1


DSP based test

+

-

vS

Cc

MA

MB

MC

MDMF

ME MG

MH

MI

MJ

MK+

-

vEvS

R1 R2

C1

C2VDD

iDD

VSS

0 0.1 0.2 0.3-20

0

20

0 0.1 0.2 0.350

100

150

200

0 0.1 0.2 0.3-10

-5

0

5

10

15

[s][s][s]

Test stimulus Power supply current (mA) Output voltage (V)

0 2 4 6 8 10 1230

40

50

60

70

80

90

100iDD ∪ vOUT

iDD

vOUT

FC[%]

Number of bits

Mixed i DD/vOUT testing


02

46

810

12

0

2040

6080

10040

50

60

70

80

90

100

Number of bitsSamplingstep

FC[%]

DSP based testTest by cross-correlating i DD and v OUT

Samplingstep Number of bits

FC[%]

02

46

810

12

020

4060

80100

20

40

60

80

100

Golden correlation band

-500 -400 -300 -200 -100 0 100 200 300 400 500

-1

0

0.5

1

-1.5

-0.5

Correlation length

LPF:c15x

Faultycorrelation

Correlationlength

T

TO1

O2

Nor

mal

ised

Cor

rela

tion


DSP based test

Higher fault coverage

Lower test errors

Simpler observation

Test by cross-correlating i DD and v OUT


DSP based test+

-

R1 R2

CS

vS

iDD

VDDA

D

CB

C1

C2

V

O

IC 2

TBIC

1

IC 1

1

AB2

TBIC

Core

AT1

AT2

AB

SB+

-

R1 R2v

VDD

C1

C2

A

C

CS

Stimulusgenerator


vOUT and i DD captured with 1149.4


DSP based test

Defective OpAmp1/OpAmp22xC1Nominal Increased iDD

0 40 80 120 160 2000

1

Bit

stre

ams

[sample index]

0 40 80 120 160 2000

1

2

3vAT2

[V]

0 200 400 600-0.5

0

0.5

1

1.5

2

2.5[V]

[sample index]

vOUT iDD

vAT2

Observation in sequencethrough AT2

Observation throughAT2 and digital BS chain


DSP based test

Nominal 2xR12xC1 OpAmp1 OpAmp 2Increased IDD

0 100 200 300 400-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

[no. of instances]v O

UT

i DD

Acquisition throughAT2 and digital BS chain

0 100 200 300 400-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1v O

UT

i DD

[no. of instances]

Acquisition through AT2


DSP based test

“ADC Testing Using Joint Time-Frequency Analysis”

Hélio Mendonça, J. Machado da Silva, J. Silva MatosJournal of Computer Standards & Interfaces, Elsevier, 2001.

Differential Gain and Phase Testing of Video ADCs using Joint Time-Frequency Analysis


DSP based test

J is an integer, J and M have no common dividers

Very good synchronism is required

Coherent sampling


DSP based testADC test - histogram

0 500 1000 1500 2000 2500 3000 3500 4000

0

100

200

300

400

500

600

700

800

900

1000

Conversor Ideal

Codigo (Bin)

Oco

rren

cias

0 500 1000 1500 2000 2500 3000 3500 4000

0

100

200

300

400

500

600

700

800

900

1000

Conversor Nao Ideal

Codigo (Bin)

Oco

rren

cias

[ ] [ ]121

1cos −=

−−= NC kS

kHkT Kπ [ ] [ ] 121

0

−==∑=

Nk

iC kiHkH K


DSP based testADC test - histogram

[ ] [ ] [ ]( )

221

11

−=

−−+=

Nk

Q

kTkTGkDNL

K

[ ] )1(21 −++−= kQQkT nomnom

nom

[ ] [ ] [ ]( )osnomk VkTGkT

QkINL +−=−= ε

[ ] [ ]kTVkTG nomkos =++ ε

10-4

10-3

10-2

10-1

100

101

103

104

105

106

Uncertainty - B

Num

ber

ofsa

mpl

es-

M

N=8 N=10 N=12


DSP based testADC test – Spectral analysis

026

20761

026761

,V

Vlog,SNR

N

,

,SNRN

FS

ef

ef

+−=

−=

0 2000 4000 6000 8000 10000 12000 14000 16000

-140

-120

-100

-80

-60

-40

-20

0

Espectro (32768 amostras)

Frequencia (Bin)

Pot

enci

a (d

Bc)

∑

−=

h

]fh[Yn

logSINAD

2

201020

∑

=

∑

=

=

=

m

h

]f[Y

dB

m

hh

dB

h

logTHD

]f[Y

]f[Y

logTHD

2

2

20

1

2

2

1020

20


DSP based testADC test – comparison between methods

3577289468330 harmonics

2656197368315 harmonics

209514126835 harmonicsSpectralanalysis

(32768 samples)

121453168332768 samples[1]

20886453120833310e6 samplesHistogram

ttotaltprocessingTacquisitionMethod

[1] Coherent sampling

fs= 48 kHz


DSP based test

0 500 1000 1500 2000 2500 3000 3500 40000

100

200

300

400

500

600

700

800

900

1000

Code (Bin)

Occ

urre

nces

OSkk VTGT +⋅= *

( )221

1

∑∑∑∑∑∑∑

−

−=

kk

kkkk

xx

yxyxG

( )22

2

1 ∑∑∑∑∑∑∑

−

−=

kk

kkkkkOS

xx

yxxxyV

e

Vi

e

Vi

e

Vi

l k

bk

ak

l k

bk

ak

l k

bk

ak

( )∑ ++⋅

=k

kkkkkFS

err bbaalV

222

6

1σ

Obtain transfer functionfrom the code histogram

-Q

e

-VFS

k

VFS

0

2 -1N

1

-VFS

VFS

Vo

Vi

ViTk Tk+1

Tk Tk+1

code

Obtain power of quantization error

F. Wagdy, S. S. Awad, “Determining ADC EffectiveNumber of Bits Via Histogram Testing”,IEEE Trans. on Inst. and Meas., August 1991.

SINAD and THD from code histogram


DSP based testSINAD and THD from code histogram - Results

0 500 1000 1500 2000 2500 3000 3500 4000-4

-3

-2

-1

0

1

2

3

4

Code Bin

INL

(LS

B)

ADC 4

ADC 1

ADC 2

ADC 3

Histogram


DSP based testCorrection of code probability

( )∑ ++=k

kkkkkkFSw

err bbaalwV

222

61

µσ

( ) 22 ∑∑∑∑∑∑∑

−

−=

kkkkk

kkkkkkkk

xwxww

ywxwyxwwG

( )22

2

∑∑∑∑∑∑∑

−

−=

kkkkk

kkkkkkkkk

OSxwxww

yxwxwxwywV

∑−=

kkNk w

12

1µ

“Estimation of ADC’s SINAD after the Code Histogram Method”,Hélio S. Mendonça, José Machado da Silva, José S. Matos, IET Journal on Science, Measurement & Technology, Vol.2 nº 2, pp.96-99, 2008.


ADICTSADC simulator and tester in a LabView andMatLab environment


Test and Design for Testability of Analog and Mixed-Signal CircuitsFurther bibliography• Louis Y. Ungar, Tony Ambler, "Economics of Built-in Self-Test," IEEE Design and

Test of Computers, vol. 18, no. 5, pp. 70-79, Sep./Oct. 200

• Ungar, L.Y.; Bleeker, H.; McDermid, J.E.; Hulvershorn, H.;” EEE-1149.x standards: achievements vs. expectations”, AUTOTESTCON Proceedings, 2001. IEEE Systems Readiness Technology Conference20-23 Aug. 2001 Page(s):188 – 205

• E. J. McCluskey, F. Buelow, “IC Quality and Test Transparency,” ITC1988.• Dynamic Characterisation of Analogue-to-Digital Converters", Springer, The

International Series in Engineering and Computer Science, Vol. 860, DominiqueDallet and José Machado da Silva (Eds.), Approx. 300 p., Hardcover, KluwerAcademic Publishers, ISBN: 0-387-25902 3, September 2005.

• Richard H.Williams Charles F. Hawkins, The Economics of GuardbandPlacement, INTERNATIONAL TEST CONFERENCE 1993

• C. WEGENER AND M. P. KENNEDY, “Test Development Through Defect andTest Escape Level Estimation for Data Converters”, JOURNAL OF ELECTRONIC TESTING: Theory and Applications 22, 313–324, 2006

• Gordon W. Roberts and Sadok Aouini, “Mixed-Signal Production

• Test: A Measurement Principle Perspective”, IEEE Design & Test of Computers, September/October 2009.


Test and Design for Testability of Analog and Mixed-Signal Circuits• Ooi, M. P.-L.; Kassim, Z. A.; Demidenko, S. N.; “Shortening Burn-In Test:

Application of HVST and Weibull Statistical Analysis”, IEEE Transactions onInstrumentation and Measurement, V. 56, Issue 3, June 2007 Page(s):990 – 999

• Lin, C.E.; Tsai, M.T.; Tsai, W.I.; Huang, C.L.; “ Consumption power feedback unitfor power electronics burn-in test”,Proceedings of the 1995 IEEE IECON 21st International Conference on Industrial Electronics, Control, and Instrumentation, Volume 1, 6-10 Nov. 1995 Page(s):284 - 289 vol.1

• Yong Han Ng; Yew Hock Low; Demidenko, S.; “Improving Efficiency of IC Burn-InTesting” Instrumentation and Measurement Technology Conference Proceedings. IEEE 12-15 May 2008 Page(s):1685 – 1689

• Bahukudumbi, S.; Chakrabarty, K.; “Power Management for Wafer-Level TestDuring Burn-In” Asian Test Symposium, ATS '08. 17th 24-27 Nov. 2008 Page(s):231 – 236

• Chung-Yuan Tsao; Shiue, R.Y.; Ting, C.C.; Huang, Y.S.; Lin, Y.C.; Yue, J.T.; “Applying dynamic voltage stressing to reduce early failure rate”, ReliabilityPhysics Symposium, 2001. Proceedings. 39th Annual. 2001 IEEE International, 30 April-3 May 2001 Page(s):37 - 41


Test and Design for Testability of Analog and Mixed-Signal Circuits• S. Yellampalli and A. Srivastava, “∆IDDQ Testing of CMOS Data Converters”, J. of

Active and Passive Electronic Devices, Vol. 4, pp. 63–89, 2009.• Karim Arabi and Bozena Kaminska, “ Design for Testability of Embedded Integrated

Operational Amplifiers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 4, APRIL 1998 573.

• Mohamed M. Hafed, Nazmy Abaskharoun, and Gordon W. Roberts,“A 4-GHz Effective Sample Rate Integrated Test Core for Analog and Mixed-Signal Circuits, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 4, APRIL 2002

• Sule Ozev and Alex Orailoglu, An Integrated Tool for Analog Test Generation andFault Simulation, Proceedings of the International Symposium on Quality ElectronicDesign (ISQED.02), 2002.

• Prashant Goteti Giri Devarayanadurg Mani Soma, “DFT for Embedded Charge-Pump PLL Systems Incorporating IEEE 1149.1”, IEEE 1997 CUSTOM INTEGRATED CIRCUITS CONFERENCE

• A. Lu and G. W. Roberts, “An oversampling based analog multitone signalgenerator,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 45, no.3, pp. 391–394, Mar. 1998.

• A. Lu, G. W. Roberts, and D. J. Johns, “A high quality analog oscillator usingoversampling D/A conversion techniques,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 41, no. 7, pp. 437–444, Jul. 1994.


Test and Design for Testability of Analog and Mixed-Signal Circuits• L. Milor, “A Tutorial Introduction to Research on Analog and Mixed-Signal Circuit Testing”,

IEEE Transactions on Circuits and Systems, vol. 45, no 10, pp. 1389-1407, 1998.• M. Sachdev and B. Atzema, “Industrial relevance of Analog IFA: A Fact or Fiction’, Proc.

IEEE Int. Test Conf. 1995, pp. 61-70.• Stephen Sunter, Naveena Nagi, “Test Metrics for Analog Parametric Faults”, Proc. Of

VLSI Test Symposium, pp. 226 – 234, 1999.• Ahcène Bounceur, Salvador Mir, Emmanuel Simeu and Luis Rolíndez., “Estimation of test

metrics for the optimisation of analogue circuit testing”, Journal of Electronic Testing: Theory and Applications (JETTA), 2007.

• Viera Stopjakov´a, Pavol Malosek, Vladislav Nagy, “Neural Network–Based DefectDetection in Analog and Mixed IC Using Digital Signal Pre-processing”, Journal ofElectrical Engineering, vol. 57, no. 5, p. 249–257, 2006.

• Tian, M.W., Shi, C.-J.R., “Rapid Frequency-domain Analog Fault Simulation UnderParameter Tolerances”, Design Automation Conference, June 9-13, p.275 – 280, 1997.

• Abdessatar Abderrahman, Y. Savaria, A. Khouas, M. Sawan, “Accurate TestabilityAnalysis based-on Multi-frequency Test Generation and New Test Metric”, Proc. of IEEE-MWSCAS/NEWCAS, 2007.

• Abdessatar Abderrahman, Eduard Cerny, Kaminska Bozena, “Worst-Case ToleranceAnalysis and CLP-Based Multi-frequency Test Generation for Analog Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 3, p. 332-345, 1999.


Test and Design for Testability of Analog and Mixed-Signal Circuits

ACEOLE - PH-ESE Electronics Seminars 4-5 February 2010

José Machado da Silva

U.Porto – Faculdade de Engenharia

INESC Porto

Documents

Test and Design for Testability of Analog and Mixed-Signal Circuits … · 2018. 11. 18. · Boundary-Scan Architecture • IEEE-P 1149.2 - Extended Digital Serial Subset • IEEE-P1149.3