vlsi Testability

7/13/2019 vlsi Testability

1/50

Technical University Tallinn, ESTONIA

Overview: Testability Evaluation

Outline

Quality Policy of Electronic Design

Tradeoffs of Design for Testability

Testability measures Heuristic measures

Probabilistic measures

Calculation of testability Parker - Mc Cluskey method

Cutting method

Conditional probabilities based method


2/50

Raimund Ubar

Quality Policy

Yield

2

For example 60%, other chips are faulty

Testimine

Defect level

How many chips from

hundred escape?

Chips from

manufactory


3/50


Introduction: The Problem is Money?

Cost of

testing

Quality

Cost of qualityCost

Cost of

the fault

100%0%Optimum

test / quality

How to succ eed?Try too hard!

How to fa il?

Try too hard!

(From American Wisdom )

Conclusion:

The problem of testing

can only be contained

not solved

T.Williams

Time

FaultCoverage

Test

coverage

function

Time


4/50


Design for Testability

The problem is - QUALITY:

Quality policyYield (Y)

P,n

Defect level (DL )

Pa

Design for testability

Testing

P - probability of a defect

n - number of defects

Pa- probability of accepting

a bad product

nPY )1( - probability of producing a good product


5/50Technical University Tallinn, ESTONIA


The problem is - QUALITY:

Quality policyYield (Y)

P,n

Defect level (DL )

Pa

n - number of defects

m- number of faults tested

P - probability of a defectPa- probability of accepting a bad product

T - test coverage

)1()1(

111)1(1)1(

Tnm

nmn

mn

a

n

a YYYPPP

PDL

nm

a PPP )1()1(

n

PY )1(


6/50



The problem is - Money:

Y(%)

T(%)10

10

50

90

50 90

8 5 1

45 25 5

81 45 9

)1(1 TYDL

Goal: DL T Testability

Paradox: TestabilityDL (Y )

DL

T(%)

Y

1000

1


7/50



Tradeoffs: DFT: Resynthesis oradding extra hardware

Performance Logic complexity Area

Number of I/O

Power consumption

Yield

Economic tradeoff:

C(Design + Test)< C(Design)+ C(Test)

Goal: DL T Testability

Paradox: TestabilityDL (Y )


8/50



Economic tradeoff:

C(Design + Test)< C(Design)+ C(Test)

C(DFT) + C(Test)< C(Design)+ C(Test)

Test generation

Testing

Troubleshooting

Volume

C(Test) = CTGEN + (CAPLIC + (1 - Y) CTS) Q

C(DFT) = (CD + CD) + Q(CP+ CP)

DesignProduct


9/50


Testability Criteria

Qualitative criteria for Design for testability:Testing cost:

Test generation time

Test application time

Fault coverage

Test storage cost (test length)

Availability of Automatic Test Equipment

Redesign for testability cost:

Performance degradation

Area overhead

I/O pin demand


10/50


Testability of Design Types

General important relationships:

T (Sequential logic) < T (Combinational logic)

Solutions: Scan-Path design strategy

T (Control logic) < T (Data path)

Solutions: Data-Flow design, Scan-Path design strategies

T (Random logic) < T (Structured logic)

Solutions: Bus-oriented design, Core-oriented design

T (Asynchronous design) < T (Synchronous design)


11/50



T (Sequential logic) < T (Combinational logic

Combinationa

l circuit

IN OUT

R qqCombination

al circuit

IN OUT

R

Scan-IN

Scan-OUT

qq

Solution: Scan-Path design strategy


12/50



T (Control logic) < T (Data path)

Solutions:

Scan-Path design strategie

Data-Flow design

M3

e+M1

a

*M2b

R1

IN

c

d

y1 y2 y3 y4

Control Part

R2

Data Part

Raimund Ubar
http://www.google.com/imgres?imgurl=http://mindmappingsoftwareblog.com/mmsb/wp-content/uploads/2010/09/GordianKnot.jpg&imgrefurl=http://mindmappingsoftwareblog.com/gordian-knot/&usg=__IQnrltRigLceaI38T8ixLWfUu50=&h=276&w=250&sz=15&hl=et&start=7&zoom=1&itbs=1&tbnid=dhwSBqYY3sIdwM:&tbnh=114&tbnw=103&prev=/images%3Fq%3Dgordion%2Bknot%26hl%3Det%26sa%3DG%26gbv%3D2%26tbs%3Disch:1http://www.google.com/imgres?imgurl=http://mindmappingsoftwareblog.com/mmsb/wp-content/uploads/2010/09/GordianKnot.jpg&imgrefurl=http://mindmappingsoftwareblog.com/gordian-knot/&usg=__IQnrltRigLceaI38T8ixLWfUu50=&h=276&w=250&sz=15&hl=et&start=7&zoom=1&itbs=1&tbnid=dhwSBqYY3sIdwM:&tbnh=114&tbnw=103&prev=/images%3Fq%3Dgordion%2Bknot%26hl%3Det%26sa%3DG%26gbv%3D2%26tbs%3Disch:1


13/50

Raimund Ubar

How to test million transistors?

Scan-Path Based Testing

Multi Site Test

ATE

H.-J.Wunderlich, U Stuttgart

All memory componentsare made

transparent via shift registers

Test

patterns

Response

Test

System

Fault
http://www.google.com/imgres?imgurl=http://mindmappingsoftwareblog.com/mmsb/wp-content/uploads/2010/09/GordianKnot.jpg&imgrefurl=http://mindmappingsoftwareblog.com/gordian-knot/&usg=__IQnrltRigLceaI38T8ixLWfUu50=&h=276&w=250&sz=15&hl=et&start=7&zoom=1&itbs=1&tbnid=dhwSBqYY3sIdwM:&tbnh=114&tbnw=103&prev=/images%3Fq%3Dgordion%2Bknot%26hl%3Det%26sa%3DG%26gbv%3D2%26tbs%3Disch:1http://www.google.com/imgres?imgurl=http://mindmappingsoftwareblog.com/mmsb/wp-content/uploads/2010/09/GordianKnot.jpg&imgrefurl=http://mindmappingsoftwareblog.com/gordian-knot/&usg=__IQnrltRigLceaI38T8ixLWfUu50=&h=276&w=250&sz=15&hl=et&start=7&zoom=1&itbs=1&tbnid=dhwSBqYY3sIdwM:&tbnh=114&tbnw=103&prev=/images%3Fq%3Dgordion%2Bknot%26hl%3Det%26sa%3DG%26gbv%3D2%26tbs%3Disch:1


14/50



T (Random logic) < T (Structured logic)Solutions: Bus-oriented design, Core-oriented design

System

16 bit

counter

&

1

Sequence of

216bits

Sea of gates


15/50


Testability Estimation Rules of Thumb

Circuits less controllable

Decoders

Circuits with feedback

Counters

Clock generators

Oscillators

Self-timing circuits

Self-resetting circuits

Circuits less observable

Circuits with feedback

Embedded

RAMs

ROMs PLAs

Error-checking circuits

Circuits with redundant

nodes


16/50


Bad Testability: Fault Redundancy

1

&

&

&

1&

x1

x2

&x4x3

y

0

)(

2

434211

x

y

xxxxxxy

Faults atx2 is not testable

Optimized function:

Internal signal dependencies:

1

&

&1

11

1

1

Impossible pattern,

OR

XOR is not testable

341 xxxy

Redundant gates (bad design):

CREDES Summer School Raimund Ubar


17/50

CREDES Summer School

Fault Redundancy

1

&

&

&

1

1

01

1

0

01

1

Hazard control circuit:

Redundant AND-gateFault

0 is not testable

10

Error control circuitry:

Decoder

1

E = 1 if decoder is fault-free

Fault 1 is not testable

E=1

17

101

Hazard



18/50

Fault Redundancy

0

)(

2

434211

x

y

xxxxxxy

Faults at x2 arenot testable, the

node is redundant

1

&

&

&

1&

x1

x2

&x4

x3

y

Redundant gates

(bad design):

142

423411211

x

y

xxxxxy

if 04 x

Fault x420 is not testable

x11

1

&

&

&

x1

&x4

x3

y

x41

x42

x12

18



19/50

Fault RedundancyRedundant gates(bad design):

1

&

&

&

x1

&x4

x3

y

142

423411211

x

y

xxxxxy

if 04 x


x41

x42

x11

x12

1

&

&

x1

x3

yx4

x11

x12

112

3411211

x

yxxxxy


if 11 x

341 xxxy

Final result of optimization:

1

x3

y

x1

x4

19


20/50


Testability Measures

Evaluation of testability:

Controllability

C0(i)

C1(j)

Observability

OY(k)

OZ(k)

Testability

12

20

&

&12

20

1

x

DefectProbability of detecting 1/260

12

20 &

12

20 1

i

kj

Y

Z

Controllability for 1 needed


21/50


Heuristic Testability Measures

Controllability calculation: AND gateMeasure: minimum number of nodesthat must be set to produce 0

For inputs: C0(x) = C1(x) = 1

For other signals: recursive calculationstarting from inputs

C0(xi) = 23

C0(xj) = 11

C0(xk)=

C0(x1) = 1

C0(x2) = 1

min [C0(xi), C0(xj) ] + 1 =

= min (23,11) + 1 =12


22/50



Controllability calculation: OR gateMeasure: minimum number of nodesthat must be set to produce 0



C0(xi) = 23

C0(xj) = 11

1C0(xk)=

C0(x1) = 1

C0(x2) = 1

C0(xi) + C0(xj) + 1 =

= 23 + 11 + 1 =35


23/50



Controllability calculation:Measure: minimum number of nodesthat must be set to produce 1



C1(xi) = 23

C1(xj) = 11

&C1(xk)= C1(xi) + C1(xj) + 1 =

= 23 + 11 + 1 =35

C1(x1) = 1

C1(x2) = 1


24/50



Controllability calculation: EXOR gateMeasure: minimum number of nodesthat must be set in order to produce 0



C0(xi) = 23

C1(xi) = 18

C0(xk)= min { [ C0(xi) + C0(xj) ],

[C1(xi) + C1(xj) ] } + 1 =

min{ (23 +12), (18 + 20) } + 1 =

min (35,38) + 1 =36

C0(x1) = 1

C0(x2) = 1

C0(x

j) = 12

C1(xj) = 20


25/50



Controllability calculation:Measure: minimum number of nodes that must be set in order to produce 0 or 1


For other signals: recursive calculation rules:

&x y &

x1

yx2

1x1 yx2

x1 yx2

C0

(y) = minC0

(x1

), C0

(x2

)+ 1

C1(y) = C1(x1) + C1(x2) + 1

C0(y) = C1(x) + 1

C1(y) = C0(x) + 1C1(y) = minC1(x1), C1(x2)+ 1

C0(y) = C0(x1) + C0(x2) + 1

C0(y) = min(C0(x1) + C0(x2)), (C1(x1) + C1(x2))+ 1

C1(y) = min(C0(x1) + C1(x2)), (C1(x1) + C0(x2))+ 1


26/50



Observability calculation:Measure: minimum number of nodes which must be set forfault propagating

For outputs: O(y) = 1


O(xi)= O(xk) + C1(xj) =

= 23 + 11 + 1 = 35

C1(xj) = 11

O(y) = 1

O(xk) = 23


27/50



Observability calculation:Measure: minimum number of nodes which must be set forfault propagating

For outputs: O(y) = 1


&x y&

x1

yx2

1x1 yx2

x1 yx2

O(x1) = O(y) + C1(x2) + 1

O(x) = O(y) + 1 O(x1) = O(y) + C0(x2) + 1

O(x1) = O(y) + 1


28/50



Testability calculation:Measure: sum of controllability and observability

O(xi) = 35

C1(xj) = 11

O(y) = 1

O(xk) = 23

T(x

0) = C1(x) + O(x)

T(x1) = C0(x) + O(x)

T(xi= 0)= O(xi) + C1(xj) = 35 + 16 = 51

C1(xi) = 16


29/50



Controllabilies Obs.x C0(x) C1(x) O(x)

1 1 1 102 1 1 12

3 1 1 114 1 1 11

5 1 1 10

6 1 1 10

7 3 2 971 3 2 11

72 3 2 973 3 2 9

a 4 2 9b 4 2 7

c 4 2 7

d 4 2 7e 5 5 4

y 8 5 1

Controllability and observability:

&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

Macro


30/50



Controllabilies Obs. Testab.x C0(x) C1(x) O(x) T(x0)

1 1 1 10 112 1 1 12 133 1 1 11 124 1 1 11 125 1 1 10 116 1 1 10 11

7 3 2 9 1171 3 2 11 1372 3 2 9 1173 3 2 9 11

a 4 2 9 11b 4 2 7 9c 4 2 7 9d 4 2 7 9e 5 5 4 9

y 8 5 1 6

Testability calculation:

&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

Macro

T(x0) = C1(x) + O(x)

T(x1) = C0(x) + O(x)


31/50


Probabilistic Testability Measures

Controllability calculation:Measure: probability to produce 0 or 1 at the given nodes

For inputs: C0(i) = p(xi=0) = 1 - pxi C1(i) = p(xi=1) = 1 - p(xi=0) = pxi


&x y &

x1

yx2

1x1 yx2

py= px1 px2

py= 1 - pxpy= 1 - (1 - px1)(1 - px2)

&x1 yxn

... xi

n

i

y pp

1

1x1

yxn

...

)1(11

xi

n

i

y pp


32/50



Probabilities of reconverging fanouts:

x1 yx2

py = 1 - (1 - pa ) (1 - pb)

= 1 - 0,75*0,75 = 0,44

&x1

yx2

&

1

a

b

&x y py= px px= px2 ?

Signal correlations:

py = (1px1 ) px2+ (1px2) px1

= 0,25 + 0,25 = 0,5


33/50


Calculation of Signal Probabilities

&x1

yx2

&

1

py = 1 - (1 - pa ) (1 - pb) =

= 1 - (1 - px1(1 - px2))(1 - px2(1 - px1)) =

= 1 - (1 - px1+ px1px2) (1 - px2+ px1px2) =

= 1(1 - px2+ px1px2- px1+ px1 px2- p2x1px2+

+ px1px2- px1 p2x2+ p2x1 p2x2) =

= 1(1 - px2+ px1px2- px1+ px1 px2- px1px2+

+ px1px2- px1 px2+ px1 px2) =

= px2- px1px2+ px1- px1 px2+ px1px2 -

- px1px2+ px1 px2- px1 px2 ) =

= px1 + px2- 2px1px2 = 0,5

a

b

Parker - McCluskeyalgorithm:


34/50



Straightforward methods:

&

&

&

a

c

y&

b

1

2

3

21

22

23

Parker - McCluskey algorithm:

py = pcp2 = (1- papb) p2 =

= (1(1- p1p2) (1- p2p3)) p2 =

= p1p22

+ p22

p3 - p1p23

p3 == p1p2

+ p2p3 - p1p2p3 = 0,38

Calculation gate by gate:

pa= 1p1p2= 0,75,

pb= 0,75, pc= 0,4375, py= 0,22

For all inputs: pk= 1/2


35/50



Parker-McCluskey:

&

&

&

a

c

y&

b

1

2

3

21

22

23

Observability:

p(y/a = 1) = pb p2=

= (1 - p2p3) p2 = p2 - p22p3

= p2 - p2p3 = 0,25

x

Testability:

p(a 1) = p(y/a = 1) (1 - pa) =

= (p2 - p2p3)(p1p2) =

= p1

p2

2

- p1

p2

2p3

=

= p1p2 - p1p2p3 = 0,125



36/50



Idea:

Complexity of exactcalculation is reduced byusing lower and higher

bounds of probabilitiesTechnique:

Reconvergent fan-outs arecut except of one

Probability range of [0,1] isassigned to all the cut lines

The bounds are propagatedby straightforwardcalculation

Cutting method&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

Low er and higher bound s for the

pro babi l i t ies of the cut l ines:

p71 := (0;1), p72 := (0;1), p73 := 0,75


37/50



For all inputs:pk= 0,5

Reconvergent

fan-outs are cut

except of one

71and 72

Probability

range of [0,1] is

assigned to all

the cut lines -

71and 72

The bounds are

propagated by

straightforward

calculation

Cutting method&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

pk [pLB, pHB) Exact pk pk [pLB, pHB) Exact pkp7 3/4 3/4 pb [1/2, 1] 5/8

p71 [0, 1] 3/4 pc 5/8 5/8

p72

[0, 1] 3/4 pd

[1/2, 3/4] 11/16

p73 3/4 3/4 pe [1/4, 3/4] 19/32

pa [1/2, 1] 5/8 py [34/64, 54/64 ] 41/64

Calculat ion steps :

1/2

[0,1]

[1/2,1]

3/4

3/4

1/2

1/2

5/8

[1/2,1]

[1/2,3/4]

[1/4,3/4]

[34/64,54/64]

Exact value:

41/64


38/50



Method of conditional

probabilities

yx

P(y) = p(y/x=0)p(x=0) + p(y/x=1)p(x=1)

)1,0(

)()/(()(i

ixpixypyp

Probabilitiy fory

Conditionsx

set of conditions

Conditional probabilitiyIdea of the method:

Two conditional probabilitiesare calculated along the paths (NB! not bounds as in

the case of the cutting method)

Since no reconvergent fanouts are on the paths, no danger for signal correlations


39/50



Method of conditional

probabilities&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

)1,0(

)()/(()(i

ixpixypyp

yx

NB! Probabilities

Pk= [Pk*= p(xk/x7=0), Pk

**= p(xk/x7=1)]

are propagated, not bounds

as in the cutting method.For all inputs: pk= 1/2

Pk [Pk*, Pk

**] Pk [Pk

*, Pk

**]

P7 Pb [1, 1/2]P71 Pc [1, 1/2]P72 Pd [1/2, 3/4]P73 Pe [1/2, 5/8]

Pa [1, 1/2] Py [1/2, 11/16 ]

3/4

[1,1/2]

[1,1/2]

[1,1/2]

[1/2,3/4]

[1/2,5/8]

[1/2,11/16]

py= p(y/x7=0)(1 - p7) + p(y/x7=1)p7= (1/2 x 1/4) + (11/16 x 3/4) = 41/64


40/50



Using BDDs:

1

21

3

23

3

y L1

L2

py = p(L1) + p(L2) =

= p1 p21 p23+ (1 - p1) p22 p3 p23=

= p1 p2+ p2 p3- p1p2 p3= 0,38

&

&

&

a

c

y&

b

1

2

3

21

22

23


p1 p21 p23

(1-p1)p22p3p23

2

y p2 p1

p2(1-p1)p3

1

22


41/50


Calculating Probabilities on BDDs

&

&

&

a

c

& b

1

2

3

21

22

23

1 21

22

23

3

L1

L2

py = pxL kL (1) xXk

Example:

L1 = (1,21,23)

L2 = (1,22,3,23)

py = p1p2 + p1p2p3 = 0,375


42/50


Heuristic and Probabilistic Measures

py = pxk: L kL (1) xXk

CC1[y] = min { CC1(x(m) } + const .

k: lkL (1) mMk

Heuristic controllability measure:

Probabilistic measure:1 21

22

23

3

L1

L2


43/50


Heuristic Controllabilities

Using BDDs for controllability

calculation:&

&

&

a

c

y&

b

1

2

3

21

22

23

x C0(x) C1(x)

a 3 2

b 3 2

c 5 4

y 2 6

Gate level calculation

1 21

22

23

3

y L1

L2

3 3 1

3 3

BDD-based algorithm

for the heuristic

measure is the same

as for the

probabilistic measure

C1(y) = min [(C1(L1), C1(L2)] + 1 =

= min [C1(x1) + C1(x2),

C0(x1) + C1(x2) + C1(x3)] + 1 == min [2, 3] + 1 = 3


44/50



Using BDDs:

1 21

22

23

3

yL1 L2

Observability:

p(y/x21= 1) = p(L1) p(L2) p(L3) =

= p1 p23(1 - p3) = 0,125

&

&

&

a

c

y&

b

1

2

3

21

22

23

x

L3

Testability:

p(x210) = p21p(y/x21= 1) =

= p21p(L1) p(L2) p(L3) =

= p2p1 (1 - p3) = 0,125

Why: p(y/x21= 1) = p21p(y/x21= 1)?


45/50


Calculating Observabilities on BDDs

&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

Macro

y/x(m) =L(m0,m) L(m1, mT,1) L(m0, mT,0)

p(y/x(m)=1)=p(m0,m) p(m1,mT,1) p(m0,mT,0)

6 73

1

2

5

7271

y


46/50


Calculating Observabilities on BDDs

6 73 5 2

25

2

2

5 2

25

2

2

6

71

72

1/64

1/64

1/64

1/64

4/64

1/64

1/64

1/64

&

&

&

&

&

&

&

1

2

3

4

5

6

7

71

72

73

a

b

c

d

e

y

Macro

6 73

1

2

5

7271

y

Calculation procedure:

p(y/x1= 1) = 11/64


47/50



Combining BDDs and conditional probabilities

x

z

y

w

Using BDDs gives correct results only inside the blocks,

not for the whole system

New method:

Block level: use BDDs and straightforward calculation System level: use conditional probabilities


48/50


Register Transfer Level and DDs

Superposition of word-level DDs:

R2M3

e+M1

a

*M2b

R1

IN

c

d

y1 y2 y3 y4

y4

y3 y1 R1+ R2

IN + R2

R1* R2

IN* R2

y2

R20

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

C l l i RT L l Ob bili i


49/50


Calculating RT-Level Observabilities

py = pxL kL (1) xXk

Gate-level calculation:

RT-level calculation:

Example:

P(R2= R1R2) = P(y4=2) P(y3=3) P(y2=0)

Terminal nodesdata-path):

y4

y3 y1 R1 + R2

IN +R2

R1*R2

IN* R2

y2

R20

1

2 0

1

0

1

0

1

0

R2

IN

R12

3

P(y=z(mT)) =

P(x=e)L iL (m0,m

T) xXi

C l l ti RT l l P b biliti


50/50


Calculating RT-level Probabilities

py = p(y=1) = pxL kL (1) xXk

3,4

02

q

1

01

0q 1

4xA

2

1

5xB

3

Gate-level calculation:

RT-level calculation:

P(y=k) = P(x=e)L iL (k) xXi

Example:P(q=5) = P(q=2)P(xB=0) + P(q=3) +P(q=4)

Nonterminal nodes

(control-path):

Documents

vlsi Testability