Szu-Wei Huang, C-V Lab, GIEE of NTU 1 黃思維 F90943078 Graduate Institute of Electronics Engineering National Taiwan University Advanced Multi-Gate Technologies

Szu-Wei Huang, C-V Lab, GIEE of NTU 1

黃思維F90943078

Graduate Institute of Electronics Engineering

National Taiwan University

Advanced Multi-Gate Technologies

for the Sub-25 nm Regime


Conventional Planar Bulk MOSFET

Challenges for Planar Bulk MOSFETs Scaling

Gate Leakage Current

Packing Density

Drive Current

Short Channel Effect (SCE)

Drain Induced Barrier Lowing (DIBL)

Device Scalability

Process Complexity


Advantages of Non-Planar MOSFET

Ultra-Thin Body (UTB) Structure

Current Driven by Multi-Gate

Excellent Short-Channel Behavior

Better Gate-to-Channel Controllability

Reduced DIBL

Potential Scalability

CMOS-compatible Process


Non-Planar MOSFET

Device Evolution of Non-Planar MOSFETs

Dimension Restriction of

Non-Planar MOSFETs


Thickness of Si Body Tsb

UTB-SOI

DST

FinFET

-FET

Tsb ≤ 1/3 Lg

Tsb ≤ 1/3 Lg

Tsb ≤ 2/3 Lg

Tsb ≤ Lg


FinFET with 10-nm Gate LengthLayout and Process Flow

Fabricated with

(110) Orientation to Enhance Hole

Mobility


FinFET with 10-nm Gate LengthCross-section and Top View

Tox = 17 Å

Tsb : 17~26 nm

Double Gate Device


FinFET with 10-nm Gate LengthElectrical Characteristics

WCH = 2 Hfin

SCE Reduced Due to :Thicker Tsb

Dual Gate StructureAbrupt S/D Junction


FinFET with 10-nm Gate LengthCarrier Mobility on (110) Orientation

Field in Inversion Layer

(110) Crystal OrientationHole Mobility


FinFET with 10-nm Gate LengthCMOS-FinFET Inverter


FinFET with 10-nm Gate LengthDevice Performance

Double Gate NMOS PMOS

Lg (nm) 10

Tsb (nm) 17~26

VDD (V) 1.2

Tox (Å) 17

Id (µA/µm) 446 356

Swing (mV/dec) 125 101

DIBL (mV/V) 71 120

Gate Delay (ps) 0.34 0.43


-FET with 25-nm Gate Length

Triple-Gate Device Structure

Gate Extension Under Si Body

Decreasing Drain-Induced-Barrier-LowingIncreasing Gate-to-Channel Controllability



Cross-Section View

Tox = 17~19 Å

Tsb = 25 nm

HSi = 55 nm

Tsb Shielding Electrical Field from Drain

Reducing Parasitic Resistance


Characteristics of |VD|=1V Version


WCH = 2 Hfin + Tsb



Characteristics of |VD|=0.7V Version

Gate Delay (ps)

NMOS 0.39

PMOS 0.88

WCH = Hfin



Gate Delay Comparison of |VD|=0.7V Version

Gate Delay is Defined as ( CV/I )



Demonstration of Multiple CMOS -FET Circuit


Comparison of Device Geometry

H W

UTB-SOI ≤1/3Lg

FinFET ≤2/3Lg

-FET ≥2Lg Lg

If Channel Length = Lg


Process Refinements of FinFETHydrogen Annealing

Higher Surface Quality

Improved Drive Current

Lower Gate NoiseMetal Gate Engineering

Ideal Mobility Lower Gate Leakage Current Higher Transconductance Competitive ION/IOFF Ratio

Adjustable Vt


Hydrogen AnnealingIncreased Surface Si Migration Rate

Red Circle:ImprovedLine Edge

Roughness

Blue Circle:ImprovedSidewall

Roughness


Hydrogen Annealing

Increased Current Due To Decreased Surface Trap Density

NMOS Drive Current is More Degraded Due To the Closer Inversion Charge Centroid of Electrons


Hydrogen AnnealingEquivalent Gate Voltage Noise SVG

SVG=Output Drain Current Noise/Transconductance

Hydrogen Annealing Forms High Quality Surface


Hydrogen AnnealingCarrier Mobility on the (110) Orientation

Mobility Degradation Due to Surface Roughness Scattering µSR1/(Eeff Δ)2, where Δ is the Root-Mean-Square Value of Surface Roughness


Metal Gate Engineering

Gate Work Function for FDSOI CMOS FinFET Technology is 4.4-5.0 eV.Molybdenum Gate

A work Function of ~5V which is suitable for p-FinFET

Nitrogen Implanted into Molybdenum Followed by Annealing Results in Work Function of ~4.4V which is suitable for n-FinFET

Molybdenum-Gated FinFET


Metal Gate EngineeringMolybdenum-Gated FinFET

Nitrogen was implanted at a tilt of 60O

Poly-Silicon was used to prevent oxidation and ion channeling



Mo Gate was etched by Cl2 and O2 plasma

40 nm Mo Gate with 400 nm cap Poly-Si



PVD Mo is discontinuous due to the undercut of buried oxide caused by over-etching by HF



Multi-Vt is observed by nitrogen implantation

Gate work Function was changed by nitrogen implantation


Metal Gate EngineeringNiSi-Gated FinFET

(110) Orientation

NiSi Gate

CoSi2 Raised S/D

Lg = 100 nm

Tsb = 25 nm

Tox = 16 Å



W = 2 Hfin



10% Gm Gain achieved by the elimination of Poly-Depletion Effect



Gate Leakage of NiSi-Gated FinFET is Lower than Poly-Si-Gated FinFET


Conclusion

10 nm CMOS FinFET and 25 nm CMOS -FET have been successfully fabricated.

Excellent SCE and DIBL and other electrical characteristics of both FinFET and -FET are obtained.

CMOS circuit for both 10 nm CMOS FinFET and 25 nm CMOS -FET are demonstrated.

Hydrogen annealing has verified to smoothen the line edge and sidewall surface roughness, in which the mobility and the gate noise are therefore improved.

The gate work function has shown to be adjusted by using the metal/silicide gate to acquire desired device properties.


References

[1] J. Kedzierski, et al, “Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation,” IEDM Tech. Dig., 2002, pp. 247-250.

[2] B. Yu, et al, “FinFET Scaling to 10 nm Gate Length,” IEDM Tech. Dig., 2002, pp. 251-254.

[3] F.-L. Yang, et al, “25 nm CMOS Omega FETs,” IEDM Tech. Dig., 2002, pp. 255-258.

[4] Y.-K. Choi, et al, “FinFET Process Refinements for Improved Mobility and Gate Work Function Engineering,” IEDM Tech. Dig., 2002, pp. 259-262.

Documents

Szu-Wei Huang, C-V Lab, GIEE of NTU 1 黃 思 維 F90943078 Graduate Institute of Electronics Engineering National Taiwan University Advanced Multi-Gate Technologies

Szu-Wei Huang, C-V Lab, GIEE of NTU 1 黃思維 F90943078 Graduate Institute of Electronics Engineering National Taiwan University Advanced Multi-Gate Technologies