SystemVerilog for Verification Student Workbook · Table of Contents SystemVerilog for Verification II System Tasks to Print Messages

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SystemVerilog UVM

Student Workbook

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Table of Contents

SystemVerilog UVM I

Module 1: Course Overview ................................................................................. 13

Objectives ........................................................................................................................................... 14

Why Learn UVM? .............................................................................................................................. 15

How This Course Makes Sense of UVM ........................................................................................... 16

Course Flow ....................................................................................................................................... 17

Introductions and Expectations .......................................................................................................... 18

Course Labs ........................................................................................................................................ 19

Examples & Labs Emphasize Scalable Best Practices ....................................................................... 20

Module 2: First Look At SystemVerilog UVM ................................................... 21

Objectives ........................................................................................................................................... 22

Course Glossary ................................................................................................................................. 23

Verification Methodologies ................................................................................................................ 24

What is UVM? ................................................................................................................................... 25

UVM Evolution .................................................................................................................................. 26

UVM as a Complete Methodology .................................................................................................... 27

What UVM Provides .......................................................................................................................... 28

SystemVerilog OOP Techniques in UVM ......................................................................................... 30

UVM Topology .................................................................................................................................. 31

Agent .................................................................................................................................................. 32

Class Hierarchy in UVM .................................................................................................................... 33

UVM Reporting/Messaging ............................................................................................................... 34

Verification Phases ............................................................................................................................. 35

UVM Phases ....................................................................................................................................... 36

Hello World Example ......................................................................................................................... 38

Table of Contents

SystemVerilog UVM II

UVM Overview Example ................................................................................................................... 39

Simple Transaction ............................................................................................................................. 40

Simple Driver ..................................................................................................................................... 41

Generating Stimulus ........................................................................................................................... 42

An Agent Bundles Protocol Classes ................................................................................................... 43

Testbench Environment ...................................................................................................................... 44

Test Class ........................................................................................................................................... 45

Packages ............................................................................................................................................. 46

Running the Test ................................................................................................................................ 47

Connecting Testbench and DUT: Dual Top ....................................................................................... 48

Knowledge Check .............................................................................................................................. 49

Configuration Classes ........................................................................................................................ 50

The UVM Factory .............................................................................................................................. 51

UVM Factory Introduction ................................................................................................................. 52

Viewing Topology .............................................................................................................................. 53

Printing Messages in UVM ................................................................................................................ 54

Message Verbosity ............................................................................................................................. 55

Message Tips ...................................................................................................................................... 56

UVM Source Code and Documentation ............................................................................................. 57

Debugging UVM Testbenches ........................................................................................................... 58

Learning UVM ................................................................................................................................... 59

Module 2 Lab: UVM First Look ........................................................................................................ 60

Questa SIM 10.7 Quick Guide ........................................................................................................... 61

Lab Instructions .................................................................................................................................. 63

Description of Lab Environment ........................................................................................................ 64

Table of Contents

SystemVerilog UVM III

Knowledge Check Answers ............................................................................................................... 70

Supplemental Information .................................................................................................................. 71

UVM Reporting .................................................................................................................................. 72

Module 3: Transactions and Sequences .............................................................. 77

Objectives ........................................................................................................................................... 78

Transactions and Sequences ............................................................................................................... 79

UVM Terminology and Class Hierarchy ........................................................................................... 80

UVM Stimulus Built From Sequence Items ...................................................................................... 81

What's Inside Your Transaction? ....................................................................................................... 82

Sequence Item Coding Styles ............................................................................................................. 83

Transaction Methods .......................................................................................................................... 84

Each Transaction Method Calls a Virtual Method ............................................................................. 85

Implementing the Transaction do_*() Methods ................................................................................. 87

The do_copy() Method ....................................................................................................................... 88

The do_compare() Method ................................................................................................................. 89

The convert2string() Method ............................................................................................................. 90

The do_print() Method ....................................................................................................................... 91

Pack, Unpack, Record ........................................................................................................................ 92

Extended Transaction Classes ............................................................................................................ 93

Best Practices with do_* Methods ..................................................................................................... 94

Knowledge Check - Transactions ...................................................................................................... 95

Building Stimulus From Transactions ................................................................................................ 96

UVM Sequences ................................................................................................................................. 97

Handshaking Between Test/Sequence/Driver .................................................................................... 98

Generating Multiple Transactions ...................................................................................................... 99

Table of Contents

SystemVerilog UVM IV

Complex Sequences ......................................................................................................................... 100

Knowledge Check - Sequences ........................................................................................................ 101

Module 3 Lab: Define Transactions and Sequences ........................................................................ 102

Lab Instructions ................................................................................................................................ 103

Knowledge Check Answers - Transactions ..................................................................................... 107

Knowledge Check Answers - Sequences ......................................................................................... 108

Supplemental Information ................................................................................................................ 109

Review: SystemVerilog Class Randomization ................................................................................ 110

Review: SystemVerilog Constraints ................................................................................................ 111

Randomized Sequences .................................................................................................................... 112

Each Transaction Method Calls Two Virtual Methods .................................................................... 113

Macros – When You Want It Now ................................................................................................... 114

Common `uvm_field_* Macros ....................................................................................................... 115

Field Macro Control Flags ............................................................................................................... 116

Module 4: Sequencers, Drivers, and TLM ........................................................ 117

Objectives ......................................................................................................................................... 118

Communication Between Components ............................................................................................ 119

Associating a Sequence With a Sequencer ...................................................................................... 120

TLM Communication ....................................................................................................................... 122

TLM Pull Port Flow ......................................................................................................................... 123

Sequencers, Drivers and Interfaces .................................................................................................. 124

Review: SystemVerilog Interfaces ................................................................................................... 125

The Role of Sequencers and Drivers ................................................................................................ 126

Example UVM Driver ...................................................................................................................... 127

Connecting the Driver and Sequencer .............................................................................................. 128

Table of Contents

SystemVerilog UVM V

Emulation Friendly Drivers .............................................................................................................. 129

Handshaking Between Test/Sequence/Driver .................................................................................. 131

Knowledge Check ............................................................................................................................ 132

Module 4 Lab: Define a Sequencer and Driver ................................................................................ 133


Knowledge Check Answers ............................................................................................................. 136

Module 5: Monitors and Agents ........................................................................ 137

Objectives ......................................................................................................................................... 138

UVM Monitors ................................................................................................................................. 139

Monitoring Ins and Outs .................................................................................................................. 140

Capturing Scoreboard and Coverage Collector Values .................................................................... 141

Communication Between Components ............................................................................................ 142

TLM Analysis Port Flow .................................................................................................................. 143

Monitor Example .............................................................................................................................. 144

Whose write() Method? .................................................................................................................... 146

UVM Agents .................................................................................................................................... 147

Multiple Agents ................................................................................................................................ 148

Active and Passive Agents ............................................................................................................... 149

UVM Testbench With Active and Passive Agents .......................................................................... 150

Analysis Port Connections ............................................................................................................... 151

Example: Analysis Ports .................................................................................................................. 152

Knowledge Check ............................................................................................................................ 154

Module 5 Lab: Monitors and Agents ............................................................................................... 155



Table of Contents

SystemVerilog UVM VI

Module 6: Coverage Collectors .......................................................................... 159

Objectives ......................................................................................................................................... 160

Review: SystemVerilog Functional Coverage ................................................................................. 161

Project Coverage Flow ..................................................................................................................... 166

Covering Transactions ...................................................................................................................... 167

UVM Coverage ................................................................................................................................ 168

What Should be Covered? ................................................................................................................ 169

Coverage Collector Example ........................................................................................................... 170

Connecting the Coverage Collector ................................................................................................. 172

Debugging Coverage ........................................................................................................................ 173

Knowledge Check ............................................................................................................................ 174

Module 6 Lab: Define a UVM Coverage Collector ......................................................................... 175



Module 7: Scoreboards and Environments ...................................................... 179

Objectives ......................................................................................................................................... 180

Introduction to Scoreboards ............................................................................................................. 181

Scoreboard Progression .................................................................................................................... 182

Scoreboard Storage .......................................................................................................................... 183

Clone On Write (COW) ................................................................................................................... 184

Scoreboard TLM Communication ................................................................................................... 185

Two UVM Scoreboard Examples .................................................................................................... 186

Ex1: ALU Predictor, Internal to Scoreboard .................................................................................... 187

Ex1: Evaluator for the ALU with FIFO Ports for Storage ............................................................... 188

Ex1: Scoreboard for the ALU example ............................................................................................ 190

Table of Contents

SystemVerilog UVM VII

Ex1: Environment for the ALU example ......................................................................................... 191

Ex2: Scoreboard with Multiple Analysis Imp Exports .................................................................... 192

UVM Environments ......................................................................................................................... 196

An Example UVM Environment ...................................................................................................... 197

Knowledge Check ............................................................................................................................ 198

Module 7 Lab: Scoreboards and Environments ............................................................................... 199

Lab Diagram ..................................................................................................................................... 200



Module 8: Configuration and Factory .............................................................. 203

Objectives ......................................................................................................................................... 204

Configurable Test Environments ..................................................................................................... 205

UVM Phase Method Order .............................................................................................................. 206

Passing Information Across the Topology ....................................................................................... 207

The UVM Configuration Database .................................................................................................. 208

UVM Configuration Database Example .......................................................................................... 210

Configuration Class Example ........................................................................................................... 211

Configuration Object Flow ............................................................................................................... 213

Setting Configuration from Command Line .................................................................................... 218

Component Arrays ........................................................................................................................... 219

Performance Considerations ............................................................................................................ 220

Configuring Sequences .................................................................................................................... 221

Debugging UVM Configuration Database ....................................................................................... 222

UVM Factory Introduction ............................................................................................................... 223

Creating Objects With the Factory ................................................................................................... 224

Table of Contents

SystemVerilog UVM VIII

Registering Classes in the Factory ................................................................................................... 225

Factory Override .............................................................................................................................. 226

The Benefits of Factory Overrides ................................................................................................... 229

Module 8 Lab: Configuration and Factory ....................................................................................... 230



The UVM Configuration Database Priority ..................................................................................... 235

UVM Config DB exists() and wait_modified() Methods ................................................................ 236

Configuring Sequences Without Referring to a Sequencer ............................................................. 237

Viewing the Configuration Database Contents ................................................................................ 238

Controlling Tests From the Command Line .................................................................................... 239

Printing the Factory Contents ........................................................................................................... 240

Module 9: Tests and Virtual Sequences ............................................................ 241

Objectives ......................................................................................................................................... 242

UVM Test Class ............................................................................................................................... 243

Project-Level Base Classes .............................................................................................................. 245

UVM Test Class Example Code ...................................................................................................... 247

Acquiring a Sequencer Handle for a Sequence ................................................................................ 248

Sequencer Handle in a Configuration Object ................................................................................... 249

Delaying the End of Run Phase ........................................................................................................ 253

Knowledge Check 1 ......................................................................................................................... 256

Controlling Multiple Sequences ....................................................................................................... 257

Virtual Sequences and Running Multiple Sequences ...................................................................... 258

Configuration Objects in the Virtual Sequence ................................................................................ 259

Project-Level Base Classes .............................................................................................................. 260

Table of Contents

SystemVerilog UVM IX

Knowledge Check 2 ......................................................................................................................... 261

Module 9 Lab: Tests, and Virtual Sequences ................................................................................... 262


Knowledge Check Answers 1 .......................................................................................................... 265

Knowledge Check Answers 2 .......................................................................................................... 266


Sequencer Handle Connection Approaches ..................................................................................... 268

Sequence Handle Declarations ......................................................................................................... 272

Sequencer Example – The Environment .......................................................................................... 273

Virtual Sequencer Example – The Virtual Sequence ....................................................................... 274

Virtual Sequencer Example – The Test ............................................................................................ 275

Module 10: Sequences for Complex Stimulus .................................................. 277

Objectives ......................................................................................................................................... 278

Multiple Agents and Sequencers ...................................................................................................... 279

Virtual Sequence Starts Sequences on Both Agents ........................................................................ 280

A Virtual Sequence for Multiple Agents .......................................................................................... 281

Passing Information Into a Sequence ............................................................................................... 282

Parallel Multiple Sequences on the Same Sequencer ....................................................................... 284

Sequencer Arbitration ...................................................................................................................... 285

Setting the Arbitration Algorithm .................................................................................................... 286

Setting Sequence Priority ................................................................................................................. 287

Exclusive Sequencer Access ............................................................................................................ 288

Parallel Sequence Gotchas ............................................................................................................... 289

Sequence Libraries and Hierarchical (Layered) Sequences ............................................................. 290

Driver/Sequence: get_next_item() and get() .................................................................................... 291

Table of Contents

SystemVerilog UVM X

Feedback to Sequence: Shared Transaction Object ......................................................................... 292

Feedback to Sequence: Separate Response ...................................................................................... 293

Knowledge Check ............................................................................................................................ 294

Module 10 Lab: Sequences for Complex Stimulus .......................................................................... 295



Feedback to Sequence: Driver Analysis Port ................................................................................... 298

Sequence Macros .............................................................................................................................. 299

Module 11: UVM Register Layer Overview ..................................................... 301

Objectives ......................................................................................................................................... 302

Advantages of the UVM Register Layer .......................................................................................... 303

UVM Register Layer Components ................................................................................................... 305

UVM Register Model ....................................................................................................................... 306

UVM Register Models Working with Bus Agents .......................................................................... 307

UVM Register Model Hierarchy ...................................................................................................... 308

Software Tools Generate UVM Register Models ............................................................................ 309

Register Model Integration ............................................................................................................... 310

Register Adapter ............................................................................................................................... 311

UVM Register Values ...................................................................................................................... 312

Register Prediction ........................................................................................................................... 313

Adding a Register Model to a Test ................................................................................................... 314

Integrating a Register Model ............................................................................................................ 315

User-defined Register Tests (Sequences) ......................................................................................... 317

UVM Register Access Methods ....................................................................................................... 318

Tests with User Defined Register Sequences ................................................................................... 320

Table of Contents

SystemVerilog UVM XI

Predefined Register Test Sequences ................................................................................................ 321

Test for a Predefined Register Sequence .......................................................................................... 322

Knowledge Check ............................................................................................................................ 323

Module 11 Lab: UVM Register Layer ............................................................................................. 324




Example: Generated Register ........................................................................................................... 328

Example: Generated Register Block ................................................................................................ 329

Module 12: UVM Summary ............................................................................... 331

Objectives ......................................................................................................................................... 332

What is the Other 97% ..................................................................................................................... 333

Advanced UVM Techniques ............................................................................................................ 334

Documents

SystemVerilog for Verification Student Workbook · Table of Contents SystemVerilog for Verification II System Tasks to Print Messages