Verification Presentation to SystemVerilog Basic Committee Peter Flake Nov 15, 2002

Ver

ifica

tion Presentation to

SystemVerilog Basic Committee Peter FlakeNov 15, 2002

© 2002 Synopsys, Inc. (2) CONFIDENTIAL

Agenda AM

• Interfaces

• Instantiation syntax

• Logic type

• Type use before definition


Interfaces

• Fundamental idea Modules encapsulate behavior Interfaces encapsulate communication

• Structural communication Named bundles of wires

• Procedural communication Prototype tasks and functions


Structural Communication

• Wires in interface default to inout

• Need to specify direction for documentation, linting, synthesis QOR

• So introduce modports refer to names in enclosing interface


Procedural Communication

• Point to point messages process in one module calls a task in another

• Needs hierarchical name - hard to maintain and re-use

• Interface prototype means name is local to module import to calling module export from called module


Broadcast Messages

• One module sends a message and does not know how many receive it

• forkjoin task

• Allows address to be coded in receiver module - correct encapsulation

• Allows registration of receivers e.g. count

• No slower than fork join and task call


Slippery Slope

• How about being able to translate task calls to values on wires?

• Put in tasks and continuous assignment No new scheduling semantics

• How about being able to translate signals to task calls, and check bus activity?

• Put in always blocks


Conclusion

• Interfaces are not modules The design intent is connectivity, checkers,

testbench They synthesize to P&R wires, not logic blocks

• Interfaces are not structures Interfaces are static objects, never automatic Interfaces can contain wires and modports Interfaces can contain always blocks


Instantiation Syntax

• Parentheses requiredmoduleType instance ( );interfaceType instance ( );


Logic Type

• Two basic communication mechanisms Resolved drivers - Verilog wire or VHDL signal Shared variable - last write wins

• Verilog reg is a mixture (legacy) Shared variable inside module Gets converted to a wire through a port

• Reals and 2 state variables (e.g. bit) must be shared

• Useful to have a 4 valued data type that behaves like a shared variable through ports

• Must not be driven with strengths


Type Use Before Definition

• typedef foo;

• Minor convenience in SV 3.0 allows less attention to file order

• Type checking must be at elaboration time anyway parameters, generate

• Essential with classes in Testbench donation


Agenda PM

• Time precision and time scale• Time data type• Typedef syntax• Strings as array and structure literals• Unions and 4 state members• Masked and unmasked• Short real to 32 bits• Constants• always_comb• Increment and decrement


Time Precision and Time Scale

• For $root, use timeunit & timeprecision as first thing in source.

• `timescale does not affect $root

• timeunit & timeprecision override `timescale in their module or interface definition

• `timescale applies to any subsequent module or interface


Time Data Type

• Time variable is a logic [63:0] for backward compatibility

• Time literal is 3.4ns

• Time literals can be considered as floating point numbers scaled to the current time unit

• When passed as a parameter the floating point number may have to be re-scaled

• When used in an expression the number is rounded to the current time precision

• Only operators that are valid for reals can be used with time literals


Typedef Syntax

• ?


Strings as Array and Structure Literals

• A structure member or an array element should behave like a scalar of the same type

• A shortreal can be set to a real literalshortreal a = 4.5

• An array can be set to a string


Unions and 4 State Members

• If a union contains a 2 state member and a 4 state member, the union is 4 state

• If the 2 state member is written and then the 4 state member is read, there is no Z or X

• Like assigment var4state = var2state


Masked and Unmasked

• Masked and unmasked are the terms in the Superlog manual and in the Co-Design donation

• They were changed to 4 state and 2 state by the Accellera committee

• Some changes were missed


Short Real to 32 Bits

• Real and short real should be cast to integer or 32 bits with rounding

• To get same bit pattern use union (like C)


Constants

• A parameter or localparam can only be set to an expression of literals, parameters or local parameters, or a constant function of these

• A const in a static scope can also be set to an expression containing a hierarchical name

• A const in an automatic scope can also be set to an expression containing arguments


always_comb

• Used to model combinational logic indicates design intent execution at time 0 is guaranteed unlike @*

• Cannot drive from anywhere else - no resolution

• Functions can be used to partition the combinational logic & so add to sensitivity useful with large case statement

• No timing or event controls should be allowed


always_comb continued

• Sensitivity list should be like @* with functions inlined

• Static function locals should be treated like static variables in modules


Increment and Decrement

• Consider int i = 1; $display( "%d %d %d %d %d %d",

i++, i++, ++i, --i, i--, i-- );

• Current implementation gives 1 2 4 3 3 2

• Alternative is to limit to only one per variable per statement like C

Documents

Verification Presentation to SystemVerilog Basic Committee Peter Flake Nov 15, 2002