IEEE TRANSACTIONS ON COMPUTERS, VOL. C-22, NO. 5, MAY 1973

Synthesis of Diagnosable FET Networks

MICHAEL R. PAIGE

Abstract-With the advent of field-effect transistor (FET) technologyit has become practical and economical to employ complex functions asnetwork primitives. This paper describes a synthesis procedure fordiagnosable (all single and multiple faults can be detected) FET net-works. A companion procedure for generating tests to detect all faultsin the resulting network is also described. This methodology does notguarantee the minimality of the network, however, it is intuitivelyunderstandable and easy to apply.

Index Terns-Fault diagnosis, FET network, irredundant function,network synthesis, single and multiple faults.

INTRODUCTIONT HE concept of carrying out a hardware design without a

conscious effort to incorporate diagnostic capability intothe unit is not only costly in terms of the results of undetect-able faults that may arise, but may also be costly in terms cYfthe time that is spent in deriving fault tests, which, in turn,may be incomplete. Therefore, it is suggested that diagnosisshould be very much of a design issue.Up to quite recently, simple logic gates (OR, AND, NOR, and

NAND) have been used to implement Boolean functions. Withthe advent of field-effect transistor (FET) technology it hasbecome both practical and economical to employ more com-plex functions as network primitives. The manner in whichfunctions are realized by FET devices is similar to contact net-works seen in the early stages of switching theory.

Ibaraki and Muroga [2] have developed an algorithm for de-signing switching networks using only gates that representcomplex functions. The word "gate" in this context refers notto a single FET device but, rather, to the combination of de-vices that produce a given function; hence "gate" is closer tothe word "module." This paper will consider the synthesis ofdiagnosable FET networks using a procedure that is an adapta-tion of the work of Ibaraki and Muroga. The networks thatwill be constructed, however, are done so with the aim ofsimplifying the diagnosis problem and not, necessarily, guaran-teeing minimality. The design is intended to be coinpletelydiagnosable, that is, all single and multiple faults can be de-tected. An easy and efficient procedure for generating a suffi-cient set of fault-detection tests for the network is alsopresented.

Manuscript received March 13, 1972; revised November 9, 1972.This work was supported in part by the Joint Services Electronics Pro-gram under Contract DAAB-67-C-0199 and in part by the Interna-tional Business Machines Corporation. Portions of this paper were pre-sented as a Short Note at the 1971 Spring Joint Computer Conferencein conjunction with Prof. G. Metze, Coordinated Science Laboratory,University of Illinois, Urbana-Champaign, Ill.The author was with the Coordinated Science Laboratory, University

of Illinois, Urbana-Champaign, Ill. He is now with General ResearchCorporation, Santa Barbara, Calif. 93105.

SYNTHESIS OF FET NETWORKSIt has been shown [2] that a function F(x) is negative if

there is no pair of comparable vectors Xi and Xi such thatXi > Xi, and, F(X1) = 1 and F(Xj) = 0. For example, the func-tiOn F(X1, X2, X3) represented by its truth table in Table I isnot a negative function since (100) > (000), and, F(100) = 1and F(OOO) = 0.The FET module shown in Fig. 1 will be used as the primi-

tive for the networks to be synthesized. The function G(X) inthe figure is formed by the contact-like network of FET's.The output function F(X) would be equal to G(X) and isformed by an auxiliary FET that is also used to create theproper loading capabilities for the module.Without loss of generality it will be assumed that the output

function to be realized is given in the following form:

F(X) = G(X) = PI (X) + P2(X) + * - - + Pn(X) (1)where G(X) is irredundant, and each Pi(X) is a product term.It is obvious that each product term Pi(X) in (1) can be dividedinto two factors: a positive product term Pi(X) and a negativeproduct term Pi'(X). Either Pi(X) or P7 (X) can be equal to 1.For the function given by Table I, for example, the follow-

ing representation can be made:

F(X)=G(X)=x1x3 +x1x2 +x1x2x3where P1 (X) =x1x3, P2 (X) = x 1 x2, and P3 (X) = X IX2X3.The first step in the synthesis procedure is to generate a

function Li(X) for each Pi(X) such that we have the following.Rule 1: For each vector Xt such that Pl(Xt) = 1 set Li(Xt) =

Pilet).Rule 2: If Li(Xk) = 0 then for all vectors Xt such that

Xk > Xt, set Li(Xt) = 1.Rule 3: If Li(Xk) = O then for all vectors Xt such that

Xt > Xk, set Li(Xt) = 0.Rules 2 and 3 are included so that Li(X) will be a negative

function. The auxiliary function Li(X) for the product termsin the example are shown in Table I. Note that entries thatcould not be filled using Rule 1 are filled using Rules 2 and 3wherever possible. DONT CARE entries emerge due to nonap-plicability of the above rules. It is straightforward to demon-strate that replacing each Pi'(X) by its respective Li(X) func-tion does not change G(X) (or F(X)).The second step in the procedure is to merge the Li(X) func-

tions wherever possible using the DON'T CARE positions. Inthis manner one L1(X) function can fulfill the requirements (ifpossible) of several others.There are several well-known tabular methods for combining

the above type of function (such as Quine-McCluskey [6] andso they will not be discussed here further. It should suffice to

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IEEE TRANSACTIONS ON COMPUTERS, MAY 1973

TABLE ITRUTH TABLE AND FUNCTIONS FOR EXAMPLE

XI X2 X3 I F(X) G(X) L1(X) L2(X) L3(X)1L2/3(X)

0

1

0

0

1

0

1

1

0

1

I

0

1

0

0

0

1

0

0

0

0

0

1

1

1

1

1

1

o 1

- 1

0 -

o o

+ + 774L C F ( X) = G X

I NVERTINGDRIVER

6 ( x ) i CONTACT-LII

Fig. G1.FETmodulNETWORK

Fig. 1. FET module (primitive).

1

1

1

1

1

1

0

0

KE

state that the Li(X) functions should be combined whereverpossible to reduce both the functional and (eventually) thehardware complexity. The functions L2(X) and L3(X) inFig. 1, for example, can be combined into a single compositefunction that will be termedL2/3(X). Note that the combinedfunctions are still negative. It is straightforward to prove thatthese composite functions are, or can be made into (by fillingin DON'T CAREs) negative functions.The final step in this procedure is actually the network con-

struction. Each Pi(X), i = 1, 2, , n, of G(X) from (1) isrealized by a series connection of FET's where each factor ofPi(X), given by xi1, xi2, * * *, Xik, Lilj(X), is an input to a sep-

arate device. Each of these connections is made in parallel toform the logical OR of all the Pi(X). Modules on the secondlevel are implemented along similar lines; except that their in-puts will be primary variables only. The completed networkfor the example function is given in Fig. 2.

FAULT DETECTIONThe operation of FET devices suggests an obvious fault

model. The failure mode for all permanent faults is the devicestuck-at-short or stuck-at-open. Since the control lead is theaccess point to the device, these faults are represented by thecontrol lead permanently stuck-at-I or stuck-at-O, respectively.This model has been substantiated by engineering analysis [5] .

The following definition will be useful in diagnosing FETnetworks.A network is irredundant if the output function of the net-

work expanded into sum-of-products form, that is,

G(x) = PI (x) + P2 (x) + +Pn(x)where Pi(x) is a product term and has the following properties.

Property 2: PL(x) iLP,(x) for i Vzj.

Property 3: No literal or combination of literals can be re-

moved from any Pi(x) without changing the function.

A binary vector representation for each product termPi(x) ofG(x) will be used to simplify the test-generation procedure.

We assume that there are k input lines to the network as

shown in Fig. 1, and thus all vectors will be of length k. For a

given Pi(x), a characteristic vector denoted by C1 is formed,

o 0 0

o o 1

o 1 0

o 1 1

1 0 0

1 0 1

1 1 0

1 1 1

x1x2.

Xk-

514

PAIGE: FET NETWORKS

where Ci = (Cil, Ci2, * * *, Cik) and ci1 = 1 if and only if Xirepresenting the input line j is a factor in Pi(x), and ci1 = 0otherwise with i = 1,2, , n,j= 1, 2,-, k.For example, the output function of the first-level module in

Fig. 2 would be

F(X) = G(X) = L (X) +L23(X)X2 + L2/3(X)X1X3.The C-vectors of G(X) would be

C1 = (10000)C2 = (01010)C3 = (01 101)

where the variables are, respectively, L1 (X), L213(X), X1, X2,X3, as input lines xi, j = 1, 2, * , 5 to the network given byFig. 2.Forming the C-vectors as mentioned above, it is not difficult

to see that for a given G(X), G(C,) = 1. Hence the vectors Ci,i = 1, 2, 3, may be defined as the true vectors of the functionG(X).We also form a set of vectors from these C-vectors, which we

will call single-change vectors, denoted by Si. The S-vectorsare formed by sequentially replacing each 1, one at a time inthe C-vector by a 0 and leaving the rest of the binary digits un-changed. Thus, each C-vector generates as many S-vectors asthe number of l's it contains. For example, Ci = (010001)generates two S-vectors, (000001) and (010000). For con-venience these S-vectors will be subscripted from 1 to m,where m is the total number of 1's in the C-vectors.We have already seen that the C-vectors are true vectors for

G(X); the following result establishes the use of the S-vectors.If G(X) = P1 (x) + P2(x) + - - * + P, (x) is a positive irredun-

dant function, then no S-vector is a true vector of G(X).(G(Si) = 0 for all i.) To show this if G(x) is a positive function,then a given S-vector, if it were a true vector, would be a truevector of a positive-product term. This product term becauseof the construction of the S-vectors from the C-vectors [hencefrom a product term already in G(X)] would necessarily in-clude one of the original product terms. Hence an S-vectorcannot be a true vector of any product term in G(x), since thiswould contradict the irredundancy of G(x). Therefore, noS-vector is a true vector of G(x).

It has been recognized that if a network is irredundant thenthere exists a single fault test set that detects all multiplefaults. Using the FET fault model described earlier, it is obvi-ous that each network fault is represented by a set of inputconditions to various network elements. Hence each fault cor-responds to some logical change in the output function.Each single fault in an irredundant network corresponds to

a change in one or more product terms of the output function.We can characterize these changes in each product term as oneof two types [3], [4].Condition 1: The product term becomes a logical O.1Condition 2: The product term becomes independent of a

single input variable, that is, that variable is not represented inthe new product term.

The path that corresponds to that variable becomes disabled.

If Condition 1 exists then the C-vector for that product termrepresents a test for it, since this vector gives the output 1 ifand only if that product term is present. If Condition 2 existsthen a new product term is formed from a given term, that is,a new product term is formed that represents the original termindependent of a given variable. The S-vectors are the truevectors of all such possible new product terms, hence theS-vectors will not give the output 0 for F(x) if one of thesenew product terms exists; thus the S-vectors represent tests forCondition 2. Hence, the test set made up of C- and S-vectorswill detect all multiple faults in an irredundant network.The first-level module in Fig. 2, which has previously been

discussed, would have the following set of tests:

C-vectors: (10000) (01010) (01101)

and corresponding

S-vectors: (00000) (00010) (00101)(0100

(O1000) (O 1 Oj

These nine tests detect all single and multipleFET module. This at the best constitutes a reover the total number of input combinations.tion can be made on the number of S-vectors, Si;binations are allowed; however, these procedtiXsome and involve some bookkeeping [4].This procedure would have to be carried ou fi -.l

modules in the network, and would necessariXlk,sertion of test points to gain access to input v -lv-put values from/to the first level of gates. Aamount of computer simulation run time cantwo stages are isolated from each other and ,tions of C and S test sequences are applied s-PKt!presponding levels to detect single and multiple

CONCLUSIONThe procedtile for synthesis of FET networks

presented has one particular failing, and that is, 1''.no way of predicting when the second level of moduI -dused for complimentation of single variables oniZ.'tion could be foretold then the synthesis proceL-,,ssceed directly to that realization without undue cae,lud.i j',The test-generation procedure has an equal failii

necessitates the insertion for test points. It is the feii-,author that it may be possible to constraint kte;1realizations so as to make insertion of auxiliary pirn.s: i,,-Fsary without reducing the network to the trivial c"ae ."-ithe second level of modules is for complementatio- (1Both of the above weaknesses will hopefully be re-"-

future work.Aside from the above discussion, the techniques Wiat ,ha'

been presented should prove both straightforward an e -employ.

AcKNOWLEDGMENTThe author has enjoyed the privilege of being a gr-, ->a,..-

student of Prof. G. Metze at the University of Illinois., ..1'1i ,

515

IEEE TRANSACTIONS ON COMPUTERS, VOL. C-22, NO. 5, MAY 1973

Champaign. His guidance, and suggestions were invaluable inthe research described here. Sincere thanks are also due to themembers of the Switching Systems Group at the CoordinatedScience Laboratory and particularly to Dr. A. Wojcik andDr. D. Anderson.

REFERENCES

[1] H. Chang, E. Manning, and G. Metze, Fault Diagnosis of DigitalSystems. New York: Wiley-Interscience, 1970.

[2] T. Ibaraki and S. Muroga, "Synthesis of networks with a minimumnumber of negative gates," IEEE Trans. Comput., vol. C-20,pp. 49-58, Jan. 1971.

[3] M. Paige, "Generation of diagnostic tests using prime implicants,"Coord. Sci. Lab., Univ. Illinois, Urbana-Champaign, Rep. R-414(CFSTI AD 688 832), May 1969.

[4] -, "On the design of diagnosable combinational networks," Co-ord. Sci. Lab., Univ. Illinois, Urbana-Champaign, Rep. R-519,July 1971.

[5] G. L. Schnable and R. S. Keen, Jr., "Failure mechanisms in large-scale integrated circuits," IEEE Trans. Electron Devices, vol.ED-16, pp. 322-332, Apr. 1969.

[6] E. McCluskey, Introduction to the Theory of Switching Func-tions. New York: McGraw-Hill, 1965, pp. 140-143.

Michael R. Paige (S'66-M'68) was born inWorcester, Mass., on January 11, 1946. He re-ceived the B.S. degree in electrical engineeringfrom Worcester Polytechnic Institute, Worcester,Mass., in 1968, and the M.S. and Ph.D. degreesin electrical engineering from the University ofIllinois, Urbana-Champaign, in 1969 and 1971,respectively.From 1968 to 1969 he was awarded a fellow-

ship for study at the University of Illinois,Urbana-Champaign. From 1969 to 1971 he

held a Research Assistantship with the Coordinated Science Laboratoryat the University of Illinois, engaging in the study of fault diagnosis andthe design of diagnosable logic. He spent the summer semester of 1969at the Advanced Systems Development Division of IBM, Los Gatos,Calif., where he engaged in the development of a computer-aided com-puter design system. In 1971 he joined General Research Corporation,Santa Barbara, Calif., where he is presently conducting research on soft-ware reliability and testing, with emphasis on automated analysis tools;and on the design of programming languages to simplify testing. He hasalso engaged in studies of special-purpose advanced machine architec-tures. He is also a Lecturer in the Department of Electrical Engineeringat the University of California, Santa Barbara.

Dr. Paige is a member of Eta Kappa Nu, Pi Mu Epsilon, and Tau BetaPi.

Dynamic Programming for the Partitioningof Numerical Simulations with Hybrid

Computer ApplicationsJAMES R. ROWLAND AND WILLARD M. HOLMES

Abstract-The principle of dynamic programming is used to develop adigital computer software package for determining for each of severalsubsystems the optimal numerical integration algorithm from amonggiven candidate techniques. As by-products, the corresponding optimalstep sizes and error contributions of the subsystems are provided to theuser. The deveiloped program minimizes subsystem sum-squared errorssubject to the constraint that the total time available for executing allsubsystem integrations is specified in advance. After the basic conceptof dynamic programming has been reviewed briefly, the details of thecomputer software package are presented. Numerical results are givenfor two examples, including a limited hybrid partitioning problem fora six-degree-of-freedom air-defense missile simulation. Finally, general

Manuscript received September 27, 1971; revised June 5, 1972. Thiswork was performed in the Guidance and Control Directorate of theResearch, Development, Engineering and Missile Systems Laboratory,U.S. Army Missile Command, Redstone Arsenal, Ala., under the ARO/DArmy Laboratory Research Cooperative Program, Contract DAHC04-68-C-001 1.

J. R. Rowland was with the School of Electrical Engineering, GeorgiaInstitute of Technology, Atlanta, Ga. He is now with the School ofElectrical Engineering and Center for Systems Science, Oklahoma StateUniversity, Stillwater, Okla. 74074.W. M. Holmes is with the Guidance and Control Directorate (AMSMI-

RGN), Research, Development, Engineering and Missile Systems Labora-tory, U.S. Army Missile Command, Redstone Arsenal, Ala. 35809, onleave at Oklahoma State University, Stillwater, Okla. 74074.

considerations for hybrid partitioning are discussed, and extensions tothe developed program are suggested.

Index Terms-Digital computer software package, dynamic program-ming, hybrid computer applications, hybrid partitioning, optimal digitalexecution-time allocation, optimal integration intervals, optimal numer-ical integration formulas.

INTRODUCTIONT HE efficient usage of limited computing equipment is es-Tpecially important when the objective is to achieve the

real-time hybrid simulation of a large-scale system on amedium-sized hybrid facility. Partitioning between analog anddigital operations becomes particularly critical in such cases.The usual procedure in hybrid simulation is to perform mostof the algebraic operations on the digital side and all integra-tions on the analog side. However, when analog equipment isseverely limited, e.g., for simulating very large-scale missilesystems on medium-sized facilities, it becomes necessary tonumerically integrate at least a few of the more slowly varyingdifferential equations on the digital side. This paper describes