Switching surge voltage suppression in SiC half-bridge

Switching surge voltagesuppression in SiChalf-bridge module withdouble side conductingceramic substrate andsnubber capacitor

Shuhei Fukunagaa) and Tsuyoshi FunakiOsaka University, Division of Electrical, Electronic and Information Engineering,

Graduate School of Engineering, Suita, Osaka 565–0781, Japan

a) [email protected]

Abstract: Fast switching capability of SiC power devices enables the

downsizing of power conversion circuits by high-frequency switching oper-

ation. However, high di/dt in fast switching operation for high-frequency

switching induces surge voltage. This paper developed low-inductance

power module substrate with snubber capacitor directly attached on the

substrate to suppress surge voltage in fast switching, and validated the

performance of the developed SiC half-bridge power module. The surge

voltage was suppressed less than 1/10 of the conventional power module

configuration for same switching speed.

Keywords: SiC power device, low-inductance ceramic module substrate,

multi-layer ceramic capacitor

Classification: Electron devices, circuits and modules

References

[1] B. Wrzecionko, et al.: “SiC power semiconductors in HEVs: Influence ofjunction temperature on power density, chip utilization and efficiency,”IECON’09, 35th Annual Conference of IEEE (2009) 3834 (DOI: 10.1109/IECON.2009.5415122).

[2] H. Zhang, et al.: “Impact of SiC devices on hybrid electric and plug-in hybridelectric vehicles,” IEEE Trans. Ind. Appl. 47 (2011) 912 (DOI: 10.1109/TIA.2010.2102734).

[3] R. A. Wood, et al.: “Evaluation of a 1200-V, 800-A all-SiC dual module,”IEEE Trans. Power Electron. 26 (2011) 2504 (DOI: 10.1109/TPEL.2011.2108670).

[4] F. Xu, et al.: “Development of a SiC JFET-based six-pack power module fora fully integrated inverter,” IEEE Trans. Power Electron. 28 (2013) 1464 (DOI:10.1109/TPEL.2012.2205946).

[5] M. Alexandru, et al.: “SiC integrated circuit control electronics for high-temperature operation,” IEEE Trans. Ind. Electron. 62 (2015) 3182 (DOI: 10.1109/TIE.2014.2379212).

© IEICE 2017DOI: 10.1587/elex.14.20170177Received February 27, 2017Accepted April 27, 2017Publicized May 15, 2017Copyedited June 10, 2017

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LETTER IEICE Electronics Express, Vol.14, No.11, 1–8

http://dx.doi.org/10.1109/IECON.2009.5415122





http://dx.doi.org/10.1109/TIA.2010.2102734




http://dx.doi.org/10.1109/TPEL.2011.2108670









http://dx.doi.org/10.1109/TIE.2014.2379212




[6] R. Lai, et al.: “A systematic topology evaluation methodology for high-densitythree-phase PWM AC-AC converters,” IEEE Trans. Power Electron. 23 (2008)2665 (DOI: 10.1109/TPEL.2008.2005381).

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[8] M. Hammadi, et al.: “Layout optimization of power modules using asequentially coupled approach,” Int. J. Simul. Model. 10 (2011) 122 (DOI:10.2507/IJSIMM10(3)2.183).

[9] A. S. Bahman, et al.: “Electrical parasitics and thermal modeling for optimizedlayout design of high power SiC modules,” Applied power ElectronicsConference and Exposition (2016) 3012 (DOI: 10.1109/APEC.2016.7468292).

[10] Fairchild Semiconductor Corporation: “Design considerations for high powermodule (HPM),” AN-5077 (2014).

1 Introduction

Wide-bandgap semiconductor, such as silicon carbide (SiC) is superior to Si

semiconductor in terms of bandgap, breakdown electric field and thermal con-

ductivity. These features enable the high voltage unipolar device with low on

resistance, fast switching and high temperature operation. These characteristics are

expected to be utilized in EV/HEV applications [1, 2]. References [3, 4, 5]

developed high power density and high operating temperature SiC modules.

High-Frequency switching operation allows to use less inductance and capaci-

tance in power conversion circuits [6], but high di/dt in fast switching induces

large surge voltage with the parasitic inductance in the circuit wiring. Refer-

ences [7, 8, 9, 10] reported the quantification of parasitic inductance and circuit

design to reduce it.

The parasitic inductance in the wiring of circuit can be reduced by making the

current loop small. The modularization of functional block in the circuit is one way

of reducing parasitic inductance. The multi-layer substrate is the feasible solution

for modularization. A power module requires thick wiring conductor to flow large

current and low thermal resistance for heat dissipation. Then, this paper developed

low-inductance SiC half-bridge module which has low thermal resistance in

insulation layer and large via to flow large current with low resistance in inter-

connecting both side conductor. This multi-layer ceramic substrate topology makes

the high voltage multi-layer ceramic capacitor (MLCC) possible to directly attach

on the module substrate as a snubber capacitor for suppressing surge voltage. The

performance of the developed power module is validated with double pulse test

(DPT). The detail of developed module is shown in section 2. Experimental data

and discussion is described in section 3. The conclusion is provided in section 4.

2 Developed low-inductance SiC half-bridge module

2.1 Structure of developed SiC half-bridge module

The developed ceramic substrate and circuit topology are illustrated as Fig. 1. The

module dimension is 37.2mm � 15.0mm (without lead) � 0.92mm. The insula-


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tion layer is composed of silicon nitride (Si3N4) with 320 µm thickness (Fig. 1(c)),

whose thermal resistance is 9.89K/kW. The thermal resistance from junction to die

attach �JD, and from junction to case �JC are extracted to 0.088K/Wand 0.91K/W,

respectively from the transient thermal measurement based on the static method by

T3Ster (Mentor Graphics) at SiC SBD of low side arm. The Cu plate is brazed with

active metal (AMB) as conduction layer on the both side of insulation layer. The

frontside conductor has wiring pattern as shown in Fig. 1(a). And also, the backside

is used as conductor (Fig. 1(b)). Both side conductors are electrically connected at

terminal M through two �1:8mm vias with Cu cores to flow large current, which is

different from conventional multi-layer ceramic substrate (LTCC). The Cu core is

brazed on both side conductors.

Fig. 1(d) and Fig. 1(e) illustrate the placement of components in half-bridge

module and its equivalent circuit. Each arm consists of one SiC MOSFET (CPM2-

1200-0080B, CREE) and one SiC SBD (CPW4-1200-S020B, CREE) as Free

Wheeling Diode (FWD). Dies are attached with Pb-free solder Sn/0.7Cu/Ni/P

Fig. 1. Developed SiC half-bridge module with double side conductingceramic substrate: the dimension and materials are denoted inFig. 1(a) to Fig. 1(c). Fig. 1(d) is the placement of eachcomponent and Fig. 1(e) is its equivalent circuit.


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and electrically connected with �300µm aluminum bonding wire. They are molded

with epoxy resin, CEL-C-1102NF (Hitachi Chemical).

Two MLCCs (CKG57NX7T2J105M500JJ, 630V, 1 µF, TDK) are attached on

the substrate and connected in series through backside conductor. This configu-

ration gives the electrical potential of backside conductor 1=2Vin (Vin is the input

direct voltage). The capacitance of MLCC has the bias voltage dependency, and the

capacitance for combined snubber MLCC becomes Cs ¼ 0:2244µF for Vin ¼600V. The MLCC snubber capacitance is sufficiently larger than the combined

output capacitance of SiC MOSFET (106.89 pF, 600V) and SiC SBD (80.76 pF,

600V) to feed charge in switching transient.

2.2 Static electrical characteristics

The static electrical characteristics of the developed module are given in Fig. 2.

The current-voltage characteristic of each arm for Vgs ¼ �5V, 20V is shown in

Fig. 2(a). The on resistance Ron in forward conduction is 84.97mΩ and 94.54mΩ

for Vgs ¼ 20V, and threshold gate voltage Vth is 2.38V and 2.19V, respectively for

high and low arm. The reverse conduction current for Vgs ¼ �5V flows through

SiC SBD, and for Vgs ¼ 20V flow through channel of SiC MOSFET in low voltage

drop region.

Fig. 2(b) shows the frequency characteristic of module impedance between N

and P terminal. The solid blue line is measured with shunting all components on the

module substrate by wire bond. The parasitic inductance in the wiring of the

developed module 6.51 nH is extracted from the high frequency region. The dashed

green line is measured with attached snubber MLCC. MLCC on the module gives

three resonance phenomenon. Fig. 2(c) shows the current loop related to the

oscillation phenomena. The series resonance of 2.16MHz occurs for the current

loop given as blue line in Fig. 2(c), where Lsub�1 to �3 are the parasitic inductancesof the backside conduction layer. The parallel resonance of 6.90MHz occurs for the

Fig. 2. Static characteristics of developed SiC half-bridge module.


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current path given as the magenta line in Fig. 2(c), where Csub�1 and �2 are the

parasitic capacitances which originate from double side conduction layer. The

series resonance of 7.89MHz occurs for the current loop given as the green line

in Fig. 2(c). The ESL of snubber capacitor is estimated as 2.43 nH which is

extracted as the difference of the parasitic inductance of the module between solid

blue line and dashed green line in Fig. 2(b). The dashed magenta line in Fig. 2(b)

is measured with power devices and without MLCC in blocking condition by

Vgs ¼ 0V. The combined output parasitic capacitance Coss ¼ 1:53 nF for Vcc ¼0:1V is extracted from the low frequency region. The series resonance frequency of

52.94MHz is attributed to the resonance between the parasitic inductance in the

wiring and the output capacitance. The parasitic inductance of the module substrate

calculated from this frequency and the output capacitance is 5.91 nH. This value

differs to the value from the solid blue line in Fig. 2(b), because the parasitic

inductance in this case relates only to the frontside conductor. The dashed orange

line in Fig. 2(b) is for attached all components in blocking condition by Vgs ¼ 0V.

The resonance frequency 52.94MHz in dashed magenta line in Fig. 2(b) shifts to

75.49MHz in dashed orange line for the parasitic inductance of MLCC.

3 Switching characteristics

3.1 Experimental condition

The switching characteristics of the developed SiC half-bridge module is experi-

mented in DPT with the circuit shown in Fig. 3. Gate and source terminal of high-

side MOSFET is directly connected and SiC SBD is used to flow wheeling current

in this experiment. Supply voltage is Vin ¼ 600V. +20V/−5V is applied to the

gate of low-side SiC MOSFET through gate-driver IC BM6103FV-C (Rohm) as

shown in Fig. 3(c).

Fig. 3. Switching characteristics evaluation.


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3.2 Switching surge voltage for the module without MLCC

The voltage across drain to source of high and low side arm in switching operation

for 18.9A current without MLCC are shown in Fig. 4. The gate resistance Rg is

given as the parameter for regulating switching speed. The relation between Rg and

di/dt in switching operation is linearly approximated as shown in Fig. 4(a). The

significant difference is not found for overshoot voltage in turn-on of high side arm

and turn-off of low side arm with Rg as shown Fig. 4(c) and Fig. 4(e), respectively.

The peak surge voltage in turn-off of high side arm is 898V for Rg ¼ 1Ω as shown

in Fig. 4(d). It has linear relationship with Rg as shown in Fig. 4(b). The negative

peak surge voltage in turn-on of low-side arm −20V for Rg ¼ 10Ω and −118V for

Rg ¼ 1Ω shown in Fig. 4(f ) is deduced as the induction voltage in high voltage

probe.

The oscillation frequency 56.18MHz does not change with Rg, and comparable

for Fig. 4(c), (d), (e) and (f ). The parasitic inductance in the circuit is estimated

from oscillation frequency and Coss ¼ 94:32 pF for Vin ¼ 600V as 88.58 nH. The

parasitic inductance includes the inductance of wiring in half-bridge module and

the wiring from module to the input smoothing capacitor. The parasitic inductance

of wiring to input smoothing capacitor is estimated as 76.15 nH with subtracting the

parasitic inductance of the developed module.

A snubber capacitor embedded in the developed module can eliminate the

influence of the parasitic inductance in the wiring of circuit, which is expected to

restrict the peak surge voltage for Rg ¼ 1Ω as follow:

Fig. 4. Drain-source voltage waveform without MLCC.


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�V ¼ L � di

dt¼ 8:935 ½nH� � 2:860 ½kA=�s� ¼ 25:53 ½V�: ð1Þ

It is noted that di/dt in switching operation for same Rg may differ with the

existence of snubber MLCC stemming from the difference in the inductance to the

same power supply voltage.

3.3 Switching surge voltage for the module with MLCC

Fig. 5 shows the voltage across drain to source of high and low side arm in turn-off

and turn-on switching operation for 18.9A current with MLCC. The gate resistance

Rg is given as the parameter for regulating switching speed. Fig. 5 shows that the

installation of snubber MLCC directly attached on the substrate suppresses surge

voltage and ringing oscillation in switching operation for both side arm to different

di/dt by Rg. The effect is significant in suppressing peak surge voltage for turn-off

operation of high side arm and turn-on operation of low side arm, which becomes

from 898V to 622V and from −118V to −22V, respectively for Rg ¼ 1Ω as

shown in Fig. 5(b) and (d). The estimated peak voltage in turn-off of high side arm

25.53V from Eq. (1) almost coincident with the experimental result �V ¼ 22V.

Thus the effect of eliminating parasitic inductance of developed power module with

snubber MLCC on suppressing surge voltage is validated.

Fig. 6 shows the voltage across drain to source of high and low side arm in

turn-off and turn-on switching operation with MLCC. Where the 1st pulse width

is changed as the parameter to have different amplitude of current in switching

operation. That is, di/dt changes proportionally to current amplitude for same

switching time for the same gate resistance Rg ¼ 1Ω. The drain current of

MOSFETs is not measurable stemming from high density packaging structure,

then he load inductor current is shown in Fig. 6(e) as the reference of device

current. The slope of drain voltage rise and fall shown in Fig. 6(a) and (c) changes

with load current, which stems from charge up of Coss in low side arm MOSFET by

Fig. 5. Drain-source voltage waveform with MLCC.


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load current. The peak surge voltage is effectively suppressed with MLCC snubber

and no significant difference are found for current amplitude.

4 Conclusion

This paper developed low-inductance double side conducting ceramic substrate for

SiC half-bridge module to suppress surge voltage in fast switching operation, and

validated the performance experimentally in DPT. The installation of MLCC

snubber capacitor directly on the module substrate eliminates the parasitic induc-

tance in the wiring of circuit and is effective in switching surge voltage and ringing

oscillation suppression. The developed power module enables to suppress switch-

ing surge voltage with maintaining fast switching of SiC devices.

Acknowledgments

This work was partially supported by Council for Science, Technology and

Innovation (CSTI), Cross-ministerial Strategic Innovation Promotion Program

(SIP), “Next-generation power electronics” (funding agency: NEDO).

Fig. 6. Drain-source voltage waveform with MLCC.


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Switching surge voltage suppression in SiC half-bridge