Switched-capacitor filters - Extra Materialsextras.springer.com/2006/978-0-387-25746-4/Chapter_17.pdf · SC ladder filter. Willy Sansen 10-05 N177 ... Sampled Data Basics : z-transform

Willy Sansen 10-05 N171

Switched-capacitor filters

Willy Sansen

KULeuven, ESAT-MICASLeuven, Belgium

[email protected]


Switched-Capacitor Filters

• Introduction : principle• Technology:

• MOS capacitors• MOST switches

• SC Integrator• SC integrator : Exact transfer function• Stray insensitive integrator• Basic SC-integrator building blocks

• SC Filters : LC ladder / bi-quadratic section• Opamp requirements

• Charge transfer accuracy• Noise

• Switched-current filters McCreary, JSSC Dec 75, 371-379Gregorian, IEEE Proc. Aug 83, 941-986


Principle

φ1φ2

• Non overlapping clocks• Switches are MOSTs

CQ Q

φ1 φ2V1 V2

Iav = =

Iav

C(V1-V2)

Tc = 1/ fc

Qav

Tc Tc

Iav = (V1-V2)

R

R = = Tc

For C = 1 pF & fc = 100 kHz R = 10 MΩ

1

fcCC

I2 Iav

t

t


Low-Pass Filter with R’s and C

+

Av0 =

f-3db =

Ratio’s of R: 0.5% accuracy

R1 R2

C

-

R1

R2

2πR2C1

f-3dB f

Av0

Av

1

-20 dB/dec

Absolute value of RC : 20 % accuracy

vIN vOUT


Low-Pass Filter with switched C’s

+

High accuracy: only ratio’s of C: 0.2%Only capacitors to drive : low power !Tunable & easy to integrate !But : only for frequencies << fc

-1 2

1 2

C

C1

C2R1 R2

C

-

+

Av0 =

f-3db =

C2

C1

2πfc

CC2

vOUTvIN

vOUT

vIN


Example of 4th-Order SC Low-Pass filter

LC proto-type

SC ladder filter


4th-Order SC Low-Pass filter

Capacitors

SwitchesOpamps

Clock










Capacitors: metal-n+ & Metal-poly

Carea ≈ 5 fF/µm2

Cp ≈ 1.2 fF/µm2

Carea / Cp ≈ 1/4• Voltage dependent• Rsub: noise

Carea ≈ 2 fF/µm2

Cp ≈ 1 fF/µm2

Carea / Cp ≈ 1/2

• Linear• Large parasitics: Multi-layer !


Capacitor Matching

Common centroide lay-out !

Constant Area / Perimeter !


Random Error (σ)

1%

σ

Log (C)

local vs global tox effects

0.1%


Capacitances in nanometer CMOS

vias• Digital technology, no MIM cap.• lateral metal-metal capacitance• 8 metal layers, 1.7 fF/μm2

• Good matching

• MIM capacitors• 5 metal layers, 0.35 fF/μm2

• Excellent matching

Aparicio, JSSC March 02, 384-393










A MOST as a switch

1 2

W= 2 µm L = 0.7 µmKPn = 80 µA/V2

VT = 0.7 VVh = 3 V

02468101214161820

0 1 2 3

Input Signal

1 2

Ron =KPn (Vh-VT-Vsign)W

L

1


Double Switch or transmission gate

nMOST: Vin < VDD-VGS,n ≈ VDD - 0.7 VpMOST: Vin > VGS,p ≈ 0.7 VMinimum Vh = VDD : VDD-VGS,n = VGS,p => VDD > 1.4 V

Switch:

Φ1

Φ1

VinC

Φ1

Φ1

VinC


Double Switch

02468101214161820

0 1 2 3

Input Signal

RnmosRpmosRon

RpMOST RnMOST


Low Voltage SC : MOST-Switch

VDD0 VTpVDD-VTn

nMOSTpMOST

1.3 V

?

VDD-VGS

VDD0 VTp VDD-VTn

nMOSTpMOST

3 VgDS gDS


Low Voltage SC : MOST-Switch

0 1.0 2.0 3.0 4.0 5.0VIN

4.0 k

3.0 k

2.0 k

0 0.5 1.0 1.5 2.0VIN

60 k

40 k

20 k

0 k

VDD =5 V

VDD =1.8 V

Ron


Time constant of Ron

Vin

time

Vout

ε

ts

Vout = Vin (1-exp(- ))

ts = RC ln(1/ε)ts ≈ 7 RC for ε = 0.1 %

Speed if large C (low noise)large R (small switch)

1Vin VoutVin

RCtRonVout

C C


For W/L = 2 and VGS-VT ≈ 1 VRon ≈ 10 kΩFor C ≈ 1 pFFor ε ≈ 0.1% ts = 7 RC ≈ 70 nsTc = 140 ns fmax ≈ 7 MHz

Maximum frequency of operation

Due to only one switch

practical fmax : 1-10 MHz

φ1

Tmax = 1/fmax

ts

L Ron


For Cmin ≈ 0.25 pF (mismatch)∆Vc = 1% of 0.1 V or ∆Vc = 1 mV dt = Tc/2 with Tc = 1/fcmin

Minimum frequency of operation

φ1 φ1φ2 φ2

VC

t0

∆VC

Tc

Leakage i = CdVC

dti is 10 nA/cm2 at 25o

is 10 µA/cm2 at 125o

For 10x1 µm: 2 fA (25o)or 2 pA (125o)

fcmin =i

2 Cmin ∆Vc= 4 Hz or 4 kHz (125o)


Clock Feed-Through

Overlap Capacitors Covl ≈ W Covlo

W ↑ ⇒ R ↓ but Covl ↑

Example : W = 3µm L = 0.7µm Covlo = 0.5 fF/µm

⇒ Covl ≈ 1 fF

∆V: Q = Covl (Vh-Vl) ≈ 1fF. 3V ≈ 3fC

⇒ ∆V ≈ ≈ 3fC/1pF ≈ 3 mVQC

Covl

C


Charge redistribution

Inversion layer charge Qm ≈ CoxWL(Vh-Vsign-VT)

Ex. W = 3µm L = 0.7µm Cox = 1.6 fF/µm2

VT = 0.7V Vsign = 1.5V

⇒ Q ≈ 6 fC∆V: Half is stored in each cap⇒ ∆V ≈ Q/2C ≈ 3 fC/1pF ≈ 3 mV

Total: ∆V ≈ 10 mV/pF C ↑ ⇒ CD ↓ Speed ↓ Power ↑


Clock injection & Charge redistribution

If Covl,n = Covl,p

No Clock FT !

Problems: matchingWn = Wp ?

Φ

Φ

Φ

Φ

Dummy Switch

6/0.7

3/0.7

OK if Q is split equal 1/2

Problems: clock skewrise/fall timeimpedance


Quantitative Charge Redistribution

Ci/C

Ci >> C, B >>1 ∆Q 0

NO dummy

Ci << C, B >>1∆Q QDummy

Ci = C: ∆Q=Q/2Dummy

B<<1 : ∆Q=Q/2 Dummy

High Speed Clocks

Low Speed Clocks

Ref. Wegmann, Vittoz, JSSC Dec.87, 1091-1097

β = µCox.W/La = dV/dtVTe = effective VT (with bulk effect)


Layout considerations

Reduce Cox area Use metal to ‘shield’

clock lines

Parasitic C⇓

CFT










Sampling analog signals

VoutVin

Φ1

Φ1

C

Vin

Vout


Spectra

Input signal vin

Sampled signal fc/2 >> fsignal

Sampled signal fc/2 < fsignalNyquist !

fs

fs fc

fs fc fc 3fc

f

f

f

fc/2

fs

|Vin|

|Vout|

|Vout|


Anti-Aliasing filter

fcfs ffc-fs


Anti-aliasing / Reconstruction

N-order filter:N

fsfc − fs[ ] =

−Attenuation2010 fc = fs.

Attenuation20.N10

Ex. Attenuation = 40 dB; fs = 10 kHz ; N = 1 fc = 1 MHz


Sampled Data Basics : z-transform

Analog System: s = jω

Sampled data: z-transforms1 delay is z-1

z = e = ejωTc j2πf

e = 1 + jωTc + jωTc (jωTc)2

2

VoutVin

11 + sRC

=

fc

R C

+ …… if ωTc << 1


SC-Integrator in phase 1

+-

RC

Vout(s) =−Vin(s)sRC

+-1 2

C

aC

timetntn-1/2tn-1

Φ1

Φ2Φ1 QaC1 = aC Vin(n-1/2)

QC1 = - C Vout (n-1)Vout(n-1/2) = Vout(n-1)


SC-Integrator in phase 2 : charge conservation

+-

RC

Vout(s) =−Vin(s)sRC

+-1 2

C

aC

timetntn-1/2tn-1

Φ1

Φ2 Φ2

- C Vout (n) = aC Vin (n-1/2) - C Vout (n-1)

QaC2 = 0QC2 = - C Vout (n)

QaC2 +QC2 = QaC1 +QC1


SC-Integrator : approximate transfer function

- C Vout (n) = aC Vin (n-1/2) - C Vout (n-1)

Vout (n-1) = z-1 Vout

C.Vout = z-1 C Vout - z-1/2 aC Vin

⇒VoutVin

≈ −a(1− jωTc/ 2)

jωTc≈ −

ajωTc

Integrator

RC = aTc

= - az-1/2

1 - z-1

Vout

Vinz-1 = e ≈ 1 - jωTc

-jωTc


Exact Transfer function

Euler’s relationship:

sin(x) =+ jxe − − jxe2 j

f/fc = 0.1error ≈ 0.1%

H(z) = -az-1/2

1 - z-1

H(e ) = -ae1 - e

jωTc-jωTc/2

-jωTc

H(e ) = -a

e - ejωTc

jωTc/2

jωTc

-jωTc/2

H(e ) = -ajωTc ωTc/2

sin(ωTc/2)


The sin(x)/x function

x

sin(x) ≈ x - + .. x3

3

sin(x) ≈ 1 - + ..x2

3

For x = 0.1sin(x)/x ≈ 1 - 0.003

For x = 0.05sin(x)/x ≈ 1 - 0.0008

≈ 1 - 0.001










Stray Capacitances

+-1 2

C

aC

Stray Cap at input:Substrate couplingContinuous timePSRR very bad

Stray Cap at output:Cp is extra load

for opamp


Stray Capacitances

+-1 2

CaC

Cp ≈ 2.CjS.Area ≈ 20 fF

Gain =aC + 2Cp

C

error ≈2CpaC

≈ 5 −10%


Stray Insensitive SC integrator

+-1 2

C2 = CC1 = aC

12

Av =C1C2

= a

vIN+

-vOUT



+-

CaC

Av =C1C2

= a

vIN+

-vOUT

Φ1



+-

CaC

Av =C1C2

= a

vIN+

-vOUT

Φ2


Stray Insensitive Integrator during phase 1

+-1 2

CaC

12

Φ1 aC

Q = 0 no effectQaC = aC VinQcp = Cp Vin

Av =C1C2

τ =1afc

CpCp

Cp Cp

= a


Stray Insensitive Integrator during phase 2

+-1 2

CaC

12

Φ2 aC

Qcp is discharged

to gnd Virtual groundQcp remains 0Only QaC is transferred

CpCp

Cp Cp

+-

C










Loss-less Integrators

-

1 2

C1

C2

+

H(z) =C1

C2

z-1

1 - z-1

12

2

1H(z) =

C1

C2

z-1/2

1 - z-1

H(z) = -C1

C2

z-1/2

1 - z-1

H(z) = -C1

C2

11 - z-1

-

1

2

C1

C2

+1

2

2

1


Low-pass filter of 1st order

-1 2

1 2

C1

C2+

Av =C1C2

BW =fc

2π

vINvOUT

C

C2C

Damped because of R//C !


Damped integrators

Non-inverting damped integrator

Inverting Damped integrator

-

(c)


Offset compensation

-1

aC+2

21vIN

vOUTvos

1

+-

C

Av = a z-1/2

independent of vos

Gregorian, IEEE Proc. Aug 83, 941-986


Offset compensation

-

aC

+vIN

vOUTvos+-

C

QaC1 = aC (vos - vIN(n-1/2))QC1 = C vos

-

aC

+vos+-

Φ1 Φ2

+

+

vOUT

Av = a z-1/2

QaC2 = aC vosQC2 = C (vos - vOUT(n))

QaC1 + QC1 = QaC2 + QC2

C








• Switched-current filters

Gregorian, Temes, Analog MOS Integrated Circuits for Signal Processing, Wiley, 1986

Laker, Sansen, Design of Analog Integrated Circuits and Systems, McGrawHill, 1994

Johns, Martin, Analog Integrated CircuitDesign, Wiley 1997


Capacitors

SwitchesOpamps

Clock

Clock freq 100 kHzCut-off 5 kHzPass ripple 0.25dBStop reject >45 dBPower 190µW (± 2.5V)S/N 75 dBHarm dist 0.25%Area 0.9 mm2

4th Order SC low-pass ladder filter


Biquadratic filter










Opamp parameters

A0

1

|A|

fd f

Loop gain (1+T) ≈ T

GBW

Feedback factor α

Ac0 = 1/ α

T = A0 / Ac0 = α A0 Ac0

BW = α GBW

BW

GBW = gm

2π Ceff

α


Static error

Vout , t = ∞ = −Ao.Vstep1 +α.Ao

εS =Vstep /α −VoutVstep /α

=1−Ao

1+ Ao.α≈

1α .Ao

Ao >1

α.εSMinimum Gain

ε = 0.05%

A0 ≈ 1-10k≈ 60-80 dB


Dynamic error

εD = EXP(−α.gm.tSCL, ef

)

GBW >fc

π.αln(1εD)Minimum GBW:

GBW =gm2πCL, ef

εD = EXP(−α.2π.GBW.tS) tS =12 fc

GBW =1

α.2π .tSln(1εD) =

2 fc2π.α

ln(1εD)

ε = 0.05%

GBW ≈ 2-3*fc










kT/C versus kTR noise

Narrow-band noise >> noise density : dvni2 = 4kT R df

kTC

Wide-band noise >> integrated noise : vni2 =

fc GBW

dvni2

vni2 =

kTC

GBW

f

fc/2

2fc 3fcfc2










Switched-current delay block

Ref. Zele JSSC Feb. 96, 157- 168

M1 M2

IBIB

Iout

1 : 1

IinSwitch closed : track VGS

Iout = IinClock

Switch open : hold VGSIout = Iin (∆Tc)

Iout = Iin z-1/2


Switched-current low-pass filter

Ref. Zele JSSC Feb. 96, 157- 168

M1 M2 IB

IBiout = Kif

1 : 1

if

if = if z-1 - iin z-1/2K z-1/2

1 - z-1

Clock1 Clock2

iin

ioutiin

=

1 : K

KIB

if


2nd-generation switched-current filter

A1z-1

1 - Bz-1io(z) = i1(z) - i2(z) -

A2z-1

1 - Bz-1

A3(1-z-1)

1 - Bz-1i3(z)

A1 = 1 + α4

α1

A2 = 1 + α4

α2

A3 = 1 + α4

α3

B = 1 + α4

1


Comparison SC - SI

SC SI

Signal : Voltage CurrentCharge on linear C Charge on MOST CGS

Q = C V Q = I tAccuracy : Capacitor ratio MOST area ratio

0.2 % 2 %Amps : Opamps Current mirrorsS/N+D 70 dB 50 dB









Documents

Switched-capacitor filters - Extra Materialsextras.springer.com/2006/978-0-387-25746-4/Chapter_17.pdf · SC ladder filter. Willy Sansen 10-05 N177 ... Sampled Data Basics : z-transform