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EE C245 Surface Micromachining III Dr. Thara Srinivasan Lecture 5 Picture credit: Sandia National Lab 2 U. Srinivasan © EE C245 Lecture Outline Reading From reader: Bustillo, J. et al., “Surface Micromachining of Microelectromechanical Systems,” pp. 1564-9. Problem set #2 on website, due next Tuesday 9/16 MUMPS Labs after class: 4-5, 5-6 pm Where Prof. Howe’s grad students demonstrate MUMPS devices and you help… 6-10 students per session Today’s Lecture MEMS Test Structures for Film Characterization (from Lecture 4) Stiction and Friction in MEMS (from Lecture 4) 3-D Microstructures

Surface Micromachining III · 2003. 9. 11. · Brosnihan et al. Analog Devices 14 U. Srinivasan ... Title: Microsoft PowerPoint - 3Micromachining_surface2 Author: Uthara Srinivasan

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Page 1: Surface Micromachining III · 2003. 9. 11. · Brosnihan et al. Analog Devices 14 U. Srinivasan ... Title: Microsoft PowerPoint - 3Micromachining_surface2 Author: Uthara Srinivasan

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Surface Micromachining III

Dr. Thara SrinivasanLecture 5

Picture credit: Sandia National Lab

2U. Srinivasan ©

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Lecture Outline

• Reading• From reader: Bustillo, J. et al., “Surface Micromachining of

Microelectromechanical Systems,” pp. 1564-9.

• Problem set #2 on website, due next Tuesday 9/16

• MUMPS Labs after class: 4-5, 5-6 pm• Where Prof. Howe’s grad students demonstrate MUMPS devices and you

help…• 6-10 students per session

• Today’s Lecture• MEMS Test Structures for Film Characterization (from Lecture 4)• Stiction and Friction in MEMS (from Lecture 4)• 3-D Microstructures

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• Today’s Lecture• MEMS Test Structures for Film Characterization (from Lecture 4)• Stiction and Friction in MEMS (from Lecture 4)• 3-D Microstructures

Lecture Outline

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• Today’s Lecture• MEMS Test Structures for Film Characterization (from Lecture 4)• Stiction and Friction in MEMS (from Lecture 4)• 3-D Microstructures

Lecture Outline

Page 3: Surface Micromachining III · 2003. 9. 11. · Brosnihan et al. Analog Devices 14 U. Srinivasan ... Title: Microsoft PowerPoint - 3Micromachining_surface2 Author: Uthara Srinivasan

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53-D Microstructures

• Approaches• Hinges• Molding: Hexsil• Silicon-on-Insulator Process• Sealed-cavity Deep RIE Process• SCREAM

StaplePolysilicon level 2

Polysilicon level 1

Silicon substrate

Polysilicon level 1

Polysilicon level 2

Hinge staple

Plate

Silicon substrate

Support arm K.S.J. Pister et al., Sensors and Actuators A, Vol. A33, p. 249, 1992.

Hexsil molding

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Hinge Process FlowDeposit first sacrificialDeposit and pattern first poly

Pattern contactsDeposit and pattern second poly

Deposit and pattern second sacrificial

Etch sacrificialAssemble part

Pister

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Pop-Up MEMS

First MEMS hinge, K. Pister, et al. 1992

Corner Cube Reflector : V. Hsu, 1999

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Pop-Up MEMS

Hinged Campanile made in SUMMiT process,

assembled using probes Elliot Hui et al.

Page 5: Surface Micromachining III · 2003. 9. 11. · Brosnihan et al. Analog Devices 14 U. Srinivasan ... Title: Microsoft PowerPoint - 3Micromachining_surface2 Author: Uthara Srinivasan

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5Assembling Hinges

• Assembly using• Grad students’ eyebrows!• Fluidic agitation• On-chip actuators• Magnetic forces• Surface tension of precisely

located droplets

Muller & Lau groups Pister group

Syms, Imperial College

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Deformable Hinges and Flexures

Helmbrecht, Srinivasan et al.

• Flexible hinges• Rigid polySi plates (E =

140 GPa) connected by elastic polyimide hinges (E = 3 GPa), Suzuki et al.

• Aluminum hinges fabricated in standard CMOS process, released with XeF2, Pister et al.

• Pop-up flexures• Nickel film has tensile

stress• Nickel-polySi “bimorph”

legs

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5Molding Hexsil

• Makes high aspect ratio structures using conformal thin films in mold trenches

• Parts are demolded(and transferred to another wafer)

• Mold can be reused• Honeycomb

structure

C. Keller et al.

J. Heck, Ph.D.

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Hexsil MEMS

MEMS Precision Instruments

Heck, Muller and Howe

A. Singh et al.

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5Silicon on Insulator Process

• Silicon-on-Insulator (SOI) wafer• Thin layer of SCS (10’s of nm – 10’s of

µm) on oxide layer (few 100’s of nm) on handle Si wafer

• SIMOX• Bonded SOI

• CMOS compatible• Cost: ~$200 per wafer

• Fabrication• Dry etching to pattern Si layer• Etch buried SiO2 to release

Si wafer

SiO2

Si (100) layer

Silicon-on-Insulator wafer

Brosnihan et al.

Analog Devices

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Proof mass 52 µg

SOI Process

Lemkin et al.

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5SCREAM Process (!)

Shaw, MacDonald et al.

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Sealed-cavity Deep RIE Process• Si substrates are polished to

desired thickness, micromachined, and fusion-bonded together in a stack.

200 µm-deep thermal actuator

Lucas NovaSensor